diff --git a/thys/Buchi_Complementation/Complementation_Final.thy b/thys/Buchi_Complementation/Complementation_Final.thy
--- a/thys/Buchi_Complementation/Complementation_Final.thy
+++ b/thys/Buchi_Complementation/Complementation_Final.thy
@@ -1,183 +1,183 @@
 section \<open>Final Instantiation of Algorithms Related to Complementation\<close>
 
 theory Complementation_Final
 imports
   "Complementation_Implement"
   "Formula"
   "Transition_Systems_and_Automata.NBA_Translate"
   "Transition_Systems_and_Automata.NGBA_Algorithms"
   "HOL-Library.Permutation"
 begin
 
   subsection \<open>Syntax\<close>
 
   (* TODO: this syntax has unnecessarily high inner binding strength, requiring extra parentheses
     the regular let syntax correctly uses inner binding strength 0: ("(2_ =/ _)" 10) *)
   no_syntax "_do_let" :: "[pttrn, 'a] \<Rightarrow> do_bind" ("(2let _ =/ _)" [1000, 13] 13)
   syntax "_do_let" :: "[pttrn, 'a] \<Rightarrow> do_bind" ("(2let _ =/ _)" 13)
 
   subsection \<open>Hashcodes on Complement States\<close>
 
   definition "hci k \<equiv> uint32_of_nat k * 1103515245 + 12345"
   definition "hc \<equiv> \<lambda> (p, q, b). hci p + hci q * 31 + (if b then 1 else 0)"
-  definition "list_hash xs \<equiv> fold (bitXOR \<circ> hc) xs 0"
+  definition "list_hash xs \<equiv> fold ((XOR) \<circ> hc) xs 0"
 
   lemma list_hash_eq:
     assumes "distinct xs" "distinct ys" "set xs = set ys"
     shows "list_hash xs = list_hash ys"
   proof -
     have "remdups xs <~~> remdups ys" using eq_set_perm_remdups assms(3) by this
     then have "xs <~~> ys" using assms(1, 2) by (simp add: distinct_remdups_id)
-    then have "fold (bitXOR \<circ> hc) xs a = fold (bitXOR \<circ> hc) ys a" for a
+    then have "fold ((XOR) \<circ> hc) xs a = fold ((XOR) \<circ> hc) ys a" for a
     proof (induct arbitrary: a)
       case (swap y x l)
       have "x XOR y XOR a = y XOR x XOR a" for x y by (transfer) (simp add: word_bw_lcs(3))
       then show ?case by simp
     qed simp+
     then show ?thesis unfolding list_hash_def by this
   qed
 
   definition state_hash :: "nat \<Rightarrow> Complementation_Implement.state \<Rightarrow> nat" where
     "state_hash n p \<equiv> nat_of_hashcode (list_hash p) mod n"
 
   lemma state_hash_bounded_hashcode[autoref_ga_rules]: "is_bounded_hashcode state_rel
     (gen_equals (Gen_Map.gen_ball (foldli \<circ> list_map_to_list)) (list_map_lookup (=))
     (prod_eq (=) (\<longleftrightarrow>))) state_hash"
   proof
     show [param]: "(gen_equals (Gen_Map.gen_ball (foldli \<circ> list_map_to_list)) (list_map_lookup (=))
       (prod_eq (=) (\<longleftrightarrow>)), (=)) \<in> state_rel \<rightarrow> state_rel \<rightarrow> bool_rel" by autoref
     show "state_hash n xs = state_hash n ys" if "xs \<in> Domain state_rel" "ys \<in> Domain state_rel"
       "gen_equals (Gen_Map.gen_ball (foldli \<circ> list_map_to_list))
       (list_map_lookup (=)) (prod_eq (=) (=)) xs ys" for xs ys n
     proof -
       have 1: "distinct (map fst xs)" "distinct (map fst ys)"
         using that(1, 2) unfolding list_map_rel_def list_map_invar_def by (auto simp: in_br_conv)
       have 2: "distinct xs" "distinct ys" using 1 by (auto intro: distinct_mapI)
       have 3: "(xs, map_of xs) \<in> state_rel" "(ys, map_of ys) \<in> state_rel"
         using 1 unfolding list_map_rel_def list_map_invar_def by (auto simp: in_br_conv)
       have 4: "(gen_equals (Gen_Map.gen_ball (foldli \<circ> list_map_to_list)) (list_map_lookup (=))
         (prod_eq (=) (\<longleftrightarrow>)) xs ys, map_of xs = map_of ys) \<in> bool_rel" using 3 by parametricity
       have 5: "map_to_set (map_of xs) = map_to_set (map_of ys)" using that(3) 4 by simp
       have 6: "set xs = set ys" using map_to_set_map_of 1 5 by blast
       show "state_hash n xs = state_hash n ys" unfolding state_hash_def using list_hash_eq 2 6 by metis
     qed
     show "state_hash n x < n" if "1 < n" for n x using that unfolding state_hash_def by simp
   qed
 
   subsection \<open>Complementation\<close>
 
   schematic_goal complement_impl:
     assumes [simp]: "finite (NBA.nodes A)"
     assumes [autoref_rules]: "(Ai, A) \<in> \<langle>Id, nat_rel\<rangle> nbai_nba_rel"
     shows "(?f :: ?'c, op_translate (complement_4 A)) \<in> ?R"
     by (autoref_monadic (plain))
   concrete_definition complement_impl uses complement_impl
 
   theorem complement_impl_correct:
     assumes "finite (NBA.nodes A)"
     assumes "(Ai, A) \<in> \<langle>Id, nat_rel\<rangle> nbai_nba_rel"
     shows "NBA.language (nbae_nba (nbaei_nbae (complement_impl Ai))) =
       streams (nba.alphabet A) - NBA.language A"
     using op_translate_language[OF complement_impl.refine[OF assms]]
     using complement_4_correct[OF assms(1)]
     by simp
 
   subsection \<open>Language Subset\<close>
 
   definition [simp]: "op_language_subset A B \<equiv> NBA.language A \<subseteq> NBA.language B"
 
   lemmas [autoref_op_pat] = op_language_subset_def[symmetric]
 
   schematic_goal language_subset_impl:
     assumes [simp]: "finite (NBA.nodes B)"
     assumes [autoref_rules]: "(Ai, A) \<in> \<langle>Id, nat_rel\<rangle> nbai_nba_rel"
     assumes [autoref_rules]: "(Bi, B) \<in> \<langle>Id, nat_rel\<rangle> nbai_nba_rel"
     shows "(?f :: ?'c, do {
       let AB' = intersect' A (complement_4 B);
       ASSERT (finite (NGBA.nodes AB'));
       RETURN (NGBA.language AB' = {})
     }) \<in> ?R"
 		by (autoref_monadic (plain))
   concrete_definition language_subset_impl uses language_subset_impl
   lemma language_subset_impl_refine[autoref_rules]:
     assumes "SIDE_PRECOND (finite (NBA.nodes A))"
     assumes "SIDE_PRECOND (finite (NBA.nodes B))"
     assumes "SIDE_PRECOND (nba.alphabet A \<subseteq> nba.alphabet B)"
     assumes "(Ai, A) \<in> \<langle>Id, nat_rel\<rangle> nbai_nba_rel"
     assumes "(Bi, B) \<in> \<langle>Id, nat_rel\<rangle> nbai_nba_rel"
     shows "(language_subset_impl Ai Bi, (OP op_language_subset :::
       \<langle>Id, nat_rel\<rangle> nbai_nba_rel \<rightarrow> \<langle>Id, nat_rel\<rangle> nbai_nba_rel \<rightarrow> bool_rel) $ A $ B) \<in> bool_rel"
   proof -
     have "(RETURN (language_subset_impl Ai Bi), do {
       let AB' = intersect' A (complement_4 B);
       ASSERT (finite (NGBA.nodes AB'));
       RETURN (NGBA.language AB' = {})
     }) \<in> \<langle>bool_rel\<rangle> nres_rel"
       using language_subset_impl.refine assms(2, 4, 5) unfolding autoref_tag_defs by this
     also have "(do {
       let AB' = intersect' A (complement_4 B);
       ASSERT (finite (NGBA.nodes AB'));
       RETURN (NGBA.language AB' = {})
     }, RETURN (NBA.language A \<subseteq> NBA.language B)) \<in> \<langle>bool_rel\<rangle> nres_rel"
     proof refine_vcg
       show "finite (NGBA.nodes (intersect' A (complement_4 B)))" using assms(1, 2) by auto
       have 1: "NBA.language A \<subseteq> streams (nba.alphabet B)"
         using nba.language_alphabet streams_mono2 assms(3) unfolding autoref_tag_defs by blast
       have 2: "NBA.language (complement_4 B) = streams (nba.alphabet B) - NBA.language B"
         using complement_4_correct assms(2) by auto
       show "(NGBA.language (intersect' A (complement_4 B)) = {},
         NBA.language A \<subseteq> NBA.language B) \<in> bool_rel" using 1 2 by auto
     qed
     finally show ?thesis using RETURN_nres_relD unfolding nres_rel_comp by force
   qed
 
   subsection \<open>Language Equality\<close>
 
   definition [simp]: "op_language_equal A B \<equiv> NBA.language A = NBA.language B"
 
   lemmas [autoref_op_pat] = op_language_equal_def[symmetric]
 
   schematic_goal language_equal_impl:
     assumes [simp]: "finite (NBA.nodes A)"
     assumes [simp]: "finite (NBA.nodes B)"
     assumes [simp]: "nba.alphabet A = nba.alphabet B"
     assumes [autoref_rules]: "(Ai, A) \<in> \<langle>Id, nat_rel\<rangle> nbai_nba_rel"
     assumes [autoref_rules]: "(Bi, B) \<in> \<langle>Id, nat_rel\<rangle> nbai_nba_rel"
     shows "(?f :: ?'c, NBA.language A \<subseteq> NBA.language B \<and> NBA.language B \<subseteq> NBA.language A) \<in> ?R"
     by autoref
   concrete_definition language_equal_impl uses language_equal_impl
   lemma language_equal_impl_refine[autoref_rules]:
     assumes "SIDE_PRECOND (finite (NBA.nodes A))"
     assumes "SIDE_PRECOND (finite (NBA.nodes B))"
     assumes "SIDE_PRECOND (nba.alphabet A = nba.alphabet B)"
     assumes "(Ai, A) \<in> \<langle>Id, nat_rel\<rangle> nbai_nba_rel"
     assumes "(Bi, B) \<in> \<langle>Id, nat_rel\<rangle> nbai_nba_rel"
     shows "(language_equal_impl Ai Bi, (OP op_language_equal :::
       \<langle>Id, nat_rel\<rangle> nbai_nba_rel \<rightarrow> \<langle>Id, nat_rel\<rangle> nbai_nba_rel \<rightarrow> bool_rel) $ A $ B) \<in> bool_rel"
     using language_equal_impl.refine[OF assms[unfolded autoref_tag_defs]] by auto
 
   schematic_goal product_impl:
     assumes [simp]: "finite (NBA.nodes B)"
     assumes [autoref_rules]: "(Ai, A) \<in> \<langle>Id, nat_rel\<rangle> nbai_nba_rel"
     assumes [autoref_rules]: "(Bi, B) \<in> \<langle>Id, nat_rel\<rangle> nbai_nba_rel"
     shows "(?f :: ?'c, do {
       let AB' = intersect A (complement_4 B);
       ASSERT (finite (NBA.nodes AB'));
       op_translate AB'
     }) \<in> ?R"
 		by (autoref_monadic (plain))
   concrete_definition product_impl uses product_impl
 
   (* TODO: possible optimizations:
     - introduce op_map_map operation for maps instead of manually iterating via FOREACH
     - consolidate various binds and maps in expand_map_get_7 *)
   export_code
     Set.empty Set.insert Set.member
     "Inf :: 'a set set \<Rightarrow> 'a set" "Sup :: 'a set set \<Rightarrow> 'a set" image Pow set
     nat_of_integer integer_of_nat
     Variable Negation Conjunction Disjunction satisfies map_formula
     nbaei alphabetei initialei transitionei acceptingei
     nbae_nba_impl complement_impl language_equal_impl product_impl
     in SML module_name Complementation file_prefix Complementation
 
 end
\ No newline at end of file
diff --git a/thys/CakeML/generated/CakeML/SemanticPrimitives.thy b/thys/CakeML/generated/CakeML/SemanticPrimitives.thy
--- a/thys/CakeML/generated/CakeML/SemanticPrimitives.thy
+++ b/thys/CakeML/generated/CakeML/SemanticPrimitives.thy
@@ -1,998 +1,998 @@
 chapter \<open>Generated by Lem from \<open>semantics/semanticPrimitives.lem\<close>.\<close>
 
 theory "SemanticPrimitives" 
 
 imports
   Main
   "HOL-Library.Datatype_Records"
   "LEM.Lem_pervasives"
   "LEM.Lem_list_extra"
   "LEM.Lem_string"
   "Lib"
   "Namespace"
   "Ast"
   "Ffi"
   "FpSem"
   "LEM.Lem_string_extra"
 
 begin 
 
 \<comment> \<open>\<open>open import Pervasives\<close>\<close>
 \<comment> \<open>\<open>open import Lib\<close>\<close>
 \<comment> \<open>\<open>import List_extra\<close>\<close>
 \<comment> \<open>\<open>import String\<close>\<close>
 \<comment> \<open>\<open>import String_extra\<close>\<close>
 \<comment> \<open>\<open>open import Ast\<close>\<close>
 \<comment> \<open>\<open>open import Namespace\<close>\<close>
 \<comment> \<open>\<open>open import Ffi\<close>\<close>
 \<comment> \<open>\<open>open import FpSem\<close>\<close>
 
 \<comment> \<open>\<open> The type that a constructor builds is either a named datatype or an exception.
  * For exceptions, we also keep the module that the exception was declared in. \<close>\<close>
 datatype tid_or_exn =
     TypeId " (modN, typeN) id0 "
   | TypeExn " (modN, conN) id0 "
 
 \<comment> \<open>\<open>val type_defs_to_new_tdecs : list modN -> type_def -> set tid_or_exn\<close>\<close>
 definition type_defs_to_new_tdecs  :: "(string)list \<Rightarrow>((tvarN)list*string*(conN*(t)list)list)list \<Rightarrow>(tid_or_exn)set "  where 
      " type_defs_to_new_tdecs mn tdefs = (
   List.set (List.map ( \<lambda>x .  
   (case  x of (tvs,tn,ctors) => TypeId (mk_id mn tn) )) tdefs))"
 
 
 datatype_record 'v sem_env =
   
  v ::" (modN, varN, 'v) namespace "
    
  c ::" (modN, conN, (nat * tid_or_exn)) namespace "
    
 
 
 \<comment> \<open>\<open> Value forms \<close>\<close>
 datatype v =
     Litv " lit "
   \<comment> \<open>\<open> Constructor application. \<close>\<close>
   | Conv "  (conN * tid_or_exn)option " " v list "
   \<comment> \<open>\<open> Function closures
      The environment is used for the free variables in the function \<close>\<close>
   | Closure " v sem_env " " varN " " exp0 "
   \<comment> \<open>\<open> Function closure for recursive functions
    * See Closure and Letrec above
    * The last variable name indicates which function from the mutually
    * recursive bundle this closure value represents \<close>\<close>
   | Recclosure " v sem_env " " (varN * varN * exp0) list " " varN "
   | Loc " nat "
   | Vectorv " v list "
 
 type_synonym env_ctor =" (modN, conN, (nat * tid_or_exn)) namespace "
 type_synonym env_val =" (modN, varN, v) namespace "
 
 definition Bindv  :: " v "  where 
      " Bindv = ( Conv (Some((''Bind''),TypeExn(Short(''Bind'')))) [])"
 
 
 \<comment> \<open>\<open> The result of evaluation \<close>\<close>
 datatype abort =
     Rtype_error
   | Rtimeout_error
 
 datatype 'a error_result =
     Rraise " 'a " \<comment> \<open>\<open> Should only be a value of type exn \<close>\<close>
   | Rabort " abort "
 
 datatype( 'a, 'b) result =
     Rval " 'a "
   | Rerr " 'b error_result "
 
 \<comment> \<open>\<open> Stores \<close>\<close>
 datatype 'a store_v =
   \<comment> \<open>\<open> A ref cell \<close>\<close>
     Refv " 'a "
   \<comment> \<open>\<open> A byte array \<close>\<close>
   | W8array " 8 word list "
   \<comment> \<open>\<open> An array of values \<close>\<close>
   | Varray " 'a list "
 
 \<comment> \<open>\<open>val store_v_same_type : forall 'a. store_v 'a -> store_v 'a -> bool\<close>\<close>
 definition store_v_same_type  :: " 'a store_v \<Rightarrow> 'a store_v \<Rightarrow> bool "  where 
      " store_v_same_type v1 v2 = (
   (case  (v1,v2) of
     (Refv _, Refv _) => True
   | (W8array _,W8array _) => True
   | (Varray _,Varray _) => True
   | _ => False
   ))"
 
 
 \<comment> \<open>\<open> The nth item in the list is the value at location n \<close>\<close>
 type_synonym 'a store =" ( 'a store_v) list "
 
 \<comment> \<open>\<open>val empty_store : forall 'a. store 'a\<close>\<close>
 definition empty_store  :: "('a store_v)list "  where 
      " empty_store = ( [])"
 
 
 \<comment> \<open>\<open>val store_lookup : forall 'a. nat -> store 'a -> maybe (store_v 'a)\<close>\<close>
 definition store_lookup  :: " nat \<Rightarrow>('a store_v)list \<Rightarrow>('a store_v)option "  where 
      " store_lookup l st = (
   if l < List.length st then
     Some (List.nth st l)
   else
     None )"
 
 
 \<comment> \<open>\<open>val store_alloc : forall 'a. store_v 'a -> store 'a -> store 'a * nat\<close>\<close>
 definition store_alloc  :: " 'a store_v \<Rightarrow>('a store_v)list \<Rightarrow>('a store_v)list*nat "  where 
      " store_alloc v2 st = (
   ((st @ [v2]), List.length st))"
 
 
 \<comment> \<open>\<open>val store_assign : forall 'a. nat -> store_v 'a -> store 'a -> maybe (store 'a)\<close>\<close>
 definition store_assign  :: " nat \<Rightarrow> 'a store_v \<Rightarrow>('a store_v)list \<Rightarrow>(('a store_v)list)option "  where 
      " store_assign n v2 st = (
   if (n < List.length st) \<and>
      store_v_same_type (List.nth st n) v2
   then
     Some (List.list_update st n v2)
   else
     None )"
 
 
 datatype_record 'ffi state =
   
  clock ::" nat "
    
  refs  ::" v store "
    
  ffi ::" 'ffi ffi_state "
    
  defined_types ::" tid_or_exn set "
    
  defined_mods ::" ( modN list) set "
    
 
 
 \<comment> \<open>\<open> Other primitives \<close>\<close>
 \<comment> \<open>\<open> Check that a constructor is properly applied \<close>\<close>
 \<comment> \<open>\<open>val do_con_check : env_ctor -> maybe (id modN conN) -> nat -> bool\<close>\<close>
 fun do_con_check  :: "((string),(string),(nat*tid_or_exn))namespace \<Rightarrow>(((string),(string))id0)option \<Rightarrow> nat \<Rightarrow> bool "  where 
      " do_con_check cenv None l = ( True )"
 |" do_con_check cenv (Some n) l = (
         (case  nsLookup cenv n of
             None => False
           | Some (l',ns) => l = l'
         ))"
 
 
 \<comment> \<open>\<open>val build_conv : env_ctor -> maybe (id modN conN) -> list v -> maybe v\<close>\<close>
 fun build_conv  :: "((string),(string),(nat*tid_or_exn))namespace \<Rightarrow>(((string),(string))id0)option \<Rightarrow>(v)list \<Rightarrow>(v)option "  where 
      " build_conv envC None vs = (
         Some (Conv None vs))"
 |" build_conv envC (Some id1) vs = (
         (case  nsLookup envC id1 of
             None => None
           | Some (len,t1) => Some (Conv (Some (id_to_n id1, t1)) vs)
         ))"
 
 
 \<comment> \<open>\<open>val lit_same_type : lit -> lit -> bool\<close>\<close>
 definition lit_same_type  :: " lit \<Rightarrow> lit \<Rightarrow> bool "  where 
      " lit_same_type l1 l2 = (
   (case  (l1,l2) of
       (IntLit _, IntLit _) => True
     | (Char _, Char _) => True
     | (StrLit _, StrLit _) => True
     | (Word8 _, Word8 _) => True
     | (Word64 _, Word64 _) => True
     | _ => False
   ))"
 
 
 datatype 'a match_result =
     No_match
   | Match_type_error
   | Match " 'a "
 
 \<comment> \<open>\<open>val same_tid : tid_or_exn -> tid_or_exn -> bool\<close>\<close>
 fun  same_tid  :: " tid_or_exn \<Rightarrow> tid_or_exn \<Rightarrow> bool "  where 
      " same_tid (TypeId tn1) (TypeId tn2) = ( tn1 = tn2 )"
 |" same_tid (TypeExn _) (TypeExn _) = ( True )"
 |" same_tid _ _ = ( False )"
 
 
 \<comment> \<open>\<open>val same_ctor : conN * tid_or_exn -> conN * tid_or_exn -> bool\<close>\<close>
 fun  same_ctor  :: " string*tid_or_exn \<Rightarrow> string*tid_or_exn \<Rightarrow> bool "  where 
      " same_ctor (cn1, TypeExn mn1) (cn2, TypeExn mn2) = ( (cn1 = cn2) \<and> (mn1 = mn2))"
 |" same_ctor (cn1, _) (cn2, _) = ( cn1 = cn2 )"
 
 
 \<comment> \<open>\<open>val ctor_same_type : maybe (conN * tid_or_exn) -> maybe (conN * tid_or_exn) -> bool\<close>\<close>
 definition ctor_same_type  :: "(string*tid_or_exn)option \<Rightarrow>(string*tid_or_exn)option \<Rightarrow> bool "  where 
      " ctor_same_type c1 c2 = (
   (case  (c1,c2) of
       (None, None) => True
     | (Some (_,t1), Some (_,t2)) => same_tid t1 t2
     | _ => False
   ))"
 
 
 \<comment> \<open>\<open> A big-step pattern matcher.  If the value matches the pattern, return an
  * environment with the pattern variables bound to the corresponding sub-terms
  * of the value; this environment extends the environment given as an argument.
  * No_match is returned when there is no match, but any constructors
  * encountered in determining the match failure are applied to the correct
  * number of arguments, and constructors in corresponding positions in the
  * pattern and value come from the same type.  Match_type_error is returned
  * when one of these conditions is violated \<close>\<close>
 \<comment> \<open>\<open>val pmatch : env_ctor -> store v -> pat -> v -> alist varN v -> match_result (alist varN v)\<close>\<close>
 function (sequential,domintros) 
 pmatch_list  :: "((string),(string),(nat*tid_or_exn))namespace \<Rightarrow>((v)store_v)list \<Rightarrow>(pat)list \<Rightarrow>(v)list \<Rightarrow>(string*v)list \<Rightarrow>((string*v)list)match_result "  
                    and
 pmatch  :: "((string),(string),(nat*tid_or_exn))namespace \<Rightarrow>((v)store_v)list \<Rightarrow> pat \<Rightarrow> v \<Rightarrow>(string*v)list \<Rightarrow>((string*v)list)match_result "  where 
      "
 pmatch envC s Pany v' env = ( Match env )"
 |"
 pmatch envC s (Pvar x) v' env = ( Match ((x,v')# env))"
 |"
 pmatch envC s (Plit l) (Litv l') env = (
   if l = l' then
     Match env
   else if lit_same_type l l' then
     No_match
   else
     Match_type_error )"
 |"
 pmatch envC s (Pcon (Some n) ps) (Conv (Some (n', t')) vs) env = (
   (case  nsLookup envC n of
       Some (l, t1) =>
         if same_tid t1 t' \<and> (List.length ps = l) then
           if same_ctor (id_to_n n, t1) (n',t') then
             if List.length vs = l then
               pmatch_list envC s ps vs env
             else
               Match_type_error
           else
             No_match
         else
           Match_type_error
     | _ => Match_type_error
   ))"
 |"
 pmatch envC s (Pcon None ps) (Conv None vs) env = (
   if List.length ps = List.length vs then
     pmatch_list envC s ps vs env
   else
     Match_type_error )"
 |"
 pmatch envC s (Pref p) (Loc lnum) env = (
   (case  store_lookup lnum s of
       Some (Refv v2) => pmatch envC s p v2 env
     | Some _ => Match_type_error
     | None => Match_type_error
   ))"
 |"
 pmatch envC s (Ptannot p t1) v2 env = (
   pmatch envC s p v2 env )"
 |"
 pmatch envC _ _ _ env = ( Match_type_error )"
 |"
 pmatch_list envC s [] [] env = ( Match env )"
 |"
 pmatch_list envC s (p # ps) (v2 # vs) env = (
   (case  pmatch envC s p v2 env of
       No_match => No_match
     | Match_type_error => Match_type_error
     | Match env' => pmatch_list envC s ps vs env'
   ))"
 |"
 pmatch_list envC s _ _ env = ( Match_type_error )" 
 by pat_completeness auto
 
 
 \<comment> \<open>\<open> Bind each function of a mutually recursive set of functions to its closure \<close>\<close>
 \<comment> \<open>\<open>val build_rec_env : list (varN * varN * exp) -> sem_env v -> env_val -> env_val\<close>\<close>
 definition build_rec_env  :: "(varN*varN*exp0)list \<Rightarrow>(v)sem_env \<Rightarrow>((string),(string),(v))namespace \<Rightarrow>((string),(string),(v))namespace "  where 
      " build_rec_env funs cl_env add_to_env = (
   List.foldr ( \<lambda>x .  
   (case  x of
       (f,x,e) => \<lambda> env' .  nsBind f (Recclosure cl_env funs f) env'
   )) funs add_to_env )"
 
 
 \<comment> \<open>\<open> Lookup in the list of mutually recursive functions \<close>\<close>
 \<comment> \<open>\<open>val find_recfun : forall 'a 'b. varN -> list (varN * 'a * 'b) -> maybe ('a * 'b)\<close>\<close>
 fun  find_recfun  :: " string \<Rightarrow>(string*'a*'b)list \<Rightarrow>('a*'b)option "  where 
      " find_recfun n ([]) = ( None )"
 |" find_recfun n ((f,x,e) # funs) = (
         if f = n then
           Some (x,e)
         else
           find_recfun n funs )"
 
 
 datatype eq_result =
     Eq_val " bool "
   | Eq_type_error
 
 \<comment> \<open>\<open>val do_eq : v -> v -> eq_result\<close>\<close>
 function (sequential,domintros) 
 do_eq_list  :: "(v)list \<Rightarrow>(v)list \<Rightarrow> eq_result "  
                    and
 do_eq  :: " v \<Rightarrow> v \<Rightarrow> eq_result "  where 
      "
 do_eq (Litv l1) (Litv l2) = (
   if lit_same_type l1 l2 then Eq_val (l1 = l2)
   else Eq_type_error )"
 |"
 do_eq (Loc l1) (Loc l2) = ( Eq_val (l1 = l2))"
 |"
 do_eq (Conv cn1 vs1) (Conv cn2 vs2) = (
   if (cn1 = cn2) \<and> (List.length vs1 = List.length vs2) then
     do_eq_list vs1 vs2
   else if ctor_same_type cn1 cn2 then
     Eq_val False
   else
     Eq_type_error )"
 |"
 do_eq (Vectorv vs1) (Vectorv vs2) = (
   if List.length vs1 = List.length vs2 then
     do_eq_list vs1 vs2
   else
     Eq_val False )"
 |"
 do_eq (Closure _ _ _) (Closure _ _ _) = ( Eq_val True )"
 |"
 do_eq (Closure _ _ _) (Recclosure _ _ _) = ( Eq_val True )"
 |"
 do_eq (Recclosure _ _ _) (Closure _ _ _) = ( Eq_val True )"
 |"
 do_eq (Recclosure _ _ _) (Recclosure _ _ _) = ( Eq_val True )"
 |"
 do_eq _ _ = ( Eq_type_error )"
 |"
 do_eq_list [] [] = ( Eq_val True )"
 |"
 do_eq_list (v1 # vs1) (v2 # vs2) = (
   (case  do_eq v1 v2 of
       Eq_type_error => Eq_type_error
     | Eq_val r =>
         if \<not> r then
           Eq_val False
         else
           do_eq_list vs1 vs2
   ))"
 |"
 do_eq_list _ _ = ( Eq_val False )" 
 by pat_completeness auto
 
 
 \<comment> \<open>\<open>val prim_exn : conN -> v\<close>\<close>
 definition prim_exn  :: " string \<Rightarrow> v "  where 
      " prim_exn cn = ( Conv (Some (cn, TypeExn (Short cn))) [])"
 
 
 \<comment> \<open>\<open> Do an application \<close>\<close>
 \<comment> \<open>\<open>val do_opapp : list v -> maybe (sem_env v * exp)\<close>\<close>
 fun do_opapp  :: "(v)list \<Rightarrow>((v)sem_env*exp0)option "  where 
      " do_opapp ([Closure env n e, v2]) = (
       Some (( env (| v := (nsBind n v2(v   env)) |)), e))"
 |" do_opapp ([Recclosure env funs n, v2]) = (
       if allDistinct (List.map ( \<lambda>x .  
   (case  x of (f,x,e) => f )) funs) then
         (case  find_recfun n funs of
             Some (n,e) => Some (( env (| v := (nsBind n v2 (build_rec_env funs env(v   env))) |)), e)
           | None => None
         )
       else
         None )"
 |" do_opapp _ = ( None )"
 
 
 \<comment> \<open>\<open> If a value represents a list, get that list. Otherwise return Nothing \<close>\<close>
 \<comment> \<open>\<open>val v_to_list : v -> maybe (list v)\<close>\<close>
 function (sequential,domintros)  v_to_list  :: " v \<Rightarrow>((v)list)option "  where 
      " v_to_list (Conv (Some (cn, TypeId (Short tn))) []) = (
   if (cn = (''nil'')) \<and> (tn = (''list'')) then
     Some []
   else
     None )"
 |" v_to_list (Conv (Some (cn,TypeId (Short tn))) [v1,v2]) = (
   if (cn = (''::''))  \<and> (tn = (''list'')) then
     (case  v_to_list v2 of
         Some vs => Some (v1 # vs)
       | None => None
     )
   else
     None )"
 |" v_to_list _ = ( None )" 
 by pat_completeness auto
 
 
 \<comment> \<open>\<open>val v_to_char_list : v -> maybe (list char)\<close>\<close>
 function (sequential,domintros)  v_to_char_list  :: " v \<Rightarrow>((char)list)option "  where 
      " v_to_char_list (Conv (Some (cn, TypeId (Short tn))) []) = (
   if (cn = (''nil'')) \<and> (tn = (''list'')) then
     Some []
   else
     None )"
 |" v_to_char_list (Conv (Some (cn,TypeId (Short tn))) [Litv (Char c2),v2]) = (
   if (cn = (''::''))  \<and> (tn = (''list'')) then
     (case  v_to_char_list v2 of
         Some cs => Some (c2 # cs)
       | None => None
     )
   else
     None )"
 |" v_to_char_list _ = ( None )" 
 by pat_completeness auto
 
 
 \<comment> \<open>\<open>val vs_to_string : list v -> maybe string\<close>\<close>
 function (sequential,domintros)  vs_to_string  :: "(v)list \<Rightarrow>(string)option "  where 
      " vs_to_string [] = ( Some (''''))"
 |" vs_to_string (Litv(StrLit s1)# vs) = (
   (case  vs_to_string vs of
     Some s2 => Some (s1 @ s2)
   | _ => None
   ))"
 |" vs_to_string _ = ( None )" 
 by pat_completeness auto
 
 
 \<comment> \<open>\<open>val copy_array : forall 'a. list 'a * integer -> integer -> maybe (list 'a * integer) -> maybe (list 'a)\<close>\<close>
 fun copy_array  :: " 'a list*int \<Rightarrow> int \<Rightarrow>('a list*int)option \<Rightarrow>('a list)option "  where 
      " copy_array (src,srcoff) len d = (
   if (srcoff <( 0 :: int)) \<or> ((len <( 0 :: int)) \<or> (List.length src < nat (abs ( (srcoff + len))))) then None else
     (let copied = (List.take (nat (abs ( len))) (List.drop (nat (abs ( srcoff))) src)) in
     (case  d of
       Some (dst,dstoff) =>
         if (dstoff <( 0 :: int)) \<or> (List.length dst < nat (abs ( (dstoff + len)))) then None else
           Some ((List.take (nat (abs ( dstoff))) dst @
                 copied) @
                 List.drop (nat (abs ( (dstoff + len)))) dst)
     | None => Some copied
     )))"
 
 
 \<comment> \<open>\<open>val ws_to_chars : list word8 -> list char\<close>\<close>
 definition ws_to_chars  :: "(8 word)list \<Rightarrow>(char)list "  where 
      " ws_to_chars ws = ( List.map (\<lambda> w .  (%n. char_of (n::nat))(unat w)) ws )"
 
 
 \<comment> \<open>\<open>val chars_to_ws : list char -> list word8\<close>\<close>
 definition chars_to_ws  :: "(char)list \<Rightarrow>(8 word)list "  where 
      " chars_to_ws cs = ( List.map (\<lambda> c2 .  word_of_int(int(of_char c2))) cs )"
 
 
 \<comment> \<open>\<open>val opn_lookup : opn -> integer -> integer -> integer\<close>\<close>
 fun opn_lookup  :: " opn \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int "  where 
      " opn_lookup Plus = ( (+))"
 |" opn_lookup Minus = ( (-))"
 |" opn_lookup Times = ( (*))"
 |" opn_lookup Divide = ( (div))"
 |" opn_lookup Modulo = ( (mod))"
 
 
 \<comment> \<open>\<open>val opb_lookup : opb -> integer -> integer -> bool\<close>\<close>
 fun opb_lookup  :: " opb \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool "  where 
      " opb_lookup Lt = ( (<))"
 |" opb_lookup Gt = ( (>))"
 |" opb_lookup Leq = ( (\<le>))"
 |" opb_lookup Geq = ( (\<ge>))"
 
 
 \<comment> \<open>\<open>val opw8_lookup : opw -> word8 -> word8 -> word8\<close>\<close>
 fun opw8_lookup  :: " opw \<Rightarrow> 8 word \<Rightarrow> 8 word \<Rightarrow> 8 word "  where 
-     " opw8_lookup Andw = ( Bits.bitAND )"
-|" opw8_lookup Orw = ( Bits.bitOR )"
-|" opw8_lookup Xor = ( Bits.bitXOR )"
+     " opw8_lookup Andw = ( (AND) )"
+|" opw8_lookup Orw = ( (OR) )"
+|" opw8_lookup Xor = ( (XOR) )"
 |" opw8_lookup Add = ( Groups.plus )"
 |" opw8_lookup Sub = ( Groups.minus )"
 
 
 \<comment> \<open>\<open>val opw64_lookup : opw -> word64 -> word64 -> word64\<close>\<close>
 fun opw64_lookup  :: " opw \<Rightarrow> 64 word \<Rightarrow> 64 word \<Rightarrow> 64 word "  where 
-     " opw64_lookup Andw = ( Bits.bitAND )"
-|" opw64_lookup Orw = ( Bits.bitOR )"
-|" opw64_lookup Xor = ( Bits.bitXOR )"
+     " opw64_lookup Andw = ( (AND) )"
+|" opw64_lookup Orw = ( (OR) )"
+|" opw64_lookup Xor = ( (XOR) )"
 |" opw64_lookup Add = ( Groups.plus )"
 |" opw64_lookup Sub = ( Groups.minus )"
 
 
 \<comment> \<open>\<open>val shift8_lookup : shift -> word8 -> nat -> word8\<close>\<close>
 fun shift8_lookup  :: " shift \<Rightarrow> 8 word \<Rightarrow> nat \<Rightarrow> 8 word "  where 
      " shift8_lookup Lsl = ( shiftl )"
 |" shift8_lookup Lsr = ( shiftr )"
 |" shift8_lookup Asr = ( sshiftr )"
 |" shift8_lookup Ror = ( (% a b. word_rotr b a) )"
 
 
 \<comment> \<open>\<open>val shift64_lookup : shift -> word64 -> nat -> word64\<close>\<close>
 fun shift64_lookup  :: " shift \<Rightarrow> 64 word \<Rightarrow> nat \<Rightarrow> 64 word "  where 
      " shift64_lookup Lsl = ( shiftl )"
 |" shift64_lookup Lsr = ( shiftr )"
 |" shift64_lookup Asr = ( sshiftr )"
 |" shift64_lookup Ror = ( (% a b. word_rotr b a) )"
 
 
 \<comment> \<open>\<open>val Boolv : bool -> v\<close>\<close>
 definition Boolv  :: " bool \<Rightarrow> v "  where 
      " Boolv b = ( if b
   then Conv (Some ((''true''), TypeId (Short (''bool'')))) []
   else Conv (Some ((''false''), TypeId (Short (''bool'')))) [])"
 
 
 datatype exp_or_val =
     Exp " exp0 "
   | Val " v "
 
 type_synonym( 'ffi, 'v) store_ffi =" 'v store * 'ffi ffi_state "
 
 \<comment> \<open>\<open>val do_app : forall 'ffi. store_ffi 'ffi v -> op -> list v -> maybe (store_ffi 'ffi v * result v v)\<close>\<close>
 fun do_app  :: "((v)store_v)list*'ffi ffi_state \<Rightarrow> op0 \<Rightarrow>(v)list \<Rightarrow>((((v)store_v)list*'ffi ffi_state)*((v),(v))result)option "  where 
      " do_app ((s:: v store),(t1:: 'ffi ffi_state)) op1 vs = (
   (case  (op1, vs) of
       (Opn op1, [Litv (IntLit n1), Litv (IntLit n2)]) =>
         if ((op1 = Divide) \<or> (op1 = Modulo)) \<and> (n2 =( 0 :: int)) then
           Some ((s,t1), Rerr (Rraise (prim_exn (''Div''))))
         else
           Some ((s,t1), Rval (Litv (IntLit (opn_lookup op1 n1 n2))))
     | (Opb op1, [Litv (IntLit n1), Litv (IntLit n2)]) =>
         Some ((s,t1), Rval (Boolv (opb_lookup op1 n1 n2)))
     | (Opw W8 op1, [Litv (Word8 w1), Litv (Word8 w2)]) =>
         Some ((s,t1), Rval (Litv (Word8 (opw8_lookup op1 w1 w2))))
     | (Opw W64 op1, [Litv (Word64 w1), Litv (Word64 w2)]) =>
         Some ((s,t1), Rval (Litv (Word64 (opw64_lookup op1 w1 w2))))
     | (FP_bop bop, [Litv (Word64 w1), Litv (Word64 w2)]) =>
         Some ((s,t1),Rval (Litv (Word64 (fp_bop bop w1 w2))))
     | (FP_uop uop, [Litv (Word64 w)]) =>
         Some ((s,t1),Rval (Litv (Word64 (fp_uop uop w))))
     | (FP_cmp cmp, [Litv (Word64 w1), Litv (Word64 w2)]) =>
         Some ((s,t1),Rval (Boolv (fp_cmp cmp w1 w2)))
     | (Shift W8 op1 n, [Litv (Word8 w)]) =>
         Some ((s,t1), Rval (Litv (Word8 (shift8_lookup op1 w n))))
     | (Shift W64 op1 n, [Litv (Word64 w)]) =>
         Some ((s,t1), Rval (Litv (Word64 (shift64_lookup op1 w n))))
     | (Equality, [v1, v2]) =>
         (case  do_eq v1 v2 of
             Eq_type_error => None
           | Eq_val b => Some ((s,t1), Rval (Boolv b))
         )
     | (Opassign, [Loc lnum, v2]) =>
         (case  store_assign lnum (Refv v2) s of
             Some s' => Some ((s',t1), Rval (Conv None []))
           | None => None
         )
     | (Opref, [v2]) =>
         (let (s',n) = (store_alloc (Refv v2) s) in
           Some ((s',t1), Rval (Loc n)))
     | (Opderef, [Loc n]) =>
         (case  store_lookup n s of
             Some (Refv v2) => Some ((s,t1),Rval v2)
           | _ => None
         )
     | (Aw8alloc, [Litv (IntLit n), Litv (Word8 w)]) =>
         if n <( 0 :: int) then
           Some ((s,t1), Rerr (Rraise (prim_exn (''Subscript''))))
         else
           (let (s',lnum) =
             (store_alloc (W8array (List.replicate (nat (abs ( n))) w)) s)
           in
             Some ((s',t1), Rval (Loc lnum)))
     | (Aw8sub, [Loc lnum, Litv (IntLit i)]) =>
         (case  store_lookup lnum s of
             Some (W8array ws) =>
               if i <( 0 :: int) then
                 Some ((s,t1), Rerr (Rraise (prim_exn (''Subscript''))))
               else
                 (let n = (nat (abs ( i))) in
                   if n \<ge> List.length ws then
                     Some ((s,t1), Rerr (Rraise (prim_exn (''Subscript''))))
                   else
                     Some ((s,t1), Rval (Litv (Word8 (List.nth ws n)))))
           | _ => None
         )
     | (Aw8length, [Loc n]) =>
         (case  store_lookup n s of
             Some (W8array ws) =>
               Some ((s,t1),Rval (Litv(IntLit(int(List.length ws)))))
           | _ => None
          )
     | (Aw8update, [Loc lnum, Litv(IntLit i), Litv(Word8 w)]) =>
         (case  store_lookup lnum s of
           Some (W8array ws) =>
             if i <( 0 :: int) then
               Some ((s,t1), Rerr (Rraise (prim_exn (''Subscript''))))
             else
               (let n = (nat (abs ( i))) in
                 if n \<ge> List.length ws then
                   Some ((s,t1), Rerr (Rraise (prim_exn (''Subscript''))))
                 else
                   (case  store_assign lnum (W8array (List.list_update ws n w)) s of
                       None => None
                     | Some s' => Some ((s',t1), Rval (Conv None []))
                   ))
         | _ => None
       )
     | (WordFromInt W8, [Litv(IntLit i)]) =>
         Some ((s,t1), Rval (Litv (Word8 (word_of_int i))))
     | (WordFromInt W64, [Litv(IntLit i)]) =>
         Some ((s,t1), Rval (Litv (Word64 (word_of_int i))))
     | (WordToInt W8, [Litv (Word8 w)]) =>
         Some ((s,t1), Rval (Litv (IntLit (int(unat w)))))
     | (WordToInt W64, [Litv (Word64 w)]) =>
         Some ((s,t1), Rval (Litv (IntLit (int(unat w)))))
     | (CopyStrStr, [Litv(StrLit str),Litv(IntLit off),Litv(IntLit len)]) =>
         Some ((s,t1),
         (case  copy_array ( str,off) len None of
           None => Rerr (Rraise (prim_exn (''Subscript'')))
         | Some cs => Rval (Litv(StrLit((cs))))
         ))
     | (CopyStrAw8, [Litv(StrLit str),Litv(IntLit off),Litv(IntLit len),
                     Loc dst,Litv(IntLit dstoff)]) =>
         (case  store_lookup dst s of
           Some (W8array ws) =>
             (case  copy_array ( str,off) len (Some(ws_to_chars ws,dstoff)) of
               None => Some ((s,t1), Rerr (Rraise (prim_exn (''Subscript''))))
             | Some cs =>
               (case  store_assign dst (W8array (chars_to_ws cs)) s of
                 Some s' =>  Some ((s',t1), Rval (Conv None []))
               | _ => None
               )
             )
         | _ => None
         )
     | (CopyAw8Str, [Loc src,Litv(IntLit off),Litv(IntLit len)]) =>
       (case  store_lookup src s of
         Some (W8array ws) =>
         Some ((s,t1),
           (case  copy_array (ws,off) len None of
             None => Rerr (Rraise (prim_exn (''Subscript'')))
           | Some ws => Rval (Litv(StrLit((ws_to_chars ws))))
           ))
       | _ => None
       )
     | (CopyAw8Aw8, [Loc src,Litv(IntLit off),Litv(IntLit len),
                     Loc dst,Litv(IntLit dstoff)]) =>
       (case  (store_lookup src s, store_lookup dst s) of
         (Some (W8array ws), Some (W8array ds)) =>
           (case  copy_array (ws,off) len (Some(ds,dstoff)) of
             None => Some ((s,t1), Rerr (Rraise (prim_exn (''Subscript''))))
           | Some ws =>
               (case  store_assign dst (W8array ws) s of
                 Some s' => Some ((s',t1), Rval (Conv None []))
               | _ => None
               )
           )
       | _ => None
       )
     | (Ord, [Litv (Char c2)]) =>
           Some ((s,t1), Rval (Litv(IntLit(int(of_char c2)))))
     | (Chr, [Litv (IntLit i)]) =>
         Some ((s,t1),
           (if (i <( 0 :: int)) \<or> (i >( 255 :: int)) then
             Rerr (Rraise (prim_exn (''Chr'')))
           else
             Rval (Litv(Char((%n. char_of (n::nat))(nat (abs ( i))))))))
     | (Chopb op1, [Litv (Char c1), Litv (Char c2)]) =>
         Some ((s,t1), Rval (Boolv (opb_lookup op1 (int(of_char c1)) (int(of_char c2)))))
     | (Implode, [v2]) =>
           (case  v_to_char_list v2 of
             Some ls =>
               Some ((s,t1), Rval (Litv (StrLit ( ls))))
           | None => None
           )
     | (Strsub, [Litv (StrLit str), Litv (IntLit i)]) =>
         if i <( 0 :: int) then
           Some ((s,t1), Rerr (Rraise (prim_exn (''Subscript''))))
         else
           (let n = (nat (abs ( i))) in
             if n \<ge> List.length str then
               Some ((s,t1), Rerr (Rraise (prim_exn (''Subscript''))))
             else
               Some ((s,t1), Rval (Litv (Char (List.nth ( str) n)))))
     | (Strlen, [Litv (StrLit str)]) =>
         Some ((s,t1), Rval (Litv(IntLit(int(List.length str)))))
     | (Strcat, [v2]) =>
         (case  v_to_list v2 of
           Some vs =>
             (case  vs_to_string vs of
               Some str =>
                 Some ((s,t1), Rval (Litv(StrLit str)))
             | _ => None
             )
         | _ => None
         )
     | (VfromList, [v2]) =>
           (case  v_to_list v2 of
               Some vs =>
                 Some ((s,t1), Rval (Vectorv vs))
             | None => None
           )
     | (Vsub, [Vectorv vs, Litv (IntLit i)]) =>
         if i <( 0 :: int) then
           Some ((s,t1), Rerr (Rraise (prim_exn (''Subscript''))))
         else
           (let n = (nat (abs ( i))) in
             if n \<ge> List.length vs then
               Some ((s,t1), Rerr (Rraise (prim_exn (''Subscript''))))
             else
               Some ((s,t1), Rval (List.nth vs n)))
     | (Vlength, [Vectorv vs]) =>
         Some ((s,t1), Rval (Litv (IntLit (int (List.length vs)))))
     | (Aalloc, [Litv (IntLit n), v2]) =>
         if n <( 0 :: int) then
           Some ((s,t1), Rerr (Rraise (prim_exn (''Subscript''))))
         else
           (let (s',lnum) =
             (store_alloc (Varray (List.replicate (nat (abs ( n))) v2)) s)
           in
             Some ((s',t1), Rval (Loc lnum)))
     | (AallocEmpty, [Conv None []]) =>
         (let (s',lnum) = (store_alloc (Varray []) s) in
           Some ((s',t1), Rval (Loc lnum)))
     | (Asub, [Loc lnum, Litv (IntLit i)]) =>
         (case  store_lookup lnum s of
             Some (Varray vs) =>
               if i <( 0 :: int) then
                 Some ((s,t1), Rerr (Rraise (prim_exn (''Subscript''))))
               else
                 (let n = (nat (abs ( i))) in
                   if n \<ge> List.length vs then
                     Some ((s,t1), Rerr (Rraise (prim_exn (''Subscript''))))
                   else
                     Some ((s,t1), Rval (List.nth vs n)))
           | _ => None
         )
     | (Alength, [Loc n]) =>
         (case  store_lookup n s of
             Some (Varray ws) =>
               Some ((s,t1),Rval (Litv(IntLit(int(List.length ws)))))
           | _ => None
          )
     | (Aupdate, [Loc lnum, Litv (IntLit i), v2]) =>
         (case  store_lookup lnum s of
           Some (Varray vs) =>
             if i <( 0 :: int) then
               Some ((s,t1), Rerr (Rraise (prim_exn (''Subscript''))))
             else
               (let n = (nat (abs ( i))) in
                 if n \<ge> List.length vs then
                   Some ((s,t1), Rerr (Rraise (prim_exn (''Subscript''))))
                 else
                   (case  store_assign lnum (Varray (List.list_update vs n v2)) s of
                       None => None
                     | Some s' => Some ((s',t1), Rval (Conv None []))
                   ))
         | _ => None
       )
     | (ConfigGC, [Litv (IntLit i), Litv (IntLit j)]) =>
         Some ((s,t1), Rval (Conv None []))
     | (FFI n, [Litv(StrLit conf), Loc lnum]) =>
         (case  store_lookup lnum s of
           Some (W8array ws) =>
             (case  call_FFI t1 n (List.map (\<lambda> c2 .  of_nat(of_char c2)) ( conf)) ws of
               (t', ws') =>
                (case  store_assign lnum (W8array ws') s of
                  Some s' => Some ((s', t'), Rval (Conv None []))
                | None => None
                )
             )
         | _ => None
         )
     | _ => None
   ))"
 
 
 \<comment> \<open>\<open> Do a logical operation \<close>\<close>
 \<comment> \<open>\<open>val do_log : lop -> v -> exp -> maybe exp_or_val\<close>\<close>
 fun do_log  :: " lop \<Rightarrow> v \<Rightarrow> exp0 \<Rightarrow>(exp_or_val)option "  where 
      " do_log And v2 e = ( 
   (case  v2 of
       Litv _ => None
     | Conv m l2 => (case  m of
                        None => None
                      | Some p => (case  p of
                                      (s1,t1) =>
                                  if(s1 = (''true'')) then
                                    ((case  t1 of
                                         TypeId i => (case  i of
                                                         Short s2 =>
                                                     if(s2 = (''bool'')) then
                                                       ((case  l2 of
                                                            [] => Some (Exp e)
                                                          | _ => None
                                                        )) else None
                                                       | Long _ _ => None
                                                     )
                                       | TypeExn _ => None
                                     )) else
                                    (
                                    if(s1 = (''false'')) then
                                      ((case  t1 of
                                           TypeId i2 => (case  i2 of
                                                            Short s4 =>
                                                        if(s4 = (''bool'')) then
                                                          ((case  l2 of
                                                               [] => Some
                                                                     (Val v2)
                                                             | _ => None
                                                           )) else None
                                                          | Long _ _ => 
                                                        None
                                                        )
                                         | TypeExn _ => None
                                       )) else None)
                                  )
                    )
     | Closure _ _ _ => None
     | Recclosure _ _ _ => None
     | Loc _ => None
     | Vectorv _ => None
   ) )"
 |" do_log Or v2 e = ( 
   (case  v2 of
       Litv _ => None
     | Conv m0 l6 => (case  m0 of
                         None => None
                       | Some p0 => (case  p0 of
                                        (s8,t0) =>
                                    if(s8 = (''false'')) then
                                      ((case  t0 of
                                           TypeId i5 => (case  i5 of
                                                            Short s9 =>
                                                        if(s9 = (''bool'')) then
                                                          ((case  l6 of
                                                               [] => Some
                                                                     (Exp e)
                                                             | _ => None
                                                           )) else None
                                                          | Long _ _ => 
                                                        None
                                                        )
                                         | TypeExn _ => None
                                       )) else
                                      (
                                      if(s8 = (''true'')) then
                                        ((case  t0 of
                                             TypeId i8 => (case  i8 of
                                                              Short s11 =>
                                                          if(s11 = (''bool'')) then
                                                            ((case  l6 of
                                                                 [] => 
                                                             Some (Val v2)
                                                               | _ => 
                                                             None
                                                             )) else None
                                                            | Long _ _ => 
                                                          None
                                                          )
                                           | TypeExn _ => None
                                         )) else None)
                                    )
                     )
     | Closure _ _ _ => None
     | Recclosure _ _ _ => None
     | Loc _ => None
     | Vectorv _ => None
   ) )"
 
 
 \<comment> \<open>\<open> Do an if-then-else \<close>\<close>
 \<comment> \<open>\<open>val do_if : v -> exp -> exp -> maybe exp\<close>\<close>
 definition do_if  :: " v \<Rightarrow> exp0 \<Rightarrow> exp0 \<Rightarrow>(exp0)option "  where 
      " do_if v2 e1 e2 = (
   if v2 = (Boolv True) then
     Some e1
   else if v2 = (Boolv False) then
     Some e2
   else
     None )"
 
 
 \<comment> \<open>\<open> Semantic helpers for definitions \<close>\<close>
 
 \<comment> \<open>\<open> Build a constructor environment for the type definition tds \<close>\<close>
 \<comment> \<open>\<open>val build_tdefs : list modN -> list (list tvarN * typeN * list (conN * list t)) -> env_ctor\<close>\<close>
 definition build_tdefs  :: "(string)list \<Rightarrow>((tvarN)list*string*(string*(t)list)list)list \<Rightarrow>((string),(string),(nat*tid_or_exn))namespace "  where 
      " build_tdefs mn tds = (
   alist_to_ns
     (List.rev
       (List.concat
         (List.map
           ( \<lambda>x .  
   (case  x of
       (tvs, tn, condefs) =>
   List.map
     ( \<lambda>x .  (case  x of
                         (conN, ts) =>
                     (conN, (List.length ts, TypeId (mk_id mn tn)))
                     )) condefs
   ))
           tds))))"
 
 
 \<comment> \<open>\<open> Checks that no constructor is defined twice in a type \<close>\<close>
 \<comment> \<open>\<open>val check_dup_ctors : list (list tvarN * typeN * list (conN * list t)) -> bool\<close>\<close>
 definition check_dup_ctors  :: "((tvarN)list*string*(string*(t)list)list)list \<Rightarrow> bool "  where 
      " check_dup_ctors tds = (
   Lem_list.allDistinct ((let x2 = 
   ([]) in  List.foldr
    (\<lambda>x .  (case  x of
                       (tvs, tn, condefs) => \<lambda> x2 .  List.foldr
                                                               (\<lambda>x .  
                                                                (case  x of
                                                                    (n, ts) => 
                                                                \<lambda> x2 . 
                                                                  if True then
                                                                    n # x2
                                                                  else 
                                                                  x2
                                                                )) condefs 
                                                             x2
                   )) tds x2)))"
 
 
 \<comment> \<open>\<open>val combine_dec_result : forall 'a. sem_env v -> result (sem_env v) 'a -> result (sem_env v) 'a\<close>\<close>
 fun combine_dec_result  :: "(v)sem_env \<Rightarrow>(((v)sem_env),'a)result \<Rightarrow>(((v)sem_env),'a)result "  where 
      " combine_dec_result env (Rerr e) = ( Rerr e )"
 |" combine_dec_result env (Rval env') = ( Rval (| v = (nsAppend(v   env')(v   env)), c = (nsAppend(c   env')(c   env)) |) )"
 
 
 \<comment> \<open>\<open>val extend_dec_env : sem_env v -> sem_env v -> sem_env v\<close>\<close>
 definition extend_dec_env  :: "(v)sem_env \<Rightarrow>(v)sem_env \<Rightarrow>(v)sem_env "  where 
      " extend_dec_env new_env env = (
   (| v = (nsAppend(v   new_env)(v   env)), c = (nsAppend(c   new_env)(c   env))  |) )"
 
 
 \<comment> \<open>\<open>val decs_to_types : list dec -> list typeN\<close>\<close>
 definition decs_to_types  :: "(dec)list \<Rightarrow>(string)list "  where 
      " decs_to_types ds = (
   List.concat (List.map (\<lambda> d . 
         (case  d of
             Dtype locs tds => List.map ( \<lambda>x .  
   (case  x of (tvs,tn,ctors) => tn )) tds
           | _ => [] ))
      ds))"
 
 
 \<comment> \<open>\<open>val no_dup_types : list dec -> bool\<close>\<close>
 definition no_dup_types  :: "(dec)list \<Rightarrow> bool "  where 
      " no_dup_types ds = (
   Lem_list.allDistinct (decs_to_types ds))"
 
 
 \<comment> \<open>\<open>val prog_to_mods : list top -> list (list modN)\<close>\<close>
 definition prog_to_mods  :: "(top0)list \<Rightarrow>((string)list)list "  where 
      " prog_to_mods tops = (
   List.concat (List.map (\<lambda> top1 . 
         (case  top1 of
             Tmod mn _ _ => [[mn]]
           | _ => [] ))
      tops))"
 
 
 \<comment> \<open>\<open>val no_dup_mods : list top -> set (list modN) -> bool\<close>\<close>
 definition no_dup_mods  :: "(top0)list \<Rightarrow>((modN)list)set \<Rightarrow> bool "  where 
      " no_dup_mods tops defined_mods2 = (
   Lem_list.allDistinct (prog_to_mods tops) \<and>
   disjnt (List.set (prog_to_mods tops)) defined_mods2 )"
 
 
 \<comment> \<open>\<open>val prog_to_top_types : list top -> list typeN\<close>\<close>
 definition prog_to_top_types  :: "(top0)list \<Rightarrow>(string)list "  where 
      " prog_to_top_types tops = (
   List.concat (List.map (\<lambda> top1 . 
         (case  top1 of
             Tdec d => decs_to_types [d]
           | _ => [] ))
      tops))"
 
 
 \<comment> \<open>\<open>val no_dup_top_types : list top -> set tid_or_exn -> bool\<close>\<close>
 definition no_dup_top_types  :: "(top0)list \<Rightarrow>(tid_or_exn)set \<Rightarrow> bool "  where 
      " no_dup_top_types tops defined_types2 = (
   Lem_list.allDistinct (prog_to_top_types tops) \<and>
   disjnt (List.set (List.map (\<lambda> tn .  TypeId (Short tn)) (prog_to_top_types tops))) defined_types2 )"
 
 end
diff --git a/thys/Native_Word/Bits_Integer.thy b/thys/Native_Word/Bits_Integer.thy
--- a/thys/Native_Word/Bits_Integer.thy
+++ b/thys/Native_Word/Bits_Integer.thy
@@ -1,651 +1,651 @@
 (*  Title:      Bits_Integer.thy
     Author:     Andreas Lochbihler, ETH Zurich
 *)
 
 chapter \<open>Bit operations for target language integers\<close>
 
 theory Bits_Integer imports
   More_Bits_Int
   Code_Symbolic_Bits_Int
 begin
 
 lemmas [transfer_rule] =
   identity_quotient
   fun_quotient
   Quotient_integer[folded integer.pcr_cr_eq]
 
 lemma undefined_transfer:
   assumes "Quotient R Abs Rep T"
   shows "T (Rep undefined) undefined"
 using assms unfolding Quotient_alt_def by blast
 
 bundle undefined_transfer = undefined_transfer[transfer_rule]
 
 section \<open>More lemmas about @{typ integer}s\<close>
 
 context
 includes integer.lifting
 begin
 
 lemma bitval_integer_transfer [transfer_rule]:
   "(rel_fun (=) pcr_integer) of_bool of_bool"
 by(auto simp add: of_bool_def integer.pcr_cr_eq cr_integer_def)
 
 lemma integer_of_nat_less_0_conv [simp]: "\<not> integer_of_nat n < 0"
 by(transfer) simp
 
 lemma int_of_integer_pow: "int_of_integer (x ^ n) = int_of_integer x ^ n"
 by(induct n) simp_all
 
 lemma pow_integer_transfer [transfer_rule]:
   "(rel_fun pcr_integer (rel_fun (=) pcr_integer)) (^) (^)"
 by(auto 4 3 simp add: integer.pcr_cr_eq cr_integer_def int_of_integer_pow)
 
 lemma sub1_lt_0_iff [simp]: "Code_Numeral.sub n num.One < 0 \<longleftrightarrow> False"
 by(cases n)(simp_all add: Code_Numeral.sub_code)
 
 lemma nat_of_integer_numeral [simp]: "nat_of_integer (numeral n) = numeral n"
 by transfer simp
 
 lemma nat_of_integer_sub1_conv_pred_numeral [simp]:
   "nat_of_integer (Code_Numeral.sub n num.One) = pred_numeral n"
 by(cases n)(simp_all add: Code_Numeral.sub_code)
 
 lemma nat_of_integer_1 [simp]: "nat_of_integer 1 = 1"
 by transfer simp
 
 lemma dup_1 [simp]: "Code_Numeral.dup 1 = 2"
 by transfer simp
 
 
 section \<open>Bit operations on @{typ integer}\<close>
 
 text \<open>Bit operations on @{typ integer} are the same as on @{typ int}\<close>
 
 lift_definition bin_rest_integer :: "integer \<Rightarrow> integer" is bin_rest .
 lift_definition bin_last_integer :: "integer \<Rightarrow> bool" is bin_last .
 lift_definition Bit_integer :: "integer \<Rightarrow> bool \<Rightarrow> integer" is Bit .
 
 end
 
 instantiation integer :: bit_operations begin
 context includes integer.lifting begin
 
-lift_definition bitAND_integer :: "integer \<Rightarrow> integer \<Rightarrow> integer" is "bitAND" .
-lift_definition bitOR_integer :: "integer \<Rightarrow> integer \<Rightarrow> integer" is "bitOR" .
-lift_definition bitXOR_integer :: "integer \<Rightarrow> integer \<Rightarrow> integer" is "bitXOR" .
-lift_definition bitNOT_integer :: "integer \<Rightarrow> integer" is "bitNOT" .
+lift_definition bitAND_integer :: "integer \<Rightarrow> integer \<Rightarrow> integer" is "(AND)" .
+lift_definition bitOR_integer :: "integer \<Rightarrow> integer \<Rightarrow> integer" is "(OR)" .
+lift_definition bitXOR_integer :: "integer \<Rightarrow> integer \<Rightarrow> integer" is "(XOR)" .
+lift_definition bitNOT_integer :: "integer \<Rightarrow> integer" is "NOT" .
 
 lift_definition test_bit_integer :: "integer \<Rightarrow> nat \<Rightarrow> bool" is test_bit .
 lift_definition lsb_integer :: "integer \<Rightarrow> bool" is lsb .
 lift_definition set_bit_integer :: "integer \<Rightarrow> nat \<Rightarrow> bool \<Rightarrow> integer" is set_bit .
 lift_definition shiftl_integer :: "integer \<Rightarrow> nat \<Rightarrow> integer" is shiftl .
 lift_definition shiftr_integer :: "integer \<Rightarrow> nat \<Rightarrow> integer" is shiftr .
 
 lift_definition msb_integer :: "integer \<Rightarrow> bool" is msb .
 instance ..
 end
 end
 
 abbreviation (input) wf_set_bits_integer
 where "wf_set_bits_integer \<equiv> wf_set_bits_int"
 
 
 section \<open>Target language implementations\<close>
 
 text \<open>
   Unfortunately, this is not straightforward,
   because these API functions have different signatures and preconditions on the parameters:
 
   \begin{description}
   \item[Standard ML] Shifts in IntInf are given as word, but not IntInf.
   \item[Haskell] In the Data.Bits.Bits type class, shifts and bit indices are given as Int rather than Integer.
   \end{description}
 
   Additional constants take only parameters of type @{typ integer} rather than @{typ nat}
   and check the preconditions as far as possible (e.g., being non-negative) in a portable way.
   Manual implementations inside code\_printing perform the remaining range checks and convert 
   these @{typ integer}s into the right type.
 
   For normalisation by evaluation, we derive custom code equations, because NBE
   does not know these code\_printing serialisations and would otherwise loop.
 \<close>
 
 code_identifier code_module Bits_Integer \<rightharpoonup>
   (SML) Bits_Int and (OCaml) Bits_Int and (Haskell) Bits_Int and (Scala) Bits_Int
 
 code_printing code_module Bits_Integer \<rightharpoonup> (SML)
 \<open>structure Bits_Integer : sig
   val set_bit : IntInf.int -> IntInf.int -> bool -> IntInf.int
   val shiftl : IntInf.int -> IntInf.int -> IntInf.int
   val shiftr : IntInf.int -> IntInf.int -> IntInf.int
   val test_bit : IntInf.int -> IntInf.int -> bool
 end = struct
 
 val maxWord = IntInf.pow (2, Word.wordSize);
 
 fun set_bit x n b =
   if n < maxWord then
     if b then IntInf.orb (x, IntInf.<< (1, Word.fromLargeInt (IntInf.toLarge n)))
     else IntInf.andb (x, IntInf.notb (IntInf.<< (1, Word.fromLargeInt (IntInf.toLarge n))))
   else raise (Fail ("Bit index too large: " ^ IntInf.toString n));
 
 fun shiftl x n =
   if n < maxWord then IntInf.<< (x, Word.fromLargeInt (IntInf.toLarge n))
   else raise (Fail ("Shift operand too large: " ^ IntInf.toString n));
 
 fun shiftr x n =
   if n < maxWord then IntInf.~>> (x, Word.fromLargeInt (IntInf.toLarge n))
   else raise (Fail ("Shift operand too large: " ^ IntInf.toString n));
 
 fun test_bit x n =
   if n < maxWord then IntInf.andb (x, IntInf.<< (1, Word.fromLargeInt (IntInf.toLarge n))) <> 0
   else raise (Fail ("Bit index too large: " ^ IntInf.toString n));
 
 end; (*struct Bits_Integer*)\<close>
 code_reserved SML Bits_Integer
 
 code_printing code_module Bits_Integer \<rightharpoonup> (OCaml)
 \<open>module Bits_Integer : sig
   val shiftl : Z.t -> Z.t -> Z.t
   val shiftr : Z.t -> Z.t -> Z.t
   val test_bit : Z.t -> Z.t -> bool
 end = struct
 
 (* We do not need an explicit range checks here,
    because Big_int.int_of_big_int raises Failure 
    if the argument does not fit into an int. *)
 let shiftl x n = Z.shift_left x (Z.to_int n);;
 
 let shiftr x n = Z.shift_right x (Z.to_int n);;
 
 let test_bit x n =  Z.testbit x (Z.to_int n);;
 
 end;; (*struct Bits_Integer*)\<close>
 code_reserved OCaml Bits_Integer
 
 code_printing code_module Data_Bits \<rightharpoonup> (Haskell)
 \<open>
 module Data_Bits where {
 
 import qualified Data.Bits;
 
 {-
   The ...Bounded functions assume that the Integer argument for the shift 
   or bit index fits into an Int, is non-negative and (for types of fixed bit width)
   less than bitSize
 -}
 
 infixl 7 .&.;
 infixl 6 `xor`;
 infixl 5 .|.;
 
 (.&.) :: Data.Bits.Bits a => a -> a -> a;
 (.&.) = (Data.Bits..&.);
 
 xor :: Data.Bits.Bits a => a -> a -> a;
 xor = Data.Bits.xor;
 
 (.|.) :: Data.Bits.Bits a => a -> a -> a;
 (.|.) = (Data.Bits..|.);
 
 complement :: Data.Bits.Bits a => a -> a;
 complement = Data.Bits.complement;
 
 testBitUnbounded :: Data.Bits.Bits a => a -> Integer -> Bool;
 testBitUnbounded x b
   | b <= toInteger (Prelude.maxBound :: Int) = Data.Bits.testBit x (fromInteger b)
   | otherwise = error ("Bit index too large: " ++ show b)
 ;
 
 testBitBounded :: Data.Bits.Bits a => a -> Integer -> Bool;
 testBitBounded x b = Data.Bits.testBit x (fromInteger b);
 
 setBitUnbounded :: Data.Bits.Bits a => a -> Integer -> Bool -> a;
 setBitUnbounded x n b
   | n <= toInteger (Prelude.maxBound :: Int) = 
     if b then Data.Bits.setBit x (fromInteger n) else Data.Bits.clearBit x (fromInteger n)
   | otherwise = error ("Bit index too large: " ++ show n)
 ;
 
 setBitBounded :: Data.Bits.Bits a => a -> Integer -> Bool -> a;
 setBitBounded x n True = Data.Bits.setBit x (fromInteger n);
 setBitBounded x n False = Data.Bits.clearBit x (fromInteger n);
 
 shiftlUnbounded :: Data.Bits.Bits a => a -> Integer -> a;
 shiftlUnbounded x n 
   | n <= toInteger (Prelude.maxBound :: Int) = Data.Bits.shiftL x (fromInteger n)
   | otherwise = error ("Shift operand too large: " ++ show n)
 ;
 
 shiftlBounded :: Data.Bits.Bits a => a -> Integer -> a;
 shiftlBounded x n = Data.Bits.shiftL x (fromInteger n);
 
 shiftrUnbounded :: Data.Bits.Bits a => a -> Integer -> a;
 shiftrUnbounded x n 
   | n <= toInteger (Prelude.maxBound :: Int) = Data.Bits.shiftR x (fromInteger n)
   | otherwise = error ("Shift operand too large: " ++ show n)
 ;
 
 shiftrBounded :: (Ord a, Data.Bits.Bits a) => a -> Integer -> a;
 shiftrBounded x n = Data.Bits.shiftR x (fromInteger n);
 
 }\<close>
 
   and \<comment> \<open>@{theory HOL.Quickcheck_Narrowing} maps @{typ integer} to 
             Haskell's Prelude.Int type instead of Integer. For compatibility
             with the Haskell target, we nevertheless provide bounded and 
             unbounded functions.\<close>
   (Haskell_Quickcheck)
 \<open>
 module Data_Bits where {
 
 import qualified Data.Bits;
 
 {-
   The functions assume that the Int argument for the shift or bit index is 
   non-negative and (for types of fixed bit width) less than bitSize
 -}
 
 infixl 7 .&.;
 infixl 6 `xor`;
 infixl 5 .|.;
 
 (.&.) :: Data.Bits.Bits a => a -> a -> a;
 (.&.) = (Data.Bits..&.);
 
 xor :: Data.Bits.Bits a => a -> a -> a;
 xor = Data.Bits.xor;
 
 (.|.) :: Data.Bits.Bits a => a -> a -> a;
 (.|.) = (Data.Bits..|.);
 
 complement :: Data.Bits.Bits a => a -> a;
 complement = Data.Bits.complement;
 
 testBitUnbounded :: Data.Bits.Bits a => a -> Prelude.Int -> Bool;
 testBitUnbounded = Data.Bits.testBit;
 
 testBitBounded :: Data.Bits.Bits a => a -> Prelude.Int -> Bool;
 testBitBounded = Data.Bits.testBit;
 
 setBitUnbounded :: Data.Bits.Bits a => a -> Prelude.Int -> Bool -> a;
 setBitUnbounded x n True = Data.Bits.setBit x n;
 setBitUnbounded x n False = Data.Bits.clearBit x n;
 
 setBitBounded :: Data.Bits.Bits a => a -> Prelude.Int -> Bool -> a;
 setBitBounded x n True = Data.Bits.setBit x n;
 setBitBounded x n False = Data.Bits.clearBit x n;
 
 shiftlUnbounded :: Data.Bits.Bits a => a -> Prelude.Int -> a;
 shiftlUnbounded = Data.Bits.shiftL;
 
 shiftlBounded :: Data.Bits.Bits a => a -> Prelude.Int -> a;
 shiftlBounded = Data.Bits.shiftL;
 
 shiftrUnbounded :: Data.Bits.Bits a => a -> Prelude.Int -> a;
 shiftrUnbounded = Data.Bits.shiftR;
 
 shiftrBounded :: (Ord a, Data.Bits.Bits a) => a -> Prelude.Int -> a;
 shiftrBounded = Data.Bits.shiftR;
 
 }\<close>
 code_reserved Haskell Data_Bits
 
 code_printing code_module Bits_Integer \<rightharpoonup> (Scala)
 \<open>object Bits_Integer {
 
 def setBit(x: BigInt, n: BigInt, b: Boolean) : BigInt =
   if (n.isValidInt)
     if (b)
       x.setBit(n.toInt)
     else
       x.clearBit(n.toInt)
   else
     sys.error("Bit index too large: " + n.toString)
 
 def shiftl(x: BigInt, n: BigInt) : BigInt =
   if (n.isValidInt)
     x << n.toInt
   else
     sys.error("Shift index too large: " + n.toString)
 
 def shiftr(x: BigInt, n: BigInt) : BigInt =
   if (n.isValidInt)
     x << n.toInt
   else
     sys.error("Shift index too large: " + n.toString)
 
 def testBit(x: BigInt, n: BigInt) : Boolean =
   if (n.isValidInt)
     x.testBit(n.toInt) 
   else
     sys.error("Bit index too large: " + n.toString)
 
 } /* object Bits_Integer */\<close>
 
 code_printing
-  constant "bitAND :: integer \<Rightarrow> integer \<Rightarrow> integer" \<rightharpoonup>
+  constant "(AND) :: integer \<Rightarrow> integer \<Rightarrow> integer" \<rightharpoonup>
   (SML) "IntInf.andb ((_),/ (_))" and
   (OCaml) "Z.logand" and
   (Haskell) "((Data'_Bits..&.) :: Integer -> Integer -> Integer)" and
   (Haskell_Quickcheck) "((Data'_Bits..&.) :: Prelude.Int -> Prelude.Int -> Prelude.Int)" and
   (Scala) infixl 3 "&"
-| constant "bitOR :: integer \<Rightarrow> integer \<Rightarrow> integer" \<rightharpoonup>
+| constant "(OR) :: integer \<Rightarrow> integer \<Rightarrow> integer" \<rightharpoonup>
   (SML) "IntInf.orb ((_),/ (_))" and
   (OCaml) "Z.logor" and
   (Haskell) "((Data'_Bits..|.) :: Integer -> Integer -> Integer)" and
   (Haskell_Quickcheck) "((Data'_Bits..|.) :: Prelude.Int -> Prelude.Int -> Prelude.Int)" and
   (Scala) infixl 1 "|"
-| constant "bitXOR :: integer \<Rightarrow> integer \<Rightarrow> integer" \<rightharpoonup>
+| constant "(XOR) :: integer \<Rightarrow> integer \<Rightarrow> integer" \<rightharpoonup>
   (SML) "IntInf.xorb ((_),/ (_))" and
   (OCaml) "Z.logxor" and
   (Haskell) "(Data'_Bits.xor :: Integer -> Integer -> Integer)" and
   (Haskell_Quickcheck) "(Data'_Bits.xor :: Prelude.Int -> Prelude.Int -> Prelude.Int)" and
   (Scala) infixl 2 "^"
-| constant "bitNOT :: integer \<Rightarrow> integer" \<rightharpoonup>
+| constant "NOT :: integer \<Rightarrow> integer" \<rightharpoonup>
   (SML) "IntInf.notb" and
   (OCaml) "Z.lognot" and
   (Haskell) "(Data'_Bits.complement :: Integer -> Integer)" and
   (Haskell_Quickcheck) "(Data'_Bits.complement :: Prelude.Int -> Prelude.Int)" and
   (Scala) "_.unary'_~"
 
 code_printing constant bin_rest_integer \<rightharpoonup>
   (SML) "IntInf.div ((_), 2)" and
   (OCaml) "Z.shift'_right/ _/ 1" and
   (Haskell) "(Data'_Bits.shiftrUnbounded _ 1 :: Integer)" and
   (Haskell_Quickcheck) "(Data'_Bits.shiftrUnbounded _ 1 :: Prelude.Int)" and
   (Scala) "_ >> 1"
 
 context
 includes integer.lifting
 begin
 
 lemma bitNOT_integer_code [code]:
   fixes i :: integer shows
   "NOT i = - i - 1"
 by transfer(simp add: int_not_def)
 
 lemma bin_rest_integer_code [code nbe]:
   "bin_rest_integer i = i div 2"
 by transfer(simp add: bin_rest_def)
 
 lemma bin_last_integer_code [code]:
   "bin_last_integer i \<longleftrightarrow> i AND 1 \<noteq> 0"
 by transfer(rule bin_last_conv_AND)
 
 lemma bin_last_integer_nbe [code nbe]:
   "bin_last_integer i \<longleftrightarrow> i mod 2 \<noteq> 0"
 by transfer(simp add: bin_last_def)
 
 lemma bitval_bin_last_integer [code_unfold]:
   "of_bool (bin_last_integer i) = i AND 1"
 by transfer(rule bitval_bin_last)
 
 end
 
 definition integer_test_bit :: "integer \<Rightarrow> integer \<Rightarrow> bool"
   where "integer_test_bit x n = (if n < 0 then undefined x n else x !! nat_of_integer n)"
 
 lemma test_bit_integer_code [code]:
   "x !! n \<longleftrightarrow> integer_test_bit x (integer_of_nat n)"
 by(simp add: integer_test_bit_def)
 
 lemma integer_test_bit_code [code]:
   "integer_test_bit x (Code_Numeral.Neg n) = undefined x (Code_Numeral.Neg n)"
   "integer_test_bit 0 0 = False"
   "integer_test_bit 0 (Code_Numeral.Pos n) = False"
   "integer_test_bit (Code_Numeral.Pos num.One)      0 = True"
   "integer_test_bit (Code_Numeral.Pos (num.Bit0 n)) 0 = False"
   "integer_test_bit (Code_Numeral.Pos (num.Bit1 n)) 0 = True"
   "integer_test_bit (Code_Numeral.Pos num.One)      (Code_Numeral.Pos n') = False"
   "integer_test_bit (Code_Numeral.Pos (num.Bit0 n)) (Code_Numeral.Pos n') =
    integer_test_bit (Code_Numeral.Pos n) (Code_Numeral.sub n' num.One)"
   "integer_test_bit (Code_Numeral.Pos (num.Bit1 n)) (Code_Numeral.Pos n') =
    integer_test_bit (Code_Numeral.Pos n) (Code_Numeral.sub n' num.One)"
   "integer_test_bit (Code_Numeral.Neg num.One)      0 = True"
   "integer_test_bit (Code_Numeral.Neg (num.Bit0 n)) 0 = False"
   "integer_test_bit (Code_Numeral.Neg (num.Bit1 n)) 0 = True"
   "integer_test_bit (Code_Numeral.Neg num.One)      (Code_Numeral.Pos n') = True"
   "integer_test_bit (Code_Numeral.Neg (num.Bit0 n)) (Code_Numeral.Pos n') =
    integer_test_bit (Code_Numeral.Neg n) (Code_Numeral.sub n' num.One)"
   "integer_test_bit (Code_Numeral.Neg (num.Bit1 n)) (Code_Numeral.Pos n') =
    integer_test_bit (Code_Numeral.Neg (n + num.One)) (Code_Numeral.sub n' num.One)"
 by(simp_all add: integer_test_bit_def test_bit_integer_def)
 
 code_printing constant integer_test_bit \<rightharpoonup>
   (SML) "Bits'_Integer.test'_bit" and
   (OCaml) "Bits'_Integer.test'_bit" and
   (Haskell) "(Data'_Bits.testBitUnbounded :: Integer -> Integer -> Bool)" and
   (Haskell_Quickcheck) "(Data'_Bits.testBitUnbounded :: Prelude.Int -> Prelude.Int -> Bool)" and
   (Scala) "Bits'_Integer.testBit"
 
 context
 includes integer.lifting
 begin
 
 lemma lsb_integer_code [code]:
   fixes x :: integer shows
   "lsb x = x !! 0"
 by transfer(simp add: lsb_int_def)
 
 definition integer_set_bit :: "integer \<Rightarrow> integer \<Rightarrow> bool \<Rightarrow> integer"
 where [code del]: "integer_set_bit x n b = (if n < 0 then undefined x n b else set_bit x (nat_of_integer n) b)"
 
 lemma set_bit_integer_code [code]:
   "set_bit x i b = integer_set_bit x (integer_of_nat i) b"
 by(simp add: integer_set_bit_def)
 
 lemma set_bit_integer_conv_masks: 
   fixes x :: integer shows
   "set_bit x i b = (if b then x OR (1 << i) else x AND NOT (1 << i))"
 by transfer(simp add: int_set_bit_conv_ops)
 
 end
 
 code_printing constant integer_set_bit \<rightharpoonup>
   (SML) "Bits'_Integer.set'_bit" and
   (Haskell) "(Data'_Bits.setBitUnbounded :: Integer -> Integer -> Bool -> Integer)" and
   (Haskell_Quickcheck) "(Data'_Bits.setBitUnbounded :: Prelude.Int -> Prelude.Int -> Bool -> Prelude.Int)" and
   (Scala) "Bits'_Integer.setBit"
 
 text \<open>
   OCaml.Big\_int does not have a method for changing an individual bit, so we emulate that with masks.
   We prefer an Isabelle implementation, because this then takes care of the signs for AND and OR.
 \<close>
 lemma integer_set_bit_code [code]:
   "integer_set_bit x n b =
   (if n < 0 then undefined x n b else
    if b then x OR (1 << nat_of_integer n)
    else x AND NOT (1 << nat_of_integer n))"
 by(auto simp add: integer_set_bit_def set_bit_integer_conv_masks)
 
 definition integer_shiftl :: "integer \<Rightarrow> integer \<Rightarrow> integer"
 where [code del]: "integer_shiftl x n = (if n < 0 then undefined x n else x << nat_of_integer n)"
 
 lemma shiftl_integer_code [code]: 
   fixes x :: integer shows
   "x << n = integer_shiftl x (integer_of_nat n)"
 by(auto simp add: integer_shiftl_def)
 
 context
 includes integer.lifting
 begin
 
 lemma shiftl_integer_conv_mult_pow2:
   fixes x :: integer shows
   "x << n = x * 2 ^ n"
 by transfer(simp add: shiftl_int_def)
 
 lemma integer_shiftl_code [code]:
   "integer_shiftl x (Code_Numeral.Neg n) = undefined x (Code_Numeral.Neg n)"
   "integer_shiftl x 0 = x"
   "integer_shiftl x (Code_Numeral.Pos n) = integer_shiftl (Code_Numeral.dup x) (Code_Numeral.sub n num.One)"
   "integer_shiftl 0 (Code_Numeral.Pos n) = 0"
   by (simp_all add: integer_shiftl_def shiftl_integer_def shiftl_int_def numeral_eq_Suc)
     (transfer, simp)
 
 end
 
 code_printing constant integer_shiftl \<rightharpoonup>
   (SML) "Bits'_Integer.shiftl" and
   (OCaml) "Bits'_Integer.shiftl" and
   (Haskell) "(Data'_Bits.shiftlUnbounded :: Integer -> Integer -> Integer)" and
   (Haskell_Quickcheck) "(Data'_Bits.shiftlUnbounded :: Prelude.Int -> Prelude.Int -> Prelude.Int)" and
   (Scala) "Bits'_Integer.shiftl"
 
 definition integer_shiftr :: "integer \<Rightarrow> integer \<Rightarrow> integer"
 where [code del]: "integer_shiftr x n = (if n < 0 then undefined x n else x >> nat_of_integer n)"
 
 lemma shiftr_integer_conv_div_pow2: 
   includes integer.lifting fixes x :: integer shows
   "x >> n = x div 2 ^ n"
 by transfer(simp add: shiftr_int_def)
 
 lemma shiftr_integer_code [code]:
   fixes x :: integer shows
   "x >> n = integer_shiftr x (integer_of_nat n)"
 by(auto simp add: integer_shiftr_def)
 
 code_printing constant integer_shiftr \<rightharpoonup>
   (SML) "Bits'_Integer.shiftr" and
   (OCaml) "Bits'_Integer.shiftr" and
   (Haskell) "(Data'_Bits.shiftrUnbounded :: Integer -> Integer -> Integer)" and
   (Haskell_Quickcheck) "(Data'_Bits.shiftrUnbounded :: Prelude.Int -> Prelude.Int -> Prelude.Int)" and
   (Scala) "Bits'_Integer.shiftr"
 
 lemma integer_shiftr_code [code]:
   "integer_shiftr x (Code_Numeral.Neg n) = undefined x (Code_Numeral.Neg n)"
   "integer_shiftr x 0 = x"
   "integer_shiftr 0 (Code_Numeral.Pos n) = 0"
   "integer_shiftr (Code_Numeral.Pos num.One) (Code_Numeral.Pos n) = 0"
   "integer_shiftr (Code_Numeral.Pos (num.Bit0 n')) (Code_Numeral.Pos n) = 
    integer_shiftr (Code_Numeral.Pos n') (Code_Numeral.sub n num.One)"
   "integer_shiftr (Code_Numeral.Pos (num.Bit1 n')) (Code_Numeral.Pos n) = 
    integer_shiftr (Code_Numeral.Pos n') (Code_Numeral.sub n num.One)"
   "integer_shiftr (Code_Numeral.Neg num.One) (Code_Numeral.Pos n) = -1"
   "integer_shiftr (Code_Numeral.Neg (num.Bit0 n')) (Code_Numeral.Pos n) = 
    integer_shiftr (Code_Numeral.Neg n') (Code_Numeral.sub n num.One)"
   "integer_shiftr (Code_Numeral.Neg (num.Bit1 n')) (Code_Numeral.Pos n) = 
    integer_shiftr (Code_Numeral.Neg (Num.inc n')) (Code_Numeral.sub n num.One)"
 by(simp_all add: integer_shiftr_def shiftr_integer_def)
 
 context
 includes integer.lifting
 begin
 
 lemma Bit_integer_code [code]:
   "Bit_integer i False = i << 1"
   "Bit_integer i True = (i << 1) + 1"
 by(transfer, simp add: Bit_def shiftl_int_def)+
 
 lemma msb_integer_code [code]:
   "msb (x :: integer) \<longleftrightarrow> x < 0"
 by transfer(simp add: msb_int_def)
 
 end
 
 context
 includes integer.lifting natural.lifting
 begin
 
 lemma bitAND_integer_unfold [code]:
   "x AND y =
    (if x = 0 then 0
     else if x = - 1 then y
     else Bit_integer (bin_rest_integer x AND bin_rest_integer y) (bin_last_integer x \<and> bin_last_integer y))"
   by transfer (fact bitAND_int.simps)
 
 lemma bitOR_integer_unfold [code]:
   "x OR y =
    (if x = 0 then y
     else if x = - 1 then - 1
     else Bit_integer (bin_rest_integer x OR bin_rest_integer y) (bin_last_integer x \<or> bin_last_integer y))"
 proof transfer
   fix x y :: int
   from int_or_Bits [of "bin_rest x" "bin_last x" "bin_rest y" "bin_last y"]
   have "(bin_rest x OR bin_rest y) BIT (bin_last x \<or> bin_last y) = x OR y"
     by simp
   then show "x OR y =
     (if x = 0 then y
      else if x = - 1 then - 1
      else Bit (bin_rest x OR bin_rest y) (bin_last x \<or> bin_last y))"
     by simp
 qed
 
 lemma bitXOR_integer_unfold [code]:
   "x XOR y =
    (if x = 0 then y
     else if x = - 1 then NOT y
     else Bit_integer (bin_rest_integer x XOR bin_rest_integer y)
       (\<not> bin_last_integer x \<longleftrightarrow> bin_last_integer y))"
 proof transfer
   fix x y :: int
   from int_xor_Bits [of "bin_rest x" "bin_last x" "bin_rest y" "bin_last y"]
   have "(bin_rest x XOR bin_rest y) BIT
     ((bin_last x \<or> bin_last y) \<and> (bin_last x \<longrightarrow> \<not> bin_last y)) = x XOR y"
     by simp
   also have "(bin_last x \<or> bin_last y) \<and> (bin_last x \<longrightarrow> \<not> bin_last y) \<longleftrightarrow> (\<not> bin_last x \<longleftrightarrow> bin_last y)"
     by auto
   finally show "x XOR y =
    (if x = 0 then y
     else if x = - 1 then NOT y
     else Bit (bin_rest x XOR bin_rest y)
       (\<not> bin_last x \<longleftrightarrow> bin_last y))"
     by simp
 qed
 
 end
 
 
 section \<open>Test code generator setup\<close>
 
 definition bit_integer_test :: "bool" where
   "bit_integer_test =
   (([ -1 AND 3, 1 AND -3, 3 AND 5, -3 AND (- 5)
     , -3 OR 1, 1 OR -3, 3 OR 5, -3 OR (- 5)
     , NOT 1, NOT (- 3)
     , -1 XOR 3, 1 XOR (- 3), 3 XOR 5, -5 XOR (- 3)
     , set_bit 5 4 True, set_bit (- 5) 2 True, set_bit 5 0 False, set_bit (- 5) 1 False
     , 1 << 2, -1 << 3
     , 100 >> 3, -100 >> 3] :: integer list)
   = [ 3, 1, 1, -7
     , -3, -3, 7, -1
     , -2, 2
     , -4, -4, 6, 6
     , 21, -1, 4, -7
     , 4, -8
     , 12, -13] \<and>
     [ (5 :: integer) !! 4, (5 :: integer) !! 2, (-5 :: integer) !! 4, (-5 :: integer) !! 2
     , lsb (5 :: integer), lsb (4 :: integer), lsb (-1 :: integer), lsb (-2 :: integer), 
       msb (5 :: integer), msb (0 :: integer), msb (-1 :: integer), msb (-2 :: integer)]
   = [ False, True, True, False,
       True, False, True, False,
       False, False, True, True])"
 
 export_code bit_integer_test checking SML Haskell? Haskell_Quickcheck? OCaml? Scala
 
 notepad begin
 have bit_integer_test by eval
 have bit_integer_test by normalization
 have bit_integer_test by code_simp
 end
 ML_val \<open>val true = @{code bit_integer_test}\<close>
 
 lemma "x AND y = x OR (y :: integer)"
 quickcheck[random, expect=counterexample]
 quickcheck[exhaustive, expect=counterexample]
 oops
 
 lemma "(x :: integer) AND x = x OR x"
 quickcheck[narrowing, expect=no_counterexample]
 oops
 
 lemma "(f :: integer \<Rightarrow> unit) = g"
 quickcheck[narrowing, size=3, expect=no_counterexample]
 by(simp add: fun_eq_iff)
 
 hide_const bit_integer_test
 hide_fact bit_integer_test_def
 
 end
diff --git a/thys/Native_Word/Code_Target_Bits_Int.thy b/thys/Native_Word/Code_Target_Bits_Int.thy
--- a/thys/Native_Word/Code_Target_Bits_Int.thy
+++ b/thys/Native_Word/Code_Target_Bits_Int.thy
@@ -1,75 +1,75 @@
 (*  Title:      Code_Target_Bits_Int.thy
     Author:     Andreas Lochbihler, ETH Zurich
 *)
 
 chapter \<open>Implementation of bit operations on int by target language operations\<close>
 
 theory Code_Target_Bits_Int
 imports
   Bits_Integer
   "HOL-Library.Code_Target_Int"
 begin
 
 declare [[code drop:
-  "bitAND :: int \<Rightarrow> _" "bitOR :: int \<Rightarrow> _" "bitXOR :: int \<Rightarrow> _" "bitNOT :: int \<Rightarrow> _"
+  "(AND) :: int \<Rightarrow> _" "(OR) :: int \<Rightarrow> _" "(XOR) :: int \<Rightarrow> _" "NOT :: int \<Rightarrow> _"
   "lsb :: int \<Rightarrow> _" "set_bit :: int \<Rightarrow> _" "test_bit :: int \<Rightarrow> _"
   "shiftl :: int \<Rightarrow> _" "shiftr :: int \<Rightarrow> _"
   bin_last bin_rest bin_nth Bit
   int_of_integer_symbolic
   ]]
 
 context
 includes integer.lifting
 begin
 
 lemma bitAND_int_code [code]:
   "int_of_integer i AND int_of_integer j = int_of_integer (i AND j)"
 by transfer simp
 
 lemma bitOR_int_code [code]:
   "int_of_integer i OR int_of_integer j = int_of_integer (i OR j)"
 by transfer simp
 
 lemma bitXOR_int_code [code]:
   "int_of_integer i XOR int_of_integer j = int_of_integer (i XOR j)"
 by transfer simp
 
 lemma bitNOT_int_code [code]:
   "NOT (int_of_integer i) = int_of_integer (NOT i)"
 by transfer simp
 
 declare bin_last_conv_AND [code]
 
 lemma bin_rest_code [code]:
    "bin_rest (int_of_integer i) = int_of_integer (bin_rest_integer i)"
 by transfer simp
 
 declare bitval_bin_last [code_unfold]
 
 declare bin_nth_conv_AND [code]
 
 lemma Bit_code [code]: "int_of_integer i BIT b = int_of_integer (Bit_integer i b)"
 by transfer simp
 
 lemma test_bit_int_code [code]: "int_of_integer x !! n = x !! n"
 by transfer simp
 
 lemma lsb_int_code [code]: "lsb (int_of_integer x) = lsb x"
 by transfer simp
 
 lemma set_bit_int_code [code]: "set_bit (int_of_integer x) n b = int_of_integer (set_bit x n b)"
 by transfer simp
 
 lemma shiftl_int_code [code]: "int_of_integer x << n = int_of_integer (x << n)"
 by transfer simp
 
 lemma shiftr_int_code [code]: "int_of_integer x >> n = int_of_integer (x >> n)"
 by transfer simp
 
 lemma int_of_integer_symbolic_code [code]:
   "int_of_integer_symbolic = int_of_integer"
 by(simp add: int_of_integer_symbolic_def)
 
 end
 
 end
diff --git a/thys/Native_Word/Uint.thy b/thys/Native_Word/Uint.thy
--- a/thys/Native_Word/Uint.thy
+++ b/thys/Native_Word/Uint.thy
@@ -1,794 +1,794 @@
 (*  Title:      Uint.thy
     Author:     Peter Lammich, TU Munich
     Author:     Andreas Lochbihler, ETH Zurich
 *)
 
 chapter \<open>Unsigned words of default size\<close>
 
 theory Uint imports
   Code_Target_Word_Base
 begin
 
 text \<open>
   This theory provides access to words in the target languages of the code generator
   whose bit width is the default of the target language. To that end, the type \<open>uint\<close>
   models words of width \<open>dflt_size\<close>, but \<open>dflt_size\<close> is known only to be positive.
 
   Usage restrictions:
   Default-size words (type \<open>uint\<close>) cannot be used for evaluation, because 
   the results depend on the particular choice of word size in the target language
   and implementation. Symbolic evaluation has not yet been set up for \<open>uint\<close>.
 \<close>
 
 text \<open>The default size type\<close>
 typedecl dflt_size
 
 instantiation dflt_size :: typerep begin
 definition "typerep_class.typerep \<equiv>  \<lambda>_ :: dflt_size itself. Typerep.Typerep (STR ''Uint.dflt_size'') []"
 instance ..
 end
 
 consts dflt_size_aux :: "nat"
 specification (dflt_size_aux) dflt_size_aux_g0: "dflt_size_aux > 0"
   by auto
 hide_fact dflt_size_aux_def
 
 instantiation dflt_size :: len begin
 definition "len_of_dflt_size (_ :: dflt_size itself) \<equiv> dflt_size_aux"
 instance by(intro_classes)(simp add: len_of_dflt_size_def dflt_size_aux_g0)
 end
 
 abbreviation "dflt_size \<equiv> len_of (TYPE (dflt_size))"
 
 context includes integer.lifting begin
 lift_definition dflt_size_integer :: integer is "int dflt_size" .
 declare dflt_size_integer_def[code del]
   \<comment> \<open>The code generator will substitute a machine-dependent value for this constant\<close>
 
 lemma dflt_size_by_int[code]: "dflt_size = nat_of_integer dflt_size_integer"
 by transfer simp
 
 lemma dflt_size[simp]: 
   "dflt_size > 0"
   "dflt_size \<ge> Suc 0"
   "\<not> dflt_size < Suc 0"
   using len_gt_0[where 'a=dflt_size]
   by (simp_all del: len_gt_0)
 end
 
 declare prod.Quotient[transfer_rule]
 
 section \<open>Type definition and primitive operations\<close>
 
 typedef uint = "UNIV :: dflt_size word set" .. 
 
 setup_lifting type_definition_uint
 
 text \<open>Use an abstract type for code generation to disable pattern matching on @{term Abs_uint}.\<close>
 declare Rep_uint_inverse[code abstype]
 
 declare Quotient_uint[transfer_rule]
 
 instantiation uint :: "{neg_numeral, modulo, comm_monoid_mult, comm_ring}" begin
 lift_definition zero_uint :: uint is "0 :: dflt_size word" .
 lift_definition one_uint :: uint is "1" .
 lift_definition plus_uint :: "uint \<Rightarrow> uint \<Rightarrow> uint" is "(+) :: dflt_size word \<Rightarrow> _" .
 lift_definition minus_uint :: "uint \<Rightarrow> uint \<Rightarrow> uint" is "(-)" .
 lift_definition uminus_uint :: "uint \<Rightarrow> uint" is uminus .
 lift_definition times_uint :: "uint \<Rightarrow> uint \<Rightarrow> uint" is "(*)" .
 lift_definition divide_uint :: "uint \<Rightarrow> uint \<Rightarrow> uint" is "(div)" .
 lift_definition modulo_uint :: "uint \<Rightarrow> uint \<Rightarrow> uint" is "(mod)" .
 instance by standard (transfer, simp add: algebra_simps)+
 end
 
 instantiation uint :: linorder begin
 lift_definition less_uint :: "uint \<Rightarrow> uint \<Rightarrow> bool" is "(<)" .
 lift_definition less_eq_uint :: "uint \<Rightarrow> uint \<Rightarrow> bool" is "(\<le>)" .
 instance by standard (transfer, simp add: less_le_not_le linear)+
 end
 
 lemmas [code] = less_uint.rep_eq less_eq_uint.rep_eq
 
 instantiation uint :: bit_operations begin
-lift_definition bitNOT_uint :: "uint \<Rightarrow> uint" is bitNOT .
-lift_definition bitAND_uint :: "uint \<Rightarrow> uint \<Rightarrow> uint" is bitAND .
-lift_definition bitOR_uint :: "uint \<Rightarrow> uint \<Rightarrow> uint" is bitOR .
-lift_definition bitXOR_uint :: "uint \<Rightarrow> uint \<Rightarrow> uint" is bitXOR .
+lift_definition bitNOT_uint :: "uint \<Rightarrow> uint" is NOT .
+lift_definition bitAND_uint :: "uint \<Rightarrow> uint \<Rightarrow> uint" is \<open>(AND)\<close> .
+lift_definition bitOR_uint :: "uint \<Rightarrow> uint \<Rightarrow> uint" is \<open>(OR)\<close> .
+lift_definition bitXOR_uint :: "uint \<Rightarrow> uint \<Rightarrow> uint" is \<open>(XOR)\<close> .
 lift_definition test_bit_uint :: "uint \<Rightarrow> nat \<Rightarrow> bool" is test_bit .
 lift_definition set_bit_uint :: "uint \<Rightarrow> nat \<Rightarrow> bool \<Rightarrow> uint" is set_bit .
 lift_definition lsb_uint :: "uint \<Rightarrow> bool" is lsb .
 lift_definition shiftl_uint :: "uint \<Rightarrow> nat \<Rightarrow> uint" is shiftl .
 lift_definition shiftr_uint :: "uint \<Rightarrow> nat \<Rightarrow> uint" is shiftr .
 lift_definition msb_uint :: "uint \<Rightarrow> bool" is msb .
 instance ..
 end
 
 instantiation uint :: bit_comprehension begin
 lift_definition set_bits_uint :: "(nat \<Rightarrow> bool) \<Rightarrow> uint" is "set_bits" .
 instance ..
 end
 
 lemmas [code] = test_bit_uint.rep_eq lsb_uint.rep_eq msb_uint.rep_eq
 
 instantiation uint :: equal begin
 lift_definition equal_uint :: "uint \<Rightarrow> uint \<Rightarrow> bool" is "equal_class.equal" .
 instance by standard (transfer, simp add: equal_eq)
 end
 
 lemmas [code] = equal_uint.rep_eq
 
 instantiation uint :: size begin
 lift_definition size_uint :: "uint \<Rightarrow> nat" is "size" .
 instance ..
 end
 
 lemmas [code] = size_uint.rep_eq
 
 lift_definition sshiftr_uint :: "uint \<Rightarrow> nat \<Rightarrow> uint" (infixl ">>>" 55) is sshiftr .
 
 lift_definition uint_of_int :: "int \<Rightarrow> uint" is "word_of_int" .
 
 lemma of_bool_integer_transfer [transfer_rule]:
   "(rel_fun (=) pcr_integer) of_bool of_bool"
 by(auto simp add: integer.pcr_cr_eq cr_integer_def split: bit.split)
 
 text \<open>Use pretty numerals from integer for pretty printing\<close>
 
 context includes integer.lifting begin
 
 lift_definition Uint :: "integer \<Rightarrow> uint" is "word_of_int" .
 
 lemma Rep_uint_numeral [simp]: "Rep_uint (numeral n) = numeral n"
 by(induction n)(simp_all add: one_uint_def Abs_uint_inverse numeral.simps plus_uint_def)
 
 lemma numeral_uint_transfer [transfer_rule]:
   "(rel_fun (=) cr_uint) numeral numeral"
 by(auto simp add: cr_uint_def)
 
 lemma numeral_uint [code_unfold]: "numeral n = Uint (numeral n)"
 by transfer simp
 
 lemma Rep_uint_neg_numeral [simp]: "Rep_uint (- numeral n) = - numeral n"
 by(simp only: uminus_uint_def)(simp add: Abs_uint_inverse)
 
 lemma neg_numeral_uint [code_unfold]: "- numeral n = Uint (- numeral n)"
 by transfer(simp add: cr_uint_def)
 
 end
 
 lemma Abs_uint_numeral [code_post]: "Abs_uint (numeral n) = numeral n"
 by(induction n)(simp_all add: one_uint_def numeral.simps plus_uint_def Abs_uint_inverse)
 
 lemma Abs_uint_0 [code_post]: "Abs_uint 0 = 0"
 by(simp add: zero_uint_def)
 
 lemma Abs_uint_1 [code_post]: "Abs_uint 1 = 1"
 by(simp add: one_uint_def)
 
 section \<open>Code setup\<close>
 
 code_printing code_module Uint \<rightharpoonup> (SML)
 \<open>
 structure Uint : sig
   val set_bit : Word.word -> IntInf.int -> bool -> Word.word
   val shiftl : Word.word -> IntInf.int -> Word.word
   val shiftr : Word.word -> IntInf.int -> Word.word
   val shiftr_signed : Word.word -> IntInf.int -> Word.word
   val test_bit : Word.word -> IntInf.int -> bool
 end = struct
 
 fun set_bit x n b =
   let val mask = Word.<< (0wx1, Word.fromLargeInt (IntInf.toLarge n))
   in if b then Word.orb (x, mask)
      else Word.andb (x, Word.notb mask)
   end
 
 fun shiftl x n =
   Word.<< (x, Word.fromLargeInt (IntInf.toLarge n))
 
 fun shiftr x n =
   Word.>> (x, Word.fromLargeInt (IntInf.toLarge n))
 
 fun shiftr_signed x n =
   Word.~>> (x, Word.fromLargeInt (IntInf.toLarge n))
 
 fun test_bit x n =
   Word.andb (x, Word.<< (0wx1, Word.fromLargeInt (IntInf.toLarge n))) <> Word.fromInt 0
 
 end; (* struct Uint *)\<close>
 code_reserved SML Uint
 
 code_printing code_module Uint \<rightharpoonup> (Haskell)
  \<open>module Uint(Int, Word, dflt_size) where
 
   import qualified Prelude
   import Data.Int(Int)
   import Data.Word(Word)
   import qualified Data.Bits
 
   dflt_size :: Prelude.Integer
   dflt_size = Prelude.toInteger (bitSize_aux (0::Word)) where
     bitSize_aux :: (Data.Bits.Bits a, Prelude.Bounded a) => a -> Int
     bitSize_aux = Data.Bits.bitSize\<close>
   and (Haskell_Quickcheck)
  \<open>module Uint(Int, Word, dflt_size) where
 
   import qualified Prelude
   import Data.Int(Int)
   import Data.Word(Word)
   import qualified Data.Bits
 
   dflt_size :: Prelude.Int
   dflt_size = bitSize_aux (0::Word) where
     bitSize_aux :: (Data.Bits.Bits a, Prelude.Bounded a) => a -> Int
     bitSize_aux = Data.Bits.bitSize
 \<close>
 code_reserved Haskell Uint dflt_size
 
 text \<open>
   OCaml and Scala provide only signed bit numbers, so we use these and 
   implement sign-sensitive operations like comparisons manually.
 \<close>
 
 code_printing code_module "Uint" \<rightharpoonup> (OCaml)
 \<open>module Uint : sig
   type t = int
   val dflt_size : Z.t
   val less : t -> t -> bool
   val less_eq : t -> t -> bool
   val set_bit : t -> Z.t -> bool -> t
   val shiftl : t -> Z.t -> t
   val shiftr : t -> Z.t -> t
   val shiftr_signed : t -> Z.t -> t
   val test_bit : t -> Z.t -> bool
   val int_mask : int
   val int32_mask : int32
   val int64_mask : int64
 end = struct
 
 type t = int
 
 let dflt_size = Z.of_int Sys.int_size;;
 
 (* negative numbers have their highest bit set, 
    so they are greater than positive ones *)
 let less x y =
   if x<0 then
     y<0 && x<y
   else y < 0 || x < y;;
 
 let less_eq x y =
   if x < 0 then
     y < 0 &&  x <= y
   else y < 0 || x <= y;;
 
 let set_bit x n b =
   let mask = 1 lsl (Z.to_int n)
   in if b then x lor mask
      else x land (lnot mask);;
 
 let shiftl x n = x lsl (Z.to_int n);;
 
 let shiftr x n = x lsr (Z.to_int n);;
 
 let shiftr_signed x n = x asr (Z.to_int n);;
 
 let test_bit x n = x land (1 lsl (Z.to_int n)) <> 0;;
 
 let int_mask =
   if Sys.int_size < 32 then lnot 0 else 0xFFFFFFFF;;
 
 let int32_mask = 
   if Sys.int_size < 32 then Int32.pred (Int32.shift_left Int32.one Sys.int_size)
   else Int32.of_string "0xFFFFFFFF";;
 
 let int64_mask = 
   if Sys.int_size < 64 then Int64.pred (Int64.shift_left Int64.one Sys.int_size)
   else Int64.of_string "0xFFFFFFFFFFFFFFFF";;
 
 end;; (*struct Uint*)\<close>
 code_reserved OCaml Uint
 
 code_printing code_module Uint \<rightharpoonup> (Scala)
 \<open>object Uint {
 def dflt_size : BigInt = BigInt(32)
 
 def less(x: Int, y: Int) : Boolean =
   if (x < 0) y < 0 && x < y
   else y < 0 || x < y
 
 def less_eq(x: Int, y: Int) : Boolean =
   if (x < 0) y < 0 && x <= y
   else y < 0 || x <= y
 
 def set_bit(x: Int, n: BigInt, b: Boolean) : Int =
   if (b)
     x | (1 << n.intValue)
   else
     x & (1 << n.intValue).unary_~
 
 def shiftl(x: Int, n: BigInt) : Int = x << n.intValue
 
 def shiftr(x: Int, n: BigInt) : Int = x >>> n.intValue
 
 def shiftr_signed(x: Int, n: BigInt) : Int = x >> n.intValue
 
 def test_bit(x: Int, n: BigInt) : Boolean =
   (x & (1 << n.intValue)) != 0
 
 } /* object Uint */\<close>
 code_reserved Scala Uint
 
 
 text \<open>
   OCaml's conversion from Big\_int to int demands that the value fits into a signed integer.
   The following justifies the implementation.
 \<close>
 
 context includes integer.lifting begin
 definition wivs_mask :: int where "wivs_mask = 2^ dflt_size - 1"
 lift_definition wivs_mask_integer :: integer is wivs_mask .
 lemma [code]: "wivs_mask_integer = 2 ^ dflt_size - 1"
   by transfer (simp add: wivs_mask_def)
 
 definition wivs_shift :: int where "wivs_shift = 2 ^ dflt_size"
 lift_definition wivs_shift_integer :: integer is wivs_shift .
 lemma [code]: "wivs_shift_integer = 2 ^ dflt_size"
   by transfer (simp add: wivs_shift_def)
 
 definition wivs_index :: nat where "wivs_index == dflt_size - 1"
 lift_definition wivs_index_integer :: integer is "int wivs_index".
 lemma wivs_index_integer_code[code]: "wivs_index_integer = dflt_size_integer - 1"
   by transfer (simp add: wivs_index_def of_nat_diff)
 
 definition wivs_overflow :: int where "wivs_overflow == 2^ (dflt_size - 1)"
 lift_definition wivs_overflow_integer :: integer is wivs_overflow .
 lemma [code]: "wivs_overflow_integer = 2 ^ (dflt_size - 1)"
   by transfer (simp add: wivs_overflow_def)
 
 definition wivs_least :: int where "wivs_least == - wivs_overflow"
 lift_definition wivs_least_integer :: integer is wivs_least .
 lemma [code]: "wivs_least_integer = - (2 ^ (dflt_size - 1))"
   by transfer (simp add: wivs_overflow_def wivs_least_def)
 
 definition Uint_signed :: "integer \<Rightarrow> uint" where
   "Uint_signed i = (if i < wivs_least_integer \<or> wivs_overflow_integer \<le> i then undefined Uint i else Uint i)"
 
 lemma Uint_code [code]:
   "Uint i = 
   (let i' = i AND wivs_mask_integer in 
    if i' !! wivs_index then Uint_signed (i' - wivs_shift_integer) else Uint_signed i')"
   including undefined_transfer 
   unfolding Uint_signed_def
   apply transfer
   apply (rule word_of_int_via_signed)
   by (simp_all add: wivs_mask_def wivs_shift_def wivs_index_def wivs_overflow_def 
     wivs_least_def bin_mask_conv_pow2 shiftl_int_def)
 
 lemma Uint_signed_code [code abstract]:
   "Rep_uint (Uint_signed i) = 
   (if i < wivs_least_integer \<or> i \<ge> wivs_overflow_integer then Rep_uint (undefined Uint i) else word_of_int (int_of_integer_symbolic i))"
   unfolding Uint_signed_def Uint_def int_of_integer_symbolic_def word_of_integer_def
   by(simp add: Abs_uint_inverse)
 end
 
 text \<open>
   Avoid @{term Abs_uint} in generated code, use @{term Rep_uint'} instead. 
   The symbolic implementations for code\_simp use @{term Rep_uint}.
 
   The new destructor @{term Rep_uint'} is executable.
   As the simplifier is given the [code abstract] equations literally, 
   we cannot implement @{term Rep_uint} directly, because that makes code\_simp loop.
 
   If code generation raises Match, some equation probably contains @{term Rep_uint} 
   ([code abstract] equations for @{typ uint} may use @{term Rep_uint} because
   these instances will be folded away.)
 \<close>
 
 definition Rep_uint' where [simp]: "Rep_uint' = Rep_uint"
 
 lemma Rep_uint'_code [code]: "Rep_uint' x = (BITS n. x !! n)"
 unfolding Rep_uint'_def by transfer simp
 
 lift_definition Abs_uint' :: "dflt_size word \<Rightarrow> uint" is "\<lambda>x :: dflt_size word. x" .
 
 lemma Abs_uint'_code [code]:
   "Abs_uint' x = Uint (integer_of_int (uint x))"
 including integer.lifting by transfer simp
 
 declare [[code drop: "term_of_class.term_of :: uint \<Rightarrow> _"]]
 
 lemma term_of_uint_code [code]:
   defines "TR \<equiv> typerep.Typerep" and "bit0 \<equiv> STR ''Numeral_Type.bit0''" 
   shows
   "term_of_class.term_of x = 
    Code_Evaluation.App (Code_Evaluation.Const (STR ''Uint.uint.Abs_uint'') (TR (STR ''fun'') [TR (STR ''Word.word'')  [TR (STR ''Uint.dflt_size'') []], TR (STR ''Uint.uint'') []]))
        (term_of_class.term_of (Rep_uint' x))"
   by(simp add: term_of_anything)
 
 text \<open>Important:
   We must prevent the reflection oracle (eval-tac) to 
   use our machine-dependent type.
 \<close>
 
 code_printing
   type_constructor uint \<rightharpoonup>
   (SML) "Word.word" and
   (Haskell) "Uint.Word" and
   (OCaml) "Uint.t" and
   (Scala) "Int" and
   (Eval) "*** \"Error: Machine dependent type\" ***" and
   (Quickcheck) "Word.word" 
 | constant dflt_size_integer \<rightharpoonup>
   (SML) "(IntInf.fromLarge (Int.toLarge Word.wordSize))" and
   (Eval) "(raise (Fail \"Machine dependent code\"))" and
   (Quickcheck) "Word.wordSize" and
   (Haskell) "Uint.dflt'_size" and
   (OCaml) "Uint.dflt'_size" and
   (Scala) "Uint.dflt'_size"
 | constant Uint \<rightharpoonup>
   (SML) "Word.fromLargeInt (IntInf.toLarge _)" and
   (Eval) "(raise (Fail \"Machine dependent code\"))" and
   (Quickcheck) "Word.fromInt" and
   (Haskell) "(Prelude.fromInteger _ :: Uint.Word)" and
   (Haskell_Quickcheck) "(Prelude.fromInteger (Prelude.toInteger _) :: Uint.Word)" and
   (Scala) "_.intValue"
 | constant Uint_signed \<rightharpoonup>
   (OCaml) "Z.to'_int"
 | constant "0 :: uint" \<rightharpoonup>
   (SML) "(Word.fromInt 0)" and
   (Eval) "(raise (Fail \"Machine dependent code\"))" and
   (Quickcheck) "(Word.fromInt 0)" and
   (Haskell) "(0 :: Uint.Word)" and
   (OCaml) "0" and
   (Scala) "0"
 | constant "1 :: uint" \<rightharpoonup>
   (SML) "(Word.fromInt 1)" and
   (Eval) "(raise (Fail \"Machine dependent code\"))" and
   (Quickcheck) "(Word.fromInt 1)" and
   (Haskell) "(1 :: Uint.Word)" and
   (OCaml) "1" and
   (Scala) "1"
 | constant "plus :: uint \<Rightarrow> _ " \<rightharpoonup>
   (SML) "Word.+ ((_), (_))" and
   (Eval) "(raise (Fail \"Machine dependent code\"))" and
   (Quickcheck) "Word.+ ((_), (_))" and
   (Haskell) infixl 6 "+" and
   (OCaml) "Pervasives.(+)" and
   (Scala) infixl 7 "+"
 | constant "uminus :: uint \<Rightarrow> _" \<rightharpoonup>
   (SML) "Word.~" and
   (Eval) "(raise (Fail \"Machine dependent code\"))" and
   (Quickcheck) "Word.~" and
   (Haskell) "negate" and
   (OCaml) "Pervasives.(~-)" and
   (Scala) "!(- _)"
 | constant "minus :: uint \<Rightarrow> _" \<rightharpoonup>
   (SML) "Word.- ((_), (_))" and
   (Eval) "(raise (Fail \"Machine dependent code\"))" and
   (Quickcheck) "Word.- ((_), (_))" and
   (Haskell) infixl 6 "-" and
   (OCaml) "Pervasives.(-)" and
   (Scala) infixl 7 "-"
 | constant "times :: uint \<Rightarrow> _ \<Rightarrow> _" \<rightharpoonup>
   (SML) "Word.* ((_), (_))" and
   (Eval) "(raise (Fail \"Machine dependent code\"))" and
   (Quickcheck) "Word.* ((_), (_))" and
   (Haskell) infixl 7 "*" and
   (OCaml) "Pervasives.( * )" and
   (Scala) infixl 8 "*"
 | constant "HOL.equal :: uint \<Rightarrow> _ \<Rightarrow> bool" \<rightharpoonup>
   (SML) "!((_ : Word.word) = _)" and
   (Eval) "(raise (Fail \"Machine dependent code\"))" and
   (Quickcheck) "!((_ : Word.word) = _)" and
   (Haskell) infix 4 "==" and
   (OCaml) "(Pervasives.(=):Uint.t -> Uint.t -> bool)" and
   (Scala) infixl 5 "=="
 | class_instance uint :: equal \<rightharpoonup>
   (Haskell) -
 | constant "less_eq :: uint \<Rightarrow> _ \<Rightarrow> bool" \<rightharpoonup>
   (SML) "Word.<= ((_), (_))" and
   (Eval) "(raise (Fail \"Machine dependent code\"))" and
   (Quickcheck) "Word.<= ((_), (_))" and
   (Haskell) infix 4 "<=" and
   (OCaml) "Uint.less'_eq" and
   (Scala) "Uint.less'_eq"
 | constant "less :: uint \<Rightarrow> _ \<Rightarrow> bool" \<rightharpoonup>
   (SML) "Word.< ((_), (_))" and
   (Eval) "(raise (Fail \"Machine dependent code\"))" and
   (Quickcheck) "Word.< ((_), (_))" and
   (Haskell) infix 4 "<" and
   (OCaml) "Uint.less" and
   (Scala) "Uint.less"
-| constant "bitNOT :: uint \<Rightarrow> _" \<rightharpoonup>
+| constant "NOT :: uint \<Rightarrow> _" \<rightharpoonup>
   (SML) "Word.notb" and
   (Eval) "(raise (Fail \"Machine dependent code\"))" and
   (Quickcheck) "Word.notb" and
   (Haskell) "Data'_Bits.complement" and
   (OCaml) "Pervasives.lnot" and
   (Scala) "_.unary'_~"
-| constant "bitAND :: uint \<Rightarrow> _" \<rightharpoonup>
+| constant "(AND) :: uint \<Rightarrow> _" \<rightharpoonup>
   (SML) "Word.andb ((_),/ (_))" and
   (Eval) "(raise (Fail \"Machine dependent code\"))" and
   (Quickcheck) "Word.andb ((_),/ (_))" and
   (Haskell) infixl 7 "Data_Bits..&." and
   (OCaml) "Pervasives.(land)" and
   (Scala) infixl 3 "&"
-| constant "bitOR :: uint \<Rightarrow> _" \<rightharpoonup>
+| constant "(OR) :: uint \<Rightarrow> _" \<rightharpoonup>
   (SML) "Word.orb ((_),/ (_))" and
   (Eval) "(raise (Fail \"Machine dependent code\"))" and
   (Quickcheck) "Word.orb ((_),/ (_))" and
   (Haskell) infixl 5 "Data_Bits..|." and
   (OCaml) "Pervasives.(lor)" and
   (Scala) infixl 1 "|"
-| constant "bitXOR :: uint \<Rightarrow> _" \<rightharpoonup>
+| constant "(XOR) :: uint \<Rightarrow> _" \<rightharpoonup>
   (SML) "Word.xorb ((_),/ (_))" and
   (Eval) "(raise (Fail \"Machine dependent code\"))" and
   (Quickcheck) "Word.xorb ((_),/ (_))" and
   (Haskell) "Data'_Bits.xor" and
   (OCaml) "Pervasives.(lxor)" and
   (Scala) infixl 2 "^"
 
 definition uint_divmod :: "uint \<Rightarrow> uint \<Rightarrow> uint \<times> uint" where
   "uint_divmod x y = 
   (if y = 0 then (undefined ((div) :: uint \<Rightarrow> _) x (0 :: uint), undefined ((mod) :: uint \<Rightarrow> _) x (0 :: uint)) 
   else (x div y, x mod y))"
 
 definition uint_div :: "uint \<Rightarrow> uint \<Rightarrow> uint" 
 where "uint_div x y = fst (uint_divmod x y)"
 
 definition uint_mod :: "uint \<Rightarrow> uint \<Rightarrow> uint" 
 where "uint_mod x y = snd (uint_divmod x y)"
 
 lemma div_uint_code [code]: "x div y = (if y = 0 then 0 else uint_div x y)"
 including undefined_transfer unfolding uint_divmod_def uint_div_def
 by transfer(simp add: word_div_def)
 
 lemma mod_uint_code [code]: "x mod y = (if y = 0 then x else uint_mod x y)"
 including undefined_transfer unfolding uint_mod_def uint_divmod_def
 by transfer(simp add: word_mod_def)
 
 definition uint_sdiv :: "uint \<Rightarrow> uint \<Rightarrow> uint"
 where [code del]:
   "uint_sdiv x y =
    (if y = 0 then undefined ((div) :: uint \<Rightarrow> _) x (0 :: uint)
     else Abs_uint (Rep_uint x sdiv Rep_uint y))"
 
 definition div0_uint :: "uint \<Rightarrow> uint"
 where [code del]: "div0_uint x = undefined ((div) :: uint \<Rightarrow> _) x (0 :: uint)"
 declare [[code abort: div0_uint]]
 
 definition mod0_uint :: "uint \<Rightarrow> uint"
 where [code del]: "mod0_uint x = undefined ((mod) :: uint \<Rightarrow> _) x (0 :: uint)"
 declare [[code abort: mod0_uint]]
 
 definition wivs_overflow_uint :: uint 
   where "wivs_overflow_uint \<equiv> 1 << (dflt_size - 1)"
 
 (* TODO: Move to Word *)
 lemma dflt_size_word_pow_ne_zero [simp]:
   "(2 :: 'a word) ^ (LENGTH('a::len) - Suc 0) \<noteq> 0"
 proof
   assume "(2 :: 'a word) ^ (LENGTH('a::len) - Suc 0) = 0"
   then have "unat ((2 :: 'a word) ^ (LENGTH('a::len) - Suc 0)) = unat 0"
     by simp
   then show False by (simp add: unat_p2)
 qed
 
 lemma uint_divmod_code [code]:
   "uint_divmod x y =
   (if wivs_overflow_uint \<le> y then if x < y then (0, x) else (1, x - y)
    else if y = 0 then (div0_uint x, mod0_uint x)
    else let q = (uint_sdiv (x >> 1) y) << 1;
             r = x - q * y
         in if r \<ge> y then (q + 1, r - y) else (q, r))"
   including undefined_transfer 
   unfolding uint_divmod_def uint_sdiv_def div0_uint_def mod0_uint_def
     wivs_overflow_uint_def
   by transfer (simp add: divmod_via_sdivmod)
 
 lemma uint_sdiv_code [code abstract]:
   "Rep_uint (uint_sdiv x y) =
    (if y = 0 then Rep_uint (undefined ((div) :: uint \<Rightarrow> _) x (0 :: uint))
     else Rep_uint x sdiv Rep_uint y)"
 unfolding uint_sdiv_def by(simp add: Abs_uint_inverse)
 
 text \<open>
   Note that we only need a translation for signed division, but not for the remainder
   because @{thm uint_divmod_code} computes both with division only.
 \<close>
 
 code_printing
   constant uint_div \<rightharpoonup>
   (SML) "Word.div ((_), (_))" and
   (Eval) "(raise (Fail \"Machine dependent code\"))" and
   (Quickcheck) "Word.div ((_), (_))" and
   (Haskell) "Prelude.div"
 | constant uint_mod \<rightharpoonup>
   (SML) "Word.mod ((_), (_))" and
   (Eval) "(raise (Fail \"Machine dependent code\"))" and
   (Quickcheck) "Word.mod ((_), (_))" and
   (Haskell) "Prelude.mod"
 | constant uint_divmod \<rightharpoonup>
   (Haskell) "divmod"
 | constant uint_sdiv \<rightharpoonup>
   (OCaml) "Pervasives.('/)" and
   (Scala) "_ '/ _"
 
 definition uint_test_bit :: "uint \<Rightarrow> integer \<Rightarrow> bool"
 where [code del]:
   "uint_test_bit x n =
   (if n < 0 \<or> dflt_size_integer \<le> n then undefined (test_bit :: uint \<Rightarrow> _) x n
    else x !! (nat_of_integer n))"
 
 lemma test_bit_uint_code [code]:
   "test_bit x n \<longleftrightarrow> n < dflt_size \<and> uint_test_bit x (integer_of_nat n)"
   including undefined_transfer integer.lifting unfolding uint_test_bit_def
   by transfer (auto cong: conj_cong dest: test_bit_size simp add: word_size)
 
 lemma uint_test_bit_code [code]:
   "uint_test_bit w n =
   (if n < 0 \<or> dflt_size_integer \<le> n then undefined (test_bit :: uint \<Rightarrow> _) w n else Rep_uint w !! nat_of_integer n)"
 unfolding uint_test_bit_def
 by(simp add: test_bit_uint.rep_eq)
 
 code_printing constant uint_test_bit \<rightharpoonup>
   (SML) "Uint.test'_bit" and
   (Eval) "(raise (Fail \"Machine dependent code\"))" and
   (Quickcheck) "Uint.test'_bit" and
   (Haskell) "Data'_Bits.testBitBounded" and
   (OCaml) "Uint.test'_bit" and
   (Scala) "Uint.test'_bit"
 
 definition uint_set_bit :: "uint \<Rightarrow> integer \<Rightarrow> bool \<Rightarrow> uint"
 where [code del]:
   "uint_set_bit x n b =
   (if n < 0 \<or> dflt_size_integer \<le> n then undefined (set_bit :: uint \<Rightarrow> _) x n b
    else set_bit x (nat_of_integer n) b)"
 
 lemma set_bit_uint_code [code]:
   "set_bit x n b = (if n < dflt_size then uint_set_bit x (integer_of_nat n) b else x)"
   including undefined_transfer integer.lifting unfolding uint_set_bit_def
   by (transfer) (auto cong: conj_cong simp add: not_less set_bit_beyond word_size)
 
 lemma uint_set_bit_code [code abstract]:
   "Rep_uint (uint_set_bit w n b) = 
   (if n < 0 \<or> dflt_size_integer \<le> n then Rep_uint (undefined (set_bit :: uint \<Rightarrow> _) w n b)
    else set_bit (Rep_uint w) (nat_of_integer n) b)"
 including undefined_transfer integer.lifting unfolding uint_set_bit_def by transfer simp
 
 code_printing constant uint_set_bit \<rightharpoonup>
   (SML) "Uint.set'_bit" and
   (Eval) "(raise (Fail \"Machine dependent code\"))" and
   (Quickcheck) "Uint.set'_bit" and
   (Haskell) "Data'_Bits.setBitBounded" and
   (OCaml) "Uint.set'_bit" and
   (Scala) "Uint.set'_bit"
 
 lift_definition uint_set_bits :: "(nat \<Rightarrow> bool) \<Rightarrow> uint \<Rightarrow> nat \<Rightarrow> uint" is set_bits_aux .
 
 lemma uint_set_bits_code [code]:
   "uint_set_bits f w n =
   (if n = 0 then w 
    else let n' = n - 1 in uint_set_bits f ((w << 1) OR (if f n' then 1 else 0)) n')"
 by(transfer fixing: n)(cases n, simp_all)
 
 lemma set_bits_uint [code]:
   "(BITS n. f n) = uint_set_bits f 0 dflt_size"
   by transfer (simp add: set_bits_conv_set_bits_aux)
 
 lemma lsb_code [code]: fixes x :: uint shows "lsb x = x !! 0"
 by transfer(simp add: word_lsb_def word_test_bit_def)
 
 definition uint_shiftl :: "uint \<Rightarrow> integer \<Rightarrow> uint"
 where [code del]:
   "uint_shiftl x n = (if n < 0 \<or> dflt_size_integer \<le> n then undefined (shiftl :: uint \<Rightarrow> _) x n else x << (nat_of_integer n))"
 
 lemma shiftl_uint_code [code]: "x << n = (if n < dflt_size then uint_shiftl x (integer_of_nat n) else 0)"
 including undefined_transfer integer.lifting unfolding uint_shiftl_def
 by transfer(simp add: not_less shiftl_zero_size word_size)
 
 lemma uint_shiftl_code [code abstract]:
   "Rep_uint (uint_shiftl w n) =
   (if n < 0 \<or> dflt_size_integer \<le> n then Rep_uint (undefined (shiftl :: uint \<Rightarrow> _) w n) else Rep_uint w << (nat_of_integer n))"
 including undefined_transfer integer.lifting unfolding uint_shiftl_def by transfer simp
 
 code_printing constant uint_shiftl \<rightharpoonup>
   (SML) "Uint.shiftl" and
   (Eval) "(raise (Fail \"Machine dependent code\"))" and
   (Quickcheck) "Uint.shiftl" and
   (Haskell) "Data'_Bits.shiftlBounded" and
   (OCaml) "Uint.shiftl" and
   (Scala) "Uint.shiftl"
 
 definition uint_shiftr :: "uint \<Rightarrow> integer \<Rightarrow> uint"
 where [code del]:
   "uint_shiftr x n = (if n < 0 \<or> dflt_size_integer \<le> n then undefined (shiftr :: uint \<Rightarrow> _) x n else x >> (nat_of_integer n))"
 
 lemma shiftr_uint_code [code]: "x >> n = (if n < dflt_size then uint_shiftr x (integer_of_nat n) else 0)"
 including undefined_transfer integer.lifting unfolding uint_shiftr_def
 by transfer(simp add: not_less shiftr_zero_size word_size)
 
 lemma uint_shiftr_code [code abstract]:
   "Rep_uint (uint_shiftr w n) =
   (if n < 0 \<or> dflt_size_integer \<le> n then Rep_uint (undefined (shiftr :: uint \<Rightarrow> _) w n) else Rep_uint w >> nat_of_integer n)"
 including undefined_transfer unfolding uint_shiftr_def by transfer simp
 
 code_printing constant uint_shiftr \<rightharpoonup>
   (SML) "Uint.shiftr" and
   (Eval) "(raise (Fail \"Machine dependent code\"))" and
   (Quickcheck) "Uint.shiftr" and
   (Haskell) "Data'_Bits.shiftrBounded" and
   (OCaml) "Uint.shiftr" and
   (Scala) "Uint.shiftr"
 
 definition uint_sshiftr :: "uint \<Rightarrow> integer \<Rightarrow> uint"
 where [code del]:
   "uint_sshiftr x n =
   (if n < 0 \<or> dflt_size_integer \<le> n then undefined sshiftr_uint x n else sshiftr_uint x (nat_of_integer n))"
 
 lemma sshiftr_beyond: fixes x :: "'a :: len word" shows
   "size x \<le> n \<Longrightarrow> x >>> n = (if x !! (size x - 1) then -1 else 0)"
 by(rule word_eqI)(simp add: nth_sshiftr word_size)
 
 lemma sshiftr_uint_code [code]:
   "x >>> n = 
   (if n < dflt_size then uint_sshiftr x (integer_of_nat n) else 
     if x !! wivs_index then -1 else 0)"
 including undefined_transfer integer.lifting unfolding uint_sshiftr_def
 by transfer(simp add: not_less sshiftr_beyond word_size wivs_index_def)
 
 lemma uint_sshiftr_code [code abstract]:
   "Rep_uint (uint_sshiftr w n) =
   (if n < 0 \<or> dflt_size_integer \<le> n then Rep_uint (undefined sshiftr_uint w n) else Rep_uint w >>> (nat_of_integer n))"
 including undefined_transfer unfolding uint_sshiftr_def by transfer simp
 
 code_printing constant uint_sshiftr \<rightharpoonup>
   (SML) "Uint.shiftr'_signed" and
   (Eval) "(raise (Fail \"Machine dependent code\"))" and
   (Quickcheck) "Uint.shiftr'_signed" and
   (Haskell) 
     "(Prelude.fromInteger (Prelude.toInteger (Data'_Bits.shiftrBounded (Prelude.fromInteger (Prelude.toInteger _) :: Uint.Int) _)) :: Uint.Word)" and
   (OCaml) "Uint.shiftr'_signed" and
   (Scala) "Uint.shiftr'_signed"
 
 lemma uint_msb_test_bit: "msb x \<longleftrightarrow> (x :: uint) !! wivs_index"
 by transfer(simp add: msb_nth wivs_index_def)
 
 lemma msb_uint_code [code]: "msb x \<longleftrightarrow> uint_test_bit x wivs_index_integer"
   apply(simp add: uint_test_bit_def uint_msb_test_bit 
   wivs_index_integer_code dflt_size_integer_def wivs_index_def)
   by (metis (full_types) One_nat_def dflt_size(2) less_iff_diff_less_0 
     nat_of_integer_of_nat of_nat_1 of_nat_diff of_nat_less_0_iff wivs_index_def)
 
 lemma uint_of_int_code [code]: "uint_of_int i = (BITS n. i !! n)"
 by transfer(simp add: word_of_int_conv_set_bits test_bit_int_def[abs_def])
 
 section \<open>Quickcheck setup\<close>
 
 definition uint_of_natural :: "natural \<Rightarrow> uint"
 where "uint_of_natural x \<equiv> Uint (integer_of_natural x)"
 
 instantiation uint :: "{random, exhaustive, full_exhaustive}" begin
 definition "random_uint \<equiv> qc_random_cnv uint_of_natural"
 definition "exhaustive_uint \<equiv> qc_exhaustive_cnv uint_of_natural"
 definition "full_exhaustive_uint \<equiv> qc_full_exhaustive_cnv uint_of_natural"
 instance ..
 end
 
 instantiation uint :: narrowing begin
 
 interpretation quickcheck_narrowing_samples
   "\<lambda>i. (Uint i, Uint (- i))" "0"
   "Typerep.Typerep (STR ''Uint.uint'') []" .
 
 definition "narrowing_uint d = qc_narrowing_drawn_from (narrowing_samples d) d"
 declare [[code drop: "partial_term_of :: uint itself \<Rightarrow> _"]]
 lemmas partial_term_of_uint [code] = partial_term_of_code
 
 instance ..
 end
 
 no_notation sshiftr_uint (infixl ">>>" 55)
 
 end
diff --git a/thys/Native_Word/Uint16.thy b/thys/Native_Word/Uint16.thy
--- a/thys/Native_Word/Uint16.thy
+++ b/thys/Native_Word/Uint16.thy
@@ -1,525 +1,525 @@
 (*  Title:      Uint16.thy
     Author:     Andreas Lochbihler, ETH Zurich
 *)
 
 chapter \<open>Unsigned words of 16 bits\<close>
 
 theory Uint16 imports
   Code_Target_Word_Base
 begin
 
 text \<open>
   Restriction for ML code generation:
   This theory assumes that the ML system provides a Word16
   implementation (mlton does, but PolyML 5.5 does not).
   Therefore, the code setup lives in the target \<open>SML_word\<close>
   rather than \<open>SML\<close>.  This ensures that code generation still
   works as long as \<open>uint16\<close> is not involved.
   For the target \<open>SML\<close> itself, no special code generation 
   for this type is set up. Nevertheless, it should work by emulation via @{typ "16 word"} 
   if the theory \<open>Code_Target_Bits_Int\<close> is imported.
 
   Restriction for OCaml code generation:
   OCaml does not provide an int16 type, so no special code generation 
   for this type is set up.
 \<close>
 
 declare prod.Quotient[transfer_rule]
 
 section \<open>Type definition and primitive operations\<close>
 
 typedef uint16 = "UNIV :: 16 word set" ..
 
 setup_lifting type_definition_uint16
 
 text \<open>Use an abstract type for code generation to disable pattern matching on @{term Abs_uint16}.\<close>
 declare Rep_uint16_inverse[code abstype]
 
 declare Quotient_uint16[transfer_rule]
 
 instantiation uint16 :: "{neg_numeral, modulo, comm_monoid_mult, comm_ring}" begin
 lift_definition zero_uint16 :: uint16 is "0" .
 lift_definition one_uint16 :: uint16 is "1" .
 lift_definition plus_uint16 :: "uint16 \<Rightarrow> uint16 \<Rightarrow> uint16" is "(+)" .
 lift_definition minus_uint16 :: "uint16 \<Rightarrow> uint16 \<Rightarrow> uint16" is "(-)" .
 lift_definition uminus_uint16 :: "uint16 \<Rightarrow> uint16" is uminus .
 lift_definition times_uint16 :: "uint16 \<Rightarrow> uint16 \<Rightarrow> uint16" is "(*)" .
 lift_definition divide_uint16 :: "uint16 \<Rightarrow> uint16 \<Rightarrow> uint16" is "(div)" .
 lift_definition modulo_uint16 :: "uint16 \<Rightarrow> uint16 \<Rightarrow> uint16" is "(mod)" .
 instance by standard (transfer, simp add: algebra_simps)+
 end
 
 instantiation uint16 :: linorder begin
 lift_definition less_uint16 :: "uint16 \<Rightarrow> uint16 \<Rightarrow> bool" is "(<)" .
 lift_definition less_eq_uint16 :: "uint16 \<Rightarrow> uint16 \<Rightarrow> bool" is "(\<le>)" .
 instance by standard (transfer, simp add: less_le_not_le linear)+
 end
 
 lemmas [code] = less_uint16.rep_eq less_eq_uint16.rep_eq
 
 instantiation uint16 :: bit_operations begin
-lift_definition bitNOT_uint16 :: "uint16 \<Rightarrow> uint16" is bitNOT .
-lift_definition bitAND_uint16 :: "uint16 \<Rightarrow> uint16 \<Rightarrow> uint16" is bitAND .
-lift_definition bitOR_uint16 :: "uint16 \<Rightarrow> uint16 \<Rightarrow> uint16" is bitOR .
-lift_definition bitXOR_uint16 :: "uint16 \<Rightarrow> uint16 \<Rightarrow> uint16" is bitXOR .
+lift_definition bitNOT_uint16 :: "uint16 \<Rightarrow> uint16" is NOT .
+lift_definition bitAND_uint16 :: "uint16 \<Rightarrow> uint16 \<Rightarrow> uint16" is \<open>(AND)\<close> .
+lift_definition bitOR_uint16 :: "uint16 \<Rightarrow> uint16 \<Rightarrow> uint16" is \<open>(OR)\<close> .
+lift_definition bitXOR_uint16 :: "uint16 \<Rightarrow> uint16 \<Rightarrow> uint16" is \<open>(XOR)\<close> .
 lift_definition test_bit_uint16 :: "uint16 \<Rightarrow> nat \<Rightarrow> bool" is test_bit .
 lift_definition set_bit_uint16 :: "uint16 \<Rightarrow> nat \<Rightarrow> bool \<Rightarrow> uint16" is set_bit .
 lift_definition lsb_uint16 :: "uint16 \<Rightarrow> bool" is lsb .
 lift_definition shiftl_uint16 :: "uint16 \<Rightarrow> nat \<Rightarrow> uint16" is shiftl .
 lift_definition shiftr_uint16 :: "uint16 \<Rightarrow> nat \<Rightarrow> uint16" is shiftr .
 lift_definition msb_uint16 :: "uint16 \<Rightarrow> bool" is msb .
 instance ..
 end
 
 instantiation uint16 :: bit_comprehension begin
 lift_definition set_bits_uint16 :: "(nat \<Rightarrow> bool) \<Rightarrow> uint16" is "set_bits" .
 instance ..
 end
 
 lemmas [code] = test_bit_uint16.rep_eq lsb_uint16.rep_eq msb_uint16.rep_eq
 
 instantiation uint16 :: equal begin
 lift_definition equal_uint16 :: "uint16 \<Rightarrow> uint16 \<Rightarrow> bool" is "equal_class.equal" .
 instance by standard (transfer, simp add: equal_eq)
 end
 
 lemmas [code] = equal_uint16.rep_eq
 
 instantiation uint16 :: size begin
 lift_definition size_uint16 :: "uint16 \<Rightarrow> nat" is "size" .
 instance ..
 end
 
 lemmas [code] = size_uint16.rep_eq
 
 lift_definition sshiftr_uint16 :: "uint16 \<Rightarrow> nat \<Rightarrow> uint16" (infixl ">>>" 55) is sshiftr .
 
 lift_definition uint16_of_int :: "int \<Rightarrow> uint16" is "word_of_int" .
 
 definition uint16_of_nat :: "nat \<Rightarrow> uint16"
 where "uint16_of_nat = uint16_of_int \<circ> int"
 
 lift_definition int_of_uint16 :: "uint16 \<Rightarrow> int" is "uint" .
 lift_definition nat_of_uint16 :: "uint16 \<Rightarrow> nat" is "unat" .
 
 definition integer_of_uint16 :: "uint16 \<Rightarrow> integer"
 where "integer_of_uint16 = integer_of_int o int_of_uint16"
 
 text \<open>Use pretty numerals from integer for pretty printing\<close>
 
 context includes integer.lifting begin
 
 lift_definition Uint16 :: "integer \<Rightarrow> uint16" is "word_of_int" .
 
 lemma Rep_uint16_numeral [simp]: "Rep_uint16 (numeral n) = numeral n"
 by(induction n)(simp_all add: one_uint16_def Abs_uint16_inverse numeral.simps plus_uint16_def)
 
 lemma Rep_uint16_neg_numeral [simp]: "Rep_uint16 (- numeral n) = - numeral n"
 by(simp only: uminus_uint16_def)(simp add: Abs_uint16_inverse)
 
 lemma numeral_uint16_transfer [transfer_rule]:
   "(rel_fun (=) cr_uint16) numeral numeral"
 by(auto simp add: cr_uint16_def)
 
 lemma numeral_uint16 [code_unfold]: "numeral n = Uint16 (numeral n)"
 by transfer simp
 
 lemma neg_numeral_uint16 [code_unfold]: "- numeral n = Uint16 (- numeral n)"
 by transfer(simp add: cr_uint16_def)
 
 end
 
 lemma Abs_uint16_numeral [code_post]: "Abs_uint16 (numeral n) = numeral n"
 by(induction n)(simp_all add: one_uint16_def numeral.simps plus_uint16_def Abs_uint16_inverse)
 
 lemma Abs_uint16_0 [code_post]: "Abs_uint16 0 = 0"
 by(simp add: zero_uint16_def)
 
 lemma Abs_uint16_1 [code_post]: "Abs_uint16 1 = 1"
 by(simp add: one_uint16_def)
 
 section \<open>Code setup\<close>
 
 code_printing code_module Uint16 \<rightharpoonup> (SML_word)
 \<open>(* Test that words can handle numbers between 0 and 15 *)
 val _ = if 4 <= Word.wordSize then () else raise (Fail ("wordSize less than 4"));
 
 structure Uint16 : sig
   val set_bit : Word16.word -> IntInf.int -> bool -> Word16.word
   val shiftl : Word16.word -> IntInf.int -> Word16.word
   val shiftr : Word16.word -> IntInf.int -> Word16.word
   val shiftr_signed : Word16.word -> IntInf.int -> Word16.word
   val test_bit : Word16.word -> IntInf.int -> bool
 end = struct
 
 fun set_bit x n b =
   let val mask = Word16.<< (0wx1, Word.fromLargeInt (IntInf.toLarge n))
   in if b then Word16.orb (x, mask)
      else Word16.andb (x, Word16.notb mask)
   end
 
 fun shiftl x n =
   Word16.<< (x, Word.fromLargeInt (IntInf.toLarge n))
 
 fun shiftr x n =
   Word16.>> (x, Word.fromLargeInt (IntInf.toLarge n))
 
 fun shiftr_signed x n =
   Word16.~>> (x, Word.fromLargeInt (IntInf.toLarge n))
 
 fun test_bit x n =
   Word16.andb (x, Word16.<< (0wx1, Word.fromLargeInt (IntInf.toLarge n))) <> Word16.fromInt 0
 
 end; (* struct Uint16 *)\<close>
 code_reserved SML_word Uint16
 
 code_printing code_module Uint16 \<rightharpoonup> (Haskell)
  \<open>module Uint16(Int16, Word16) where
 
   import Data.Int(Int16)
   import Data.Word(Word16)\<close>
 code_reserved Haskell Uint16
 
 text \<open>Scala provides unsigned 16-bit numbers as Char.\<close>
 
 code_printing code_module Uint16 \<rightharpoonup> (Scala)
 \<open>object Uint16 {
 
 def set_bit(x: scala.Char, n: BigInt, b: Boolean) : scala.Char =
   if (b)
     (x | (1.toChar << n.intValue)).toChar
   else
     (x & (1.toChar << n.intValue).unary_~).toChar
 
 def shiftl(x: scala.Char, n: BigInt) : scala.Char = (x << n.intValue).toChar
 
 def shiftr(x: scala.Char, n: BigInt) : scala.Char = (x >>> n.intValue).toChar
 
 def shiftr_signed(x: scala.Char, n: BigInt) : scala.Char = (x.toShort >> n.intValue).toChar
 
 def test_bit(x: scala.Char, n: BigInt) : Boolean = (x & (1.toChar << n.intValue)) != 0
 
 } /* object Uint16 */\<close>
 code_reserved Scala Uint16
 
 text \<open>
   Avoid @{term Abs_uint16} in generated code, use @{term Rep_uint16'} instead. 
   The symbolic implementations for code\_simp use @{term Rep_uint16}.
 
   The new destructor @{term Rep_uint16'} is executable.
   As the simplifier is given the [code abstract] equations literally, 
   we cannot implement @{term Rep_uint16} directly, because that makes code\_simp loop.
 
   If code generation raises Match, some equation probably contains @{term Rep_uint16} 
   ([code abstract] equations for @{typ uint16} may use @{term Rep_uint16} because
   these instances will be folded away.)
 
   To convert @{typ "16 word"} values into @{typ uint16}, use @{term "Abs_uint16'"}.
 \<close>
 
 definition Rep_uint16' where [simp]: "Rep_uint16' = Rep_uint16"
 
 lemma Rep_uint16'_transfer [transfer_rule]:
   "rel_fun cr_uint16 (=) (\<lambda>x. x) Rep_uint16'"
 unfolding Rep_uint16'_def by(rule uint16.rep_transfer)
 
 lemma Rep_uint16'_code [code]: "Rep_uint16' x = (BITS n. x !! n)"
 by transfer simp
 
 lift_definition Abs_uint16' :: "16 word \<Rightarrow> uint16" is "\<lambda>x :: 16 word. x" .
 
 lemma Abs_uint16'_code [code]:
   "Abs_uint16' x = Uint16 (integer_of_int (uint x))"
 including integer.lifting by transfer simp
 
 declare [[code drop: "term_of_class.term_of :: uint16 \<Rightarrow> _"]]
 
 lemma term_of_uint16_code [code]:
   defines "TR \<equiv> typerep.Typerep" and "bit0 \<equiv> STR ''Numeral_Type.bit0''" shows
   "term_of_class.term_of x = 
    Code_Evaluation.App (Code_Evaluation.Const (STR ''Uint16.uint16.Abs_uint16'') (TR (STR ''fun'') [TR (STR ''Word.word'') [TR bit0 [TR bit0 [TR bit0 [TR bit0 [TR (STR ''Numeral_Type.num1'') []]]]]], TR (STR ''Uint16.uint16'') []]))
        (term_of_class.term_of (Rep_uint16' x))"
 by(simp add: term_of_anything)
 
 lemma Uin16_code [code abstract]: "Rep_uint16 (Uint16 i) = word_of_int (int_of_integer_symbolic i)"
 unfolding Uint16_def int_of_integer_symbolic_def by(simp add: Abs_uint16_inverse)
 
 code_printing
   type_constructor uint16 \<rightharpoonup>
   (SML_word) "Word16.word" and
   (Haskell) "Uint16.Word16" and
   (Scala) "scala.Char"
 | constant Uint16 \<rightharpoonup>
   (SML_word) "Word16.fromLargeInt (IntInf.toLarge _)" and
   (Haskell) "(Prelude.fromInteger _ :: Uint16.Word16)" and
   (Haskell_Quickcheck) "(Prelude.fromInteger (Prelude.toInteger _) :: Uint16.Word16)" and
   (Scala) "_.charValue"
 | constant "0 :: uint16" \<rightharpoonup>
   (SML_word) "(Word16.fromInt 0)" and
   (Haskell) "(0 :: Uint16.Word16)" and
   (Scala) "0"
 | constant "1 :: uint16" \<rightharpoonup>
   (SML_word) "(Word16.fromInt 1)" and
   (Haskell) "(1 :: Uint16.Word16)" and
   (Scala) "1"
 | constant "plus :: uint16 \<Rightarrow> _ \<Rightarrow> _" \<rightharpoonup>
   (SML_word) "Word16.+ ((_), (_))" and
   (Haskell) infixl 6 "+" and
   (Scala) "(_ +/ _).toChar"
 | constant "uminus :: uint16 \<Rightarrow> _" \<rightharpoonup>
   (SML_word) "Word16.~" and
   (Haskell) "negate" and
   (Scala) "(- _).toChar"
 | constant "minus :: uint16 \<Rightarrow> _" \<rightharpoonup>
   (SML_word) "Word16.- ((_), (_))" and
   (Haskell) infixl 6 "-" and
   (Scala) "(_ -/ _).toChar"
 | constant "times :: uint16 \<Rightarrow> _ \<Rightarrow> _" \<rightharpoonup>
   (SML_word) "Word16.* ((_), (_))" and
   (Haskell) infixl 7 "*" and
   (Scala) "(_ */ _).toChar"
 | constant "HOL.equal :: uint16 \<Rightarrow> _ \<Rightarrow> bool" \<rightharpoonup>
   (SML_word) "!((_ : Word16.word) = _)" and
   (Haskell) infix 4 "==" and
   (Scala) infixl 5 "=="
 | class_instance uint16 :: equal \<rightharpoonup> (Haskell) -
 | constant "less_eq :: uint16 \<Rightarrow> _ \<Rightarrow> bool" \<rightharpoonup>
   (SML_word) "Word16.<= ((_), (_))" and
   (Haskell) infix 4 "<=" and
   (Scala) infixl 4 "<="
 | constant "less :: uint16 \<Rightarrow> _ \<Rightarrow> bool" \<rightharpoonup>
   (SML_word) "Word16.< ((_), (_))" and
   (Haskell) infix 4 "<" and
   (Scala) infixl 4 "<"
-| constant "bitNOT :: uint16 \<Rightarrow> _" \<rightharpoonup>
+| constant "NOT :: uint16 \<Rightarrow> _" \<rightharpoonup>
   (SML_word) "Word16.notb" and
   (Haskell) "Data'_Bits.complement" and
   (Scala) "_.unary'_~.toChar"
-| constant "bitAND :: uint16 \<Rightarrow> _" \<rightharpoonup>
+| constant "(AND) :: uint16 \<Rightarrow> _" \<rightharpoonup>
   (SML_word) "Word16.andb ((_),/ (_))" and
   (Haskell) infixl 7 "Data_Bits..&." and
   (Scala) "(_ & _).toChar"
-| constant "bitOR :: uint16 \<Rightarrow> _" \<rightharpoonup>
+| constant "(OR) :: uint16 \<Rightarrow> _" \<rightharpoonup>
   (SML_word) "Word16.orb ((_),/ (_))" and
   (Haskell) infixl 5 "Data_Bits..|." and
   (Scala) "(_ | _).toChar"
-| constant "bitXOR :: uint16 \<Rightarrow> _" \<rightharpoonup>
+| constant "(XOR) :: uint16 \<Rightarrow> _" \<rightharpoonup>
   (SML_word) "Word16.xorb ((_),/ (_))" and
   (Haskell) "Data'_Bits.xor" and
   (Scala) "(_ ^ _).toChar"
 
 definition uint16_div :: "uint16 \<Rightarrow> uint16 \<Rightarrow> uint16" 
 where "uint16_div x y = (if y = 0 then undefined ((div) :: uint16 \<Rightarrow> _) x (0 :: uint16) else x div y)"
 
 definition uint16_mod :: "uint16 \<Rightarrow> uint16 \<Rightarrow> uint16" 
 where "uint16_mod x y = (if y = 0 then undefined ((mod) :: uint16 \<Rightarrow> _) x (0 :: uint16) else x mod y)"
 
 context includes undefined_transfer begin
 
 lemma div_uint16_code [code]: "x div y = (if y = 0 then 0 else uint16_div x y)"
 unfolding uint16_div_def by transfer (simp add: word_div_def)
 
 lemma mod_uint16_code [code]: "x mod y = (if y = 0 then x else uint16_mod x y)"
 unfolding uint16_mod_def by transfer (simp add: word_mod_def)
 
 lemma uint16_div_code [code abstract]:
   "Rep_uint16 (uint16_div x y) =
   (if y = 0 then Rep_uint16 (undefined ((div) :: uint16 \<Rightarrow> _) x (0 :: uint16)) else Rep_uint16 x div Rep_uint16 y)"
 unfolding uint16_div_def by transfer simp
 
 lemma uint16_mod_code [code abstract]:
   "Rep_uint16 (uint16_mod x y) =
   (if y = 0 then Rep_uint16 (undefined ((mod) :: uint16 \<Rightarrow> _) x (0 :: uint16)) else Rep_uint16 x mod Rep_uint16 y)"
 unfolding uint16_mod_def by transfer simp
 
 end
 
 code_printing constant uint16_div \<rightharpoonup>
   (SML_word) "Word16.div ((_), (_))" and
   (Haskell) "Prelude.div" and
   (Scala) "(_ '/ _).toChar"
 | constant uint16_mod \<rightharpoonup>
   (SML_word) "Word16.mod ((_), (_))" and
   (Haskell) "Prelude.mod" and
   (Scala) "(_ % _).toChar"
 
 definition uint16_test_bit :: "uint16 \<Rightarrow> integer \<Rightarrow> bool"
 where [code del]:
   "uint16_test_bit x n =
   (if n < 0 \<or> 15 < n then undefined (test_bit :: uint16 \<Rightarrow> _) x n
    else x !! (nat_of_integer n))"
 
 lemma test_bit_uint16_code [code]:
   "test_bit x n \<longleftrightarrow> n < 16 \<and> uint16_test_bit x (integer_of_nat n)"
 unfolding uint16_test_bit_def including undefined_transfer integer.lifting 
 by transfer(auto cong: conj_cong dest: test_bit_size simp add: word_size)
 
 lemma uint16_test_bit_code [code]:
   "uint16_test_bit w n =
   (if n < 0 \<or> 15 < n then undefined (test_bit :: uint16 \<Rightarrow> _) w n else Rep_uint16 w !! nat_of_integer n)"
 unfolding uint16_test_bit_def by(simp add: test_bit_uint16.rep_eq)
 
 code_printing constant uint16_test_bit \<rightharpoonup>
   (SML_word) "Uint16.test'_bit" and
   (Haskell) "Data'_Bits.testBitBounded" and
   (Scala) "Uint16.test'_bit"
 
 definition uint16_set_bit :: "uint16 \<Rightarrow> integer \<Rightarrow> bool \<Rightarrow> uint16"
 where [code del]:
   "uint16_set_bit x n b =
   (if n < 0 \<or> 15 < n then undefined (set_bit :: uint16 \<Rightarrow> _) x n b
    else set_bit x (nat_of_integer n) b)"
 
 lemma set_bit_uint16_code [code]:
   "set_bit x n b = (if n < 16 then uint16_set_bit x (integer_of_nat n) b else x)"
 including undefined_transfer integer.lifting unfolding uint16_set_bit_def
 by(transfer)(auto cong: conj_cong simp add: not_less set_bit_beyond word_size)
 
 lemma uint16_set_bit_code [code abstract]:
   "Rep_uint16 (uint16_set_bit w n b) = 
   (if n < 0 \<or> 15 < n then Rep_uint16 (undefined (set_bit :: uint16 \<Rightarrow> _) w n b)
    else set_bit (Rep_uint16 w) (nat_of_integer n) b)"
 including undefined_transfer unfolding uint16_set_bit_def by transfer simp
 
 code_printing constant uint16_set_bit \<rightharpoonup>
   (SML_word) "Uint16.set'_bit" and
   (Haskell) "Data'_Bits.setBitBounded" and
   (Scala) "Uint16.set'_bit"
 
 lift_definition uint16_set_bits :: "(nat \<Rightarrow> bool) \<Rightarrow> uint16 \<Rightarrow> nat \<Rightarrow> uint16" is set_bits_aux .
 
 lemma uint16_set_bits_code [code]:
   "uint16_set_bits f w n =
   (if n = 0 then w 
    else let n' = n - 1 in uint16_set_bits f ((w << 1) OR (if f n' then 1 else 0)) n')"
 by(transfer fixing: n)(cases n, simp_all)
 
 lemma set_bits_uint16 [code]:
   "(BITS n. f n) = uint16_set_bits f 0 16"
 by transfer(simp add: set_bits_conv_set_bits_aux)
 
 
 lemma lsb_code [code]: fixes x :: uint16 shows "lsb x = x !! 0"
 by transfer(simp add: word_lsb_def word_test_bit_def)
 
 
 definition uint16_shiftl :: "uint16 \<Rightarrow> integer \<Rightarrow> uint16"
 where [code del]:
   "uint16_shiftl x n = (if n < 0 \<or> 16 \<le> n then undefined (shiftl :: uint16 \<Rightarrow> _) x n else x << (nat_of_integer n))"
 
 lemma shiftl_uint16_code [code]: "x << n = (if n < 16 then uint16_shiftl x (integer_of_nat n) else 0)"
 including undefined_transfer integer.lifting unfolding uint16_shiftl_def
 by transfer(simp add: not_less shiftl_zero_size word_size)
 
 lemma uint16_shiftl_code [code abstract]:
   "Rep_uint16 (uint16_shiftl w n) =
   (if n < 0 \<or> 16 \<le> n then Rep_uint16 (undefined (shiftl :: uint16 \<Rightarrow> _) w n)
    else Rep_uint16 w << nat_of_integer n)"
 including undefined_transfer unfolding uint16_shiftl_def by transfer simp
 
 code_printing constant uint16_shiftl \<rightharpoonup>
   (SML_word) "Uint16.shiftl" and
   (Haskell) "Data'_Bits.shiftlBounded" and
   (Scala) "Uint16.shiftl"
 
 definition uint16_shiftr :: "uint16 \<Rightarrow> integer \<Rightarrow> uint16"
 where [code del]:
   "uint16_shiftr x n = (if n < 0 \<or> 16 \<le> n then undefined (shiftr :: uint16 \<Rightarrow> _) x n else x >> (nat_of_integer n))"
 
 lemma shiftr_uint16_code [code]: "x >> n = (if n < 16 then uint16_shiftr x (integer_of_nat n) else 0)"
 including undefined_transfer integer.lifting unfolding uint16_shiftr_def
 by transfer(simp add: not_less shiftr_zero_size word_size)
 
 lemma uint16_shiftr_code [code abstract]:
   "Rep_uint16 (uint16_shiftr w n) =
   (if n < 0 \<or> 16 \<le> n then Rep_uint16 (undefined (shiftr :: uint16 \<Rightarrow> _) w n)
    else Rep_uint16 w >> nat_of_integer n)"
 including undefined_transfer unfolding uint16_shiftr_def by transfer simp
 
 code_printing constant uint16_shiftr \<rightharpoonup>
   (SML_word) "Uint16.shiftr" and
   (Haskell) "Data'_Bits.shiftrBounded" and
   (Scala) "Uint16.shiftr"
 
 definition uint16_sshiftr :: "uint16 \<Rightarrow> integer \<Rightarrow> uint16"
 where [code del]:
   "uint16_sshiftr x n =
   (if n < 0 \<or> 16 \<le> n then undefined sshiftr_uint16 x n else sshiftr_uint16 x (nat_of_integer n))"
 
 lemma sshiftr_beyond: fixes x :: "'a :: len word" shows
   "size x \<le> n \<Longrightarrow> x >>> n = (if x !! (size x - 1) then -1 else 0)"
 by(rule word_eqI)(simp add: nth_sshiftr word_size)
 
 lemma sshiftr_uint16_code [code]:
   "x >>> n = 
   (if n < 16 then uint16_sshiftr x (integer_of_nat n) else if x !! 15 then -1 else 0)"
 including undefined_transfer integer.lifting unfolding uint16_sshiftr_def
 by transfer (simp add: not_less sshiftr_beyond word_size)
 
 lemma uint16_sshiftr_code [code abstract]:
   "Rep_uint16 (uint16_sshiftr w n) =
   (if n < 0 \<or> 16 \<le> n then Rep_uint16 (undefined sshiftr_uint16 w n)
    else Rep_uint16 w >>> nat_of_integer n)"
 including undefined_transfer unfolding uint16_sshiftr_def by transfer simp
 
 code_printing constant uint16_sshiftr \<rightharpoonup>
   (SML_word) "Uint16.shiftr'_signed" and
   (Haskell) 
     "(Prelude.fromInteger (Prelude.toInteger (Data'_Bits.shiftrBounded (Prelude.fromInteger (Prelude.toInteger _) :: Uint16.Int16) _)) :: Uint16.Word16)" and
   (Scala) "Uint16.shiftr'_signed"
 
 lemma uint16_msb_test_bit: "msb x \<longleftrightarrow> (x :: uint16) !! 15"
 by transfer(simp add: msb_nth)
 
 lemma msb_uint16_code [code]: "msb x \<longleftrightarrow> uint16_test_bit x 15"
 by(simp add: uint16_test_bit_def uint16_msb_test_bit)
 
 lemma uint16_of_int_code [code]: "uint16_of_int i = Uint16 (integer_of_int i)"
 including integer.lifting by transfer simp
 
 lemma int_of_uint16_code [code]:
   "int_of_uint16 x = int_of_integer (integer_of_uint16 x)"
 by(simp add: integer_of_uint16_def)
 
 lemma nat_of_uint16_code [code]:
   "nat_of_uint16 x = nat_of_integer (integer_of_uint16 x)"
 unfolding integer_of_uint16_def including integer.lifting by transfer (simp add: unat_def)
 
 lemma integer_of_uint16_code [code]:
   "integer_of_uint16 n = integer_of_int (uint (Rep_uint16' n))"
 unfolding integer_of_uint16_def by transfer auto
 
 code_printing
   constant "integer_of_uint16" \<rightharpoonup>
   (SML_word) "Word16.toInt _ : IntInf.int" and
   (Haskell) "Prelude.toInteger" and
   (Scala) "BigInt"
 
 section \<open>Quickcheck setup\<close>
 
 definition uint16_of_natural :: "natural \<Rightarrow> uint16"
 where "uint16_of_natural x \<equiv> Uint16 (integer_of_natural x)"
 
 instantiation uint16 :: "{random, exhaustive, full_exhaustive}" begin
 definition "random_uint16 \<equiv> qc_random_cnv uint16_of_natural"
 definition "exhaustive_uint16 \<equiv> qc_exhaustive_cnv uint16_of_natural"
 definition "full_exhaustive_uint16 \<equiv> qc_full_exhaustive_cnv uint16_of_natural"
 instance ..
 end
 
 instantiation uint16 :: narrowing begin
 
 interpretation quickcheck_narrowing_samples
   "\<lambda>i. let x = Uint16 i in (x, 0xFFFF - x)" "0"
   "Typerep.Typerep (STR ''Uint16.uint16'') []" .
 
 definition "narrowing_uint16 d = qc_narrowing_drawn_from (narrowing_samples d) d"
 declare [[code drop: "partial_term_of :: uint16 itself \<Rightarrow> _"]]
 lemmas partial_term_of_uint16 [code] = partial_term_of_code
 
 instance ..
 end
 
 no_notation sshiftr_uint16 (infixl ">>>" 55)
 
 end
diff --git a/thys/Native_Word/Uint32.thy b/thys/Native_Word/Uint32.thy
--- a/thys/Native_Word/Uint32.thy
+++ b/thys/Native_Word/Uint32.thy
@@ -1,659 +1,659 @@
 (*  Title:      Uint32.thy
     Author:     Andreas Lochbihler, ETH Zurich
 *)
 
 chapter \<open>Unsigned words of 32 bits\<close>
 
 theory Uint32 imports
   Code_Target_Word_Base
 begin
 
 declare prod.Quotient[transfer_rule]
 
 section \<open>Type definition and primitive operations\<close>
 
 typedef uint32 = "UNIV :: 32 word set" .. 
 
 setup_lifting type_definition_uint32
 
 text \<open>Use an abstract type for code generation to disable pattern matching on @{term Abs_uint32}.\<close>
 declare Rep_uint32_inverse[code abstype]
 
 declare Quotient_uint32[transfer_rule]
 
 instantiation uint32 :: "{neg_numeral, modulo, comm_monoid_mult, comm_ring}" begin
 lift_definition zero_uint32 :: uint32 is "0 :: 32 word" .
 lift_definition one_uint32 :: uint32 is "1" .
 lift_definition plus_uint32 :: "uint32 \<Rightarrow> uint32 \<Rightarrow> uint32" is "(+) :: 32 word \<Rightarrow> _" .
 lift_definition minus_uint32 :: "uint32 \<Rightarrow> uint32 \<Rightarrow> uint32" is "(-)" .
 lift_definition uminus_uint32 :: "uint32 \<Rightarrow> uint32" is uminus .
 lift_definition times_uint32 :: "uint32 \<Rightarrow> uint32 \<Rightarrow> uint32" is "(*)" .
 lift_definition divide_uint32 :: "uint32 \<Rightarrow> uint32 \<Rightarrow> uint32" is "(div)" .
 lift_definition modulo_uint32 :: "uint32 \<Rightarrow> uint32 \<Rightarrow> uint32" is "(mod)" .
 instance by standard (transfer, simp add: algebra_simps)+
 end
 
 instantiation uint32 :: linorder begin
 lift_definition less_uint32 :: "uint32 \<Rightarrow> uint32 \<Rightarrow> bool" is "(<)" .
 lift_definition less_eq_uint32 :: "uint32 \<Rightarrow> uint32 \<Rightarrow> bool" is "(\<le>)" .
 instance by standard (transfer, simp add: less_le_not_le linear)+
 end
 
 lemmas [code] = less_uint32.rep_eq less_eq_uint32.rep_eq
 
 instantiation uint32 :: bit_operations begin
-lift_definition bitNOT_uint32 :: "uint32 \<Rightarrow> uint32" is bitNOT .
-lift_definition bitAND_uint32 :: "uint32 \<Rightarrow> uint32 \<Rightarrow> uint32" is bitAND .
-lift_definition bitOR_uint32 :: "uint32 \<Rightarrow> uint32 \<Rightarrow> uint32" is bitOR .
-lift_definition bitXOR_uint32 :: "uint32 \<Rightarrow> uint32 \<Rightarrow> uint32" is bitXOR .
+lift_definition bitNOT_uint32 :: "uint32 \<Rightarrow> uint32" is NOT .
+lift_definition bitAND_uint32 :: "uint32 \<Rightarrow> uint32 \<Rightarrow> uint32" is \<open>(AND)\<close> .
+lift_definition bitOR_uint32 :: "uint32 \<Rightarrow> uint32 \<Rightarrow> uint32" is \<open>(OR)\<close> .
+lift_definition bitXOR_uint32 :: "uint32 \<Rightarrow> uint32 \<Rightarrow> uint32" is \<open>(XOR)\<close> .
 lift_definition test_bit_uint32 :: "uint32 \<Rightarrow> nat \<Rightarrow> bool" is test_bit .
 lift_definition set_bit_uint32 :: "uint32 \<Rightarrow> nat \<Rightarrow> bool \<Rightarrow> uint32" is set_bit .
 lift_definition lsb_uint32 :: "uint32 \<Rightarrow> bool" is lsb .
 lift_definition shiftl_uint32 :: "uint32 \<Rightarrow> nat \<Rightarrow> uint32" is shiftl .
 lift_definition shiftr_uint32 :: "uint32 \<Rightarrow> nat \<Rightarrow> uint32" is shiftr .
 lift_definition msb_uint32 :: "uint32 \<Rightarrow> bool" is msb .
 instance ..
 end
 
 instantiation uint32 :: bit_comprehension begin
 lift_definition set_bits_uint32 :: "(nat \<Rightarrow> bool) \<Rightarrow> uint32" is "set_bits" .
 instance ..
 end
 
 lemmas [code] = test_bit_uint32.rep_eq lsb_uint32.rep_eq msb_uint32.rep_eq
 
 instantiation uint32 :: equal begin
 lift_definition equal_uint32 :: "uint32 \<Rightarrow> uint32 \<Rightarrow> bool" is "equal_class.equal" .
 instance by standard (transfer, simp add: equal_eq)
 end
 
 lemmas [code] = equal_uint32.rep_eq
 
 instantiation uint32 :: size begin
 lift_definition size_uint32 :: "uint32 \<Rightarrow> nat" is "size" .
 instance ..
 end
 
 lemmas [code] = size_uint32.rep_eq                                                    
 
 lift_definition sshiftr_uint32 :: "uint32 \<Rightarrow> nat \<Rightarrow> uint32" (infixl ">>>" 55) is sshiftr .
 
 lift_definition uint32_of_int :: "int \<Rightarrow> uint32" is "word_of_int" .
 
 definition uint32_of_nat :: "nat \<Rightarrow> uint32"
 where "uint32_of_nat = uint32_of_int \<circ> int"
 
 lift_definition int_of_uint32 :: "uint32 \<Rightarrow> int" is "uint" .
 lift_definition nat_of_uint32 :: "uint32 \<Rightarrow> nat" is "unat" .
 
 definition integer_of_uint32 :: "uint32 \<Rightarrow> integer"
 where "integer_of_uint32 = integer_of_int o int_of_uint32"
 
 lemma bitval_integer_transfer [transfer_rule]:
   "(rel_fun (=) pcr_integer) of_bool of_bool"
 by(auto simp add: of_bool_def integer.pcr_cr_eq cr_integer_def split: bit.split)
 
 text \<open>Use pretty numerals from integer for pretty printing\<close>
 
 context includes integer.lifting begin
 
 lift_definition Uint32 :: "integer \<Rightarrow> uint32" is "word_of_int" .
 
 lemma Rep_uint32_numeral [simp]: "Rep_uint32 (numeral n) = numeral n"
 by(induction n)(simp_all add: one_uint32_def Abs_uint32_inverse numeral.simps plus_uint32_def)
 
 lemma numeral_uint32_transfer [transfer_rule]:
   "(rel_fun (=) cr_uint32) numeral numeral"
 by(auto simp add: cr_uint32_def)
 
 lemma numeral_uint32 [code_unfold]: "numeral n = Uint32 (numeral n)"
 by transfer simp
 
 lemma Rep_uint32_neg_numeral [simp]: "Rep_uint32 (- numeral n) = - numeral n"
 by(simp only: uminus_uint32_def)(simp add: Abs_uint32_inverse)
 
 lemma neg_numeral_uint32 [code_unfold]: "- numeral n = Uint32 (- numeral n)"
 by transfer(simp add: cr_uint32_def)
 
 end
 
 lemma Abs_uint32_numeral [code_post]: "Abs_uint32 (numeral n) = numeral n"
 by(induction n)(simp_all add: one_uint32_def numeral.simps plus_uint32_def Abs_uint32_inverse)
 
 lemma Abs_uint32_0 [code_post]: "Abs_uint32 0 = 0"
 by(simp add: zero_uint32_def)
 
 lemma Abs_uint32_1 [code_post]: "Abs_uint32 1 = 1"
 by(simp add: one_uint32_def)
 
 section \<open>Code setup\<close>
 
 code_printing code_module Uint32 \<rightharpoonup> (SML)
 \<open>(* Test that words can handle numbers between 0 and 31 *)
 val _ = if 5 <= Word.wordSize then () else raise (Fail ("wordSize less than 5"));
 
 structure Uint32 : sig
   val set_bit : Word32.word -> IntInf.int -> bool -> Word32.word
   val shiftl : Word32.word -> IntInf.int -> Word32.word
   val shiftr : Word32.word -> IntInf.int -> Word32.word
   val shiftr_signed : Word32.word -> IntInf.int -> Word32.word
   val test_bit : Word32.word -> IntInf.int -> bool
 end = struct
 
 fun set_bit x n b =
   let val mask = Word32.<< (0wx1, Word.fromLargeInt (IntInf.toLarge n))
   in if b then Word32.orb (x, mask)
      else Word32.andb (x, Word32.notb mask)
   end
 
 fun shiftl x n =
   Word32.<< (x, Word.fromLargeInt (IntInf.toLarge n))
 
 fun shiftr x n =
   Word32.>> (x, Word.fromLargeInt (IntInf.toLarge n))
 
 fun shiftr_signed x n =
   Word32.~>> (x, Word.fromLargeInt (IntInf.toLarge n))
 
 fun test_bit x n =
   Word32.andb (x, Word32.<< (0wx1, Word.fromLargeInt (IntInf.toLarge n))) <> Word32.fromInt 0
 
 end; (* struct Uint32 *)\<close>
 code_reserved SML Uint32
 
 code_printing code_module Uint32 \<rightharpoonup> (Haskell)
  \<open>module Uint32(Int32, Word32) where
 
   import Data.Int(Int32)
   import Data.Word(Word32)\<close>
 code_reserved Haskell Uint32
 
 text \<open>
   OCaml and Scala provide only signed 32bit numbers, so we use these and 
   implement sign-sensitive operations like comparisons manually.
 \<close>
 code_printing code_module "Uint32" \<rightharpoonup> (OCaml)
 \<open>module Uint32 : sig
   val less : int32 -> int32 -> bool
   val less_eq : int32 -> int32 -> bool
   val set_bit : int32 -> Z.t -> bool -> int32
   val shiftl : int32 -> Z.t -> int32
   val shiftr : int32 -> Z.t -> int32
   val shiftr_signed : int32 -> Z.t -> int32
   val test_bit : int32 -> Z.t -> bool
 end = struct
 
 (* negative numbers have their highest bit set, 
    so they are greater than positive ones *)
 let less x y =
   if Int32.compare x Int32.zero < 0 then
     Int32.compare y Int32.zero < 0 && Int32.compare x y < 0
   else Int32.compare y Int32.zero < 0 || Int32.compare x y < 0;;
 
 let less_eq x y =
   if Int32.compare x Int32.zero < 0 then
     Int32.compare y Int32.zero < 0 && Int32.compare x y <= 0
   else Int32.compare y Int32.zero < 0 || Int32.compare x y <= 0;;
 
 let set_bit x n b =
   let mask = Int32.shift_left Int32.one (Z.to_int n)
   in if b then Int32.logor x mask
      else Int32.logand x (Int32.lognot mask);;
 
 let shiftl x n = Int32.shift_left x (Z.to_int n);;
 
 let shiftr x n = Int32.shift_right_logical x (Z.to_int n);;
 
 let shiftr_signed x n = Int32.shift_right x (Z.to_int n);;
 
 let test_bit x n =
   Int32.compare 
     (Int32.logand x (Int32.shift_left Int32.one (Z.to_int n)))
     Int32.zero
   <> 0;;
 
 end;; (*struct Uint32*)\<close>
 code_reserved OCaml Uint32
 
 code_printing code_module Uint32 \<rightharpoonup> (Scala)
 \<open>object Uint32 {
 
 def less(x: Int, y: Int) : Boolean =
   if (x < 0) y < 0 && x < y
   else y < 0 || x < y
 
 def less_eq(x: Int, y: Int) : Boolean =
   if (x < 0) y < 0 && x <= y
   else y < 0 || x <= y
 
 def set_bit(x: Int, n: BigInt, b: Boolean) : Int =
   if (b)
     x | (1 << n.intValue)
   else
     x & (1 << n.intValue).unary_~
 
 def shiftl(x: Int, n: BigInt) : Int = x << n.intValue
 
 def shiftr(x: Int, n: BigInt) : Int = x >>> n.intValue
 
 def shiftr_signed(x: Int, n: BigInt) : Int = x >> n.intValue
 
 def test_bit(x: Int, n: BigInt) : Boolean =
   (x & (1 << n.intValue)) != 0
 
 } /* object Uint32 */\<close>
 code_reserved Scala Uint32
 
 text \<open>
   OCaml's conversion from Big\_int to int32 demands that the value fits int a signed 32-bit integer.
   The following justifies the implementation.
 \<close>
 
 definition Uint32_signed :: "integer \<Rightarrow> uint32" 
 where "Uint32_signed i = (if i < -(0x80000000) \<or> i \<ge> 0x80000000 then undefined Uint32 i else Uint32 i)"
 
 lemma Uint32_code [code]:
   "Uint32 i = 
   (let i' = i AND 0xFFFFFFFF
    in if i' !! 31 then Uint32_signed (i' - 0x100000000) else Uint32_signed i')"
 including undefined_transfer integer.lifting unfolding Uint32_signed_def
 by transfer(rule word_of_int_via_signed, simp_all add: bin_mask_numeral)
 
 lemma Uint32_signed_code [code abstract]:
   "Rep_uint32 (Uint32_signed i) = 
   (if i < -(0x80000000) \<or> i \<ge> 0x80000000 then Rep_uint32 (undefined Uint32 i) else word_of_int (int_of_integer_symbolic i))"
 unfolding Uint32_signed_def Uint32_def int_of_integer_symbolic_def word_of_integer_def
 by(simp add: Abs_uint32_inverse)
 
 text \<open>
   Avoid @{term Abs_uint32} in generated code, use @{term Rep_uint32'} instead. 
   The symbolic implementations for code\_simp use @{term Rep_uint32}.
 
   The new destructor @{term Rep_uint32'} is executable.
   As the simplifier is given the [code abstract] equations literally, 
   we cannot implement @{term Rep_uint32} directly, because that makes code\_simp loop.
 
   If code generation raises Match, some equation probably contains @{term Rep_uint32} 
   ([code abstract] equations for @{typ uint32} may use @{term Rep_uint32} because
   these instances will be folded away.)
 
   To convert @{typ "32 word"} values into @{typ uint32}, use @{term "Abs_uint32'"}.
 \<close>
 
 definition Rep_uint32' where [simp]: "Rep_uint32' = Rep_uint32"
 
 lemma Rep_uint32'_transfer [transfer_rule]:
   "rel_fun cr_uint32 (=) (\<lambda>x. x) Rep_uint32'"
 unfolding Rep_uint32'_def by(rule uint32.rep_transfer)
 
 lemma Rep_uint32'_code [code]: "Rep_uint32' x = (BITS n. x !! n)"
 by transfer simp
 
 lift_definition Abs_uint32' :: "32 word \<Rightarrow> uint32" is "\<lambda>x :: 32 word. x" .
 
 lemma Abs_uint32'_code [code]:
   "Abs_uint32' x = Uint32 (integer_of_int (uint x))"
 including integer.lifting by transfer simp
 
 declare [[code drop: "term_of_class.term_of :: uint32 \<Rightarrow> _"]]
 
 lemma term_of_uint32_code [code]:
   defines "TR \<equiv> typerep.Typerep" and "bit0 \<equiv> STR ''Numeral_Type.bit0''" 
   shows
   "term_of_class.term_of x = 
    Code_Evaluation.App (Code_Evaluation.Const (STR ''Uint32.uint32.Abs_uint32'') (TR (STR ''fun'') [TR (STR ''Word.word'') [TR bit0 [TR bit0 [TR bit0 [TR bit0 [TR bit0 [TR (STR ''Numeral_Type.num1'') []]]]]]], TR (STR ''Uint32.uint32'') []]))
        (term_of_class.term_of (Rep_uint32' x))"
 by(simp add: term_of_anything)
 
 code_printing
   type_constructor uint32 \<rightharpoonup>
   (SML) "Word32.word" and
   (Haskell) "Uint32.Word32" and
   (OCaml) "int32" and
   (Scala) "Int" and
   (Eval) "Word32.word"
 | constant Uint32 \<rightharpoonup>
   (SML) "Word32.fromLargeInt (IntInf.toLarge _)" and
   (Haskell) "(Prelude.fromInteger _ :: Uint32.Word32)" and
   (Haskell_Quickcheck) "(Prelude.fromInteger (Prelude.toInteger _) :: Uint32.Word32)" and
   (Scala) "_.intValue"
 | constant Uint32_signed \<rightharpoonup>
   (OCaml) "Z.to'_int32"
 | constant "0 :: uint32" \<rightharpoonup>
   (SML) "(Word32.fromInt 0)" and
   (Haskell) "(0 :: Uint32.Word32)" and
   (OCaml) "Int32.zero" and
   (Scala) "0"
 | constant "1 :: uint32" \<rightharpoonup>
   (SML) "(Word32.fromInt 1)" and
   (Haskell) "(1 :: Uint32.Word32)" and
   (OCaml) "Int32.one" and
   (Scala) "1"
 | constant "plus :: uint32 \<Rightarrow> _ " \<rightharpoonup>
   (SML) "Word32.+ ((_), (_))" and
   (Haskell) infixl 6 "+" and
   (OCaml) "Int32.add" and
   (Scala) infixl 7 "+"
 | constant "uminus :: uint32 \<Rightarrow> _" \<rightharpoonup>
   (SML) "Word32.~" and
   (Haskell) "negate" and
   (OCaml) "Int32.neg" and
   (Scala) "!(- _)"
 | constant "minus :: uint32 \<Rightarrow> _" \<rightharpoonup>
   (SML) "Word32.- ((_), (_))" and
   (Haskell) infixl 6 "-" and
   (OCaml) "Int32.sub" and
   (Scala) infixl 7 "-"
 | constant "times :: uint32 \<Rightarrow> _ \<Rightarrow> _" \<rightharpoonup>
   (SML) "Word32.* ((_), (_))" and
   (Haskell) infixl 7 "*" and
   (OCaml) "Int32.mul" and
   (Scala) infixl 8 "*"
 | constant "HOL.equal :: uint32 \<Rightarrow> _ \<Rightarrow> bool" \<rightharpoonup>
   (SML) "!((_ : Word32.word) = _)" and
   (Haskell) infix 4 "==" and
   (OCaml) "(Int32.compare _ _ = 0)" and
   (Scala) infixl 5 "=="
 | class_instance uint32 :: equal \<rightharpoonup>
   (Haskell) -
 | constant "less_eq :: uint32 \<Rightarrow> _ \<Rightarrow> bool" \<rightharpoonup>
   (SML) "Word32.<= ((_), (_))" and
   (Haskell) infix 4 "<=" and
   (OCaml) "Uint32.less'_eq" and
   (Scala) "Uint32.less'_eq"
 | constant "less :: uint32 \<Rightarrow> _ \<Rightarrow> bool" \<rightharpoonup>
   (SML) "Word32.< ((_), (_))" and
   (Haskell) infix 4 "<" and
   (OCaml) "Uint32.less" and
   (Scala) "Uint32.less"
-| constant "bitNOT :: uint32 \<Rightarrow> _" \<rightharpoonup>
+| constant "NOT :: uint32 \<Rightarrow> _" \<rightharpoonup>
   (SML) "Word32.notb" and
   (Haskell) "Data'_Bits.complement" and
   (OCaml) "Int32.lognot" and
   (Scala) "_.unary'_~"
-| constant "bitAND :: uint32 \<Rightarrow> _" \<rightharpoonup>
+| constant "(AND) :: uint32 \<Rightarrow> _" \<rightharpoonup>
   (SML) "Word32.andb ((_),/ (_))" and
   (Haskell) infixl 7 "Data_Bits..&." and
   (OCaml) "Int32.logand" and
   (Scala) infixl 3 "&"
-| constant "bitOR :: uint32 \<Rightarrow> _" \<rightharpoonup>
+| constant "(OR) :: uint32 \<Rightarrow> _" \<rightharpoonup>
   (SML) "Word32.orb ((_),/ (_))" and
   (Haskell) infixl 5 "Data_Bits..|." and
   (OCaml) "Int32.logor" and
   (Scala) infixl 1 "|"
-| constant "bitXOR :: uint32 \<Rightarrow> _" \<rightharpoonup>
+| constant "(XOR) :: uint32 \<Rightarrow> _" \<rightharpoonup>
   (SML) "Word32.xorb ((_),/ (_))" and
   (Haskell) "Data'_Bits.xor" and
   (OCaml) "Int32.logxor" and
   (Scala) infixl 2 "^"
 
 definition uint32_divmod :: "uint32 \<Rightarrow> uint32 \<Rightarrow> uint32 \<times> uint32" where
   "uint32_divmod x y = 
   (if y = 0 then (undefined ((div) :: uint32 \<Rightarrow> _) x (0 :: uint32), undefined ((mod) :: uint32 \<Rightarrow> _) x (0 :: uint32)) 
   else (x div y, x mod y))"
 
 definition uint32_div :: "uint32 \<Rightarrow> uint32 \<Rightarrow> uint32" 
 where "uint32_div x y = fst (uint32_divmod x y)"
 
 definition uint32_mod :: "uint32 \<Rightarrow> uint32 \<Rightarrow> uint32" 
 where "uint32_mod x y = snd (uint32_divmod x y)"
 
 lemma div_uint32_code [code]: "x div y = (if y = 0 then 0 else uint32_div x y)"
 including undefined_transfer unfolding uint32_divmod_def uint32_div_def
 by transfer (simp add: word_div_def)
 
 lemma mod_uint32_code [code]: "x mod y = (if y = 0 then x else uint32_mod x y)"
 including undefined_transfer unfolding uint32_mod_def uint32_divmod_def
 by transfer (simp add: word_mod_def)
 
 definition uint32_sdiv :: "uint32 \<Rightarrow> uint32 \<Rightarrow> uint32"
 where [code del]:
   "uint32_sdiv x y =
    (if y = 0 then undefined ((div) :: uint32 \<Rightarrow> _) x (0 :: uint32)
     else Abs_uint32 (Rep_uint32 x sdiv Rep_uint32 y))"
 
 definition div0_uint32 :: "uint32 \<Rightarrow> uint32"
 where [code del]: "div0_uint32 x = undefined ((div) :: uint32 \<Rightarrow> _) x (0 :: uint32)"
 declare [[code abort: div0_uint32]]
 
 definition mod0_uint32 :: "uint32 \<Rightarrow> uint32"
 where [code del]: "mod0_uint32 x = undefined ((mod) :: uint32 \<Rightarrow> _) x (0 :: uint32)"
 declare [[code abort: mod0_uint32]]
 
 lemma uint32_divmod_code [code]:
   "uint32_divmod x y =
   (if 0x80000000 \<le> y then if x < y then (0, x) else (1, x - y)
    else if y = 0 then (div0_uint32 x, mod0_uint32 x)
    else let q = (uint32_sdiv (x >> 1) y) << 1;
             r = x - q * y
         in if r \<ge> y then (q + 1, r - y) else (q, r))"
 including undefined_transfer unfolding uint32_divmod_def uint32_sdiv_def div0_uint32_def mod0_uint32_def
 by transfer(simp add: divmod_via_sdivmod)
 
 lemma uint32_sdiv_code [code abstract]:
   "Rep_uint32 (uint32_sdiv x y) =
    (if y = 0 then Rep_uint32 (undefined ((div) :: uint32 \<Rightarrow> _) x (0 :: uint32))
     else Rep_uint32 x sdiv Rep_uint32 y)"
 unfolding uint32_sdiv_def by(simp add: Abs_uint32_inverse)
 
 text \<open>
   Note that we only need a translation for signed division, but not for the remainder
   because @{thm uint32_divmod_code} computes both with division only.
 \<close>
 
 code_printing
   constant uint32_div \<rightharpoonup>
   (SML) "Word32.div ((_), (_))" and
   (Haskell) "Prelude.div"
 | constant uint32_mod \<rightharpoonup>
   (SML) "Word32.mod ((_), (_))" and
   (Haskell) "Prelude.mod"
 | constant uint32_divmod \<rightharpoonup>
   (Haskell) "divmod"
 | constant uint32_sdiv \<rightharpoonup>
   (OCaml) "Int32.div" and
   (Scala) "_ '/ _"
 
 definition uint32_test_bit :: "uint32 \<Rightarrow> integer \<Rightarrow> bool"
 where [code del]:
   "uint32_test_bit x n =
   (if n < 0 \<or> 31 < n then undefined (test_bit :: uint32 \<Rightarrow> _) x n
    else x !! (nat_of_integer n))"
 
 lemma test_bit_uint32_code [code]:
   "test_bit x n \<longleftrightarrow> n < 32 \<and> uint32_test_bit x (integer_of_nat n)"
 including undefined_transfer integer.lifting unfolding uint32_test_bit_def
 by transfer(auto cong: conj_cong dest: test_bit_size simp add: word_size)
 
 lemma uint32_test_bit_code [code]:
   "uint32_test_bit w n =
   (if n < 0 \<or> 31 < n then undefined (test_bit :: uint32 \<Rightarrow> _) w n else Rep_uint32 w !! nat_of_integer n)"
 unfolding uint32_test_bit_def
 by(simp add: test_bit_uint32.rep_eq)
 
 code_printing constant uint32_test_bit \<rightharpoonup>
   (SML) "Uint32.test'_bit" and
   (Haskell) "Data'_Bits.testBitBounded" and
   (OCaml) "Uint32.test'_bit" and
   (Scala) "Uint32.test'_bit" and
   (Eval) "(fn w => fn n => if n < 0 orelse 32 <= n then raise (Fail \"argument to uint32'_test'_bit out of bounds\") else Uint32.test'_bit w n)"
 
 definition uint32_set_bit :: "uint32 \<Rightarrow> integer \<Rightarrow> bool \<Rightarrow> uint32"
 where [code del]:
   "uint32_set_bit x n b =
   (if n < 0 \<or> 31 < n then undefined (set_bit :: uint32 \<Rightarrow> _) x n b
    else set_bit x (nat_of_integer n) b)"
 
 lemma set_bit_uint32_code [code]:
   "set_bit x n b = (if n < 32 then uint32_set_bit x (integer_of_nat n) b else x)"
 including undefined_transfer integer.lifting unfolding uint32_set_bit_def
 by(transfer)(auto cong: conj_cong simp add: not_less set_bit_beyond word_size)
 
 lemma uint32_set_bit_code [code abstract]:
   "Rep_uint32 (uint32_set_bit w n b) = 
   (if n < 0 \<or> 31 < n then Rep_uint32 (undefined (set_bit :: uint32 \<Rightarrow> _) w n b)
    else set_bit (Rep_uint32 w) (nat_of_integer n) b)"
 including undefined_transfer unfolding uint32_set_bit_def by transfer simp
 
 code_printing constant uint32_set_bit \<rightharpoonup>
   (SML) "Uint32.set'_bit" and
   (Haskell) "Data'_Bits.setBitBounded" and
   (OCaml) "Uint32.set'_bit" and
   (Scala) "Uint32.set'_bit" and
   (Eval) "(fn w => fn n => fn b => if n < 0 orelse 32 <= n then raise (Fail \"argument to uint32'_set'_bit out of bounds\") else Uint32.set'_bit x n b)"
 
 lift_definition uint32_set_bits :: "(nat \<Rightarrow> bool) \<Rightarrow> uint32 \<Rightarrow> nat \<Rightarrow> uint32" is set_bits_aux .
 
 lemma uint32_set_bits_code [code]:
   "uint32_set_bits f w n =
   (if n = 0 then w 
    else let n' = n - 1 in uint32_set_bits f ((w << 1) OR (if f n' then 1 else 0)) n')"
 by(transfer fixing: n)(cases n, simp_all)
 
 lemma set_bits_uint32 [code]:
   "(BITS n. f n) = uint32_set_bits f 0 32"
 by transfer(simp add: set_bits_conv_set_bits_aux)
 
 
 lemma lsb_code [code]: fixes x :: uint32 shows "lsb x = x !! 0"
 by transfer(simp add: word_lsb_def word_test_bit_def)
 
 
 definition uint32_shiftl :: "uint32 \<Rightarrow> integer \<Rightarrow> uint32"
 where [code del]:
   "uint32_shiftl x n = (if n < 0 \<or> 32 \<le> n then undefined (shiftl :: uint32 \<Rightarrow> _) x n else x << (nat_of_integer n))"
 
 lemma shiftl_uint32_code [code]: "x << n = (if n < 32 then uint32_shiftl x (integer_of_nat n) else 0)"
 including undefined_transfer integer.lifting unfolding uint32_shiftl_def
 by transfer(simp add: not_less shiftl_zero_size word_size)
 
 lemma uint32_shiftl_code [code abstract]:
   "Rep_uint32 (uint32_shiftl w n) =
   (if n < 0 \<or> 32 \<le> n then Rep_uint32 (undefined (shiftl :: uint32 \<Rightarrow> _) w n) else Rep_uint32 w << (nat_of_integer n))"
 including undefined_transfer unfolding uint32_shiftl_def by transfer simp
 
 code_printing constant uint32_shiftl \<rightharpoonup>
   (SML) "Uint32.shiftl" and
   (Haskell) "Data'_Bits.shiftlBounded" and
   (OCaml) "Uint32.shiftl" and
   (Scala) "Uint32.shiftl" and
   (Eval) "(fn x => fn i => if i < 0 orelse i >= 32 then raise Fail \"argument to uint32'_shiftl out of bounds\" else Uint32.shiftl x i)"
 
 definition uint32_shiftr :: "uint32 \<Rightarrow> integer \<Rightarrow> uint32"
 where [code del]:
   "uint32_shiftr x n = (if n < 0 \<or> 32 \<le> n then undefined (shiftr :: uint32 \<Rightarrow> _) x n else x >> (nat_of_integer n))"
 
 lemma shiftr_uint32_code [code]: "x >> n = (if n < 32 then uint32_shiftr x (integer_of_nat n) else 0)"
 including undefined_transfer integer.lifting unfolding uint32_shiftr_def
 by transfer(simp add: not_less shiftr_zero_size word_size)
 
 lemma uint32_shiftr_code [code abstract]:
   "Rep_uint32 (uint32_shiftr w n) =
   (if n < 0 \<or> 32 \<le> n then Rep_uint32 (undefined (shiftr :: uint32 \<Rightarrow> _) w n) else Rep_uint32 w >> nat_of_integer n)"
 including undefined_transfer unfolding uint32_shiftr_def by transfer simp
 
 code_printing constant uint32_shiftr \<rightharpoonup>
   (SML) "Uint32.shiftr" and
   (Haskell) "Data'_Bits.shiftrBounded" and
   (OCaml) "Uint32.shiftr" and
   (Scala) "Uint32.shiftr" and
   (Eval) "(fn x => fn i => if i < 0 orelse i >= 32 then raise Fail \"argument to uint32'_shiftr out of bounds\" else Uint32.shiftr x i)"
 
 definition uint32_sshiftr :: "uint32 \<Rightarrow> integer \<Rightarrow> uint32"
 where [code del]:
   "uint32_sshiftr x n =
   (if n < 0 \<or> 32 \<le> n then undefined sshiftr_uint32 x n else sshiftr_uint32 x (nat_of_integer n))"
 
 lemma sshiftr_beyond: fixes x :: "'a :: len word" shows
   "size x \<le> n \<Longrightarrow> x >>> n = (if x !! (size x - 1) then -1 else 0)"
 by(rule word_eqI)(simp add: nth_sshiftr word_size)
 
 lemma sshiftr_uint32_code [code]:
   "x >>> n = 
   (if n < 32 then uint32_sshiftr x (integer_of_nat n) else if x !! 31 then -1 else 0)"
 including undefined_transfer integer.lifting unfolding uint32_sshiftr_def
 by transfer(simp add: not_less sshiftr_beyond word_size)
 
 lemma uint32_sshiftr_code [code abstract]:
   "Rep_uint32 (uint32_sshiftr w n) =
   (if n < 0 \<or> 32 \<le> n then Rep_uint32 (undefined sshiftr_uint32 w n) else Rep_uint32 w >>> (nat_of_integer n))"
 including undefined_transfer unfolding uint32_sshiftr_def by transfer simp
 
 code_printing constant uint32_sshiftr \<rightharpoonup>
   (SML) "Uint32.shiftr'_signed" and
   (Haskell) 
     "(Prelude.fromInteger (Prelude.toInteger (Data'_Bits.shiftrBounded (Prelude.fromInteger (Prelude.toInteger _) :: Uint32.Int32) _)) :: Uint32.Word32)" and
   (OCaml) "Uint32.shiftr'_signed" and
   (Scala) "Uint32.shiftr'_signed" and
   (Eval) "(fn x => fn i => if i < 0 orelse i >= 32 then raise Fail \"argument to uint32'_shiftr'_signed out of bounds\" else Uint32.shiftr'_signed x i)"
 
 lemma uint32_msb_test_bit: "msb x \<longleftrightarrow> (x :: uint32) !! 31"
 by transfer(simp add: msb_nth)
 
 lemma msb_uint32_code [code]: "msb x \<longleftrightarrow> uint32_test_bit x 31"
 by(simp add: uint32_test_bit_def uint32_msb_test_bit)
 
 lemma uint32_of_int_code [code]: "uint32_of_int i = Uint32 (integer_of_int i)"
 including integer.lifting by transfer simp
 
 lemma int_of_uint32_code [code]:
   "int_of_uint32 x = int_of_integer (integer_of_uint32 x)"
 by(simp add: integer_of_uint32_def)
 
 lemma nat_of_uint32_code [code]:
   "nat_of_uint32 x = nat_of_integer (integer_of_uint32 x)"
 unfolding integer_of_uint32_def including integer.lifting by transfer (simp add: unat_def)
 
 definition integer_of_uint32_signed :: "uint32 \<Rightarrow> integer"
 where
   "integer_of_uint32_signed n = (if n !! 31 then undefined integer_of_uint32 n else integer_of_uint32 n)"
 
 lemma integer_of_uint32_signed_code [code]:
   "integer_of_uint32_signed n =
   (if n !! 31 then undefined integer_of_uint32 n else integer_of_int (uint (Rep_uint32' n)))"
 unfolding integer_of_uint32_signed_def integer_of_uint32_def
 including undefined_transfer by transfer simp
 
 lemma integer_of_uint32_code [code]:
   "integer_of_uint32 n =
   (if n !! 31 then integer_of_uint32_signed (n AND 0x7FFFFFFF) OR 0x80000000 else integer_of_uint32_signed n)"
 unfolding integer_of_uint32_def integer_of_uint32_signed_def o_def
 including undefined_transfer integer.lifting
 by transfer(auto simp add: word_ao_nth uint_and_mask_or_full mask_numeral mask_Suc_0 intro!: uint_and_mask_or_full[symmetric])
 
 code_printing
   constant "integer_of_uint32" \<rightharpoonup>
   (SML) "IntInf.fromLarge (Word32.toLargeInt _) : IntInf.int" and
   (Haskell) "Prelude.toInteger"
 | constant "integer_of_uint32_signed" \<rightharpoonup>
   (OCaml) "Z.of'_int32" and
   (Scala) "BigInt"
 
 section \<open>Quickcheck setup\<close>
 
 definition uint32_of_natural :: "natural \<Rightarrow> uint32"
 where "uint32_of_natural x \<equiv> Uint32 (integer_of_natural x)"
 
 instantiation uint32 :: "{random, exhaustive, full_exhaustive}" begin
 definition "random_uint32 \<equiv> qc_random_cnv uint32_of_natural"
 definition "exhaustive_uint32 \<equiv> qc_exhaustive_cnv uint32_of_natural"
 definition "full_exhaustive_uint32 \<equiv> qc_full_exhaustive_cnv uint32_of_natural"
 instance ..
 end
 
 instantiation uint32 :: narrowing begin
 
 interpretation quickcheck_narrowing_samples
   "\<lambda>i. let x = Uint32 i in (x, 0xFFFFFFFF - x)" "0"
   "Typerep.Typerep (STR ''Uint32.uint32'') []" .
 
 definition "narrowing_uint32 d = qc_narrowing_drawn_from (narrowing_samples d) d"
 declare [[code drop: "partial_term_of :: uint32 itself \<Rightarrow> _"]]
 lemmas partial_term_of_uint32 [code] = partial_term_of_code
 
 instance ..
 end
 
 no_notation sshiftr_uint32 (infixl ">>>" 55)
 
 end
diff --git a/thys/Native_Word/Uint64.thy b/thys/Native_Word/Uint64.thy
--- a/thys/Native_Word/Uint64.thy
+++ b/thys/Native_Word/Uint64.thy
@@ -1,860 +1,860 @@
 (*  Title:      Uint64.thy
     Author:     Andreas Lochbihler, ETH Zurich
 *)
 
 chapter \<open>Unsigned words of 64 bits\<close>
 
 theory Uint64 imports
   Code_Target_Word_Base
 begin
 
 text \<open>
   PolyML (in version 5.7) provides a Word64 structure only when run in 64-bit mode.
   Therefore, we by default provide an implementation of 64-bit words using \verb$IntInf.int$ and
   masking. The code target \texttt{SML\_word} replaces this implementation and maps the operations
   directly to the \verb$Word64$ structure provided by the Standard ML implementations.
 
   The \verb$Eval$ target used by @{command value} and @{method eval} dynamically tests at
   runtime for the version of PolyML and uses PolyML's Word64 structure if it detects a 64-bit 
   version which does not suffer from a division bug found in PolyML 5.6.
 \<close>
 
 declare prod.Quotient[transfer_rule]
 
 section \<open>Type definition and primitive operations\<close>
 
 typedef uint64 = "UNIV :: 64 word set" .. 
 
 setup_lifting type_definition_uint64
 
 text \<open>Use an abstract type for code generation to disable pattern matching on @{term Abs_uint64}.\<close>
 declare Rep_uint64_inverse[code abstype]
 
 declare Quotient_uint64[transfer_rule]
 
 instantiation uint64 :: "{neg_numeral, modulo, comm_monoid_mult, comm_ring}" begin
 lift_definition zero_uint64 :: uint64 is "0 :: 64 word" .
 lift_definition one_uint64 :: uint64 is "1" .
 lift_definition plus_uint64 :: "uint64 \<Rightarrow> uint64 \<Rightarrow> uint64" is "(+) :: 64 word \<Rightarrow> _" .
 lift_definition minus_uint64 :: "uint64 \<Rightarrow> uint64 \<Rightarrow> uint64" is "(-)" .
 lift_definition uminus_uint64 :: "uint64 \<Rightarrow> uint64" is uminus .
 lift_definition times_uint64 :: "uint64 \<Rightarrow> uint64 \<Rightarrow> uint64" is "(*)" .
 lift_definition divide_uint64 :: "uint64 \<Rightarrow> uint64 \<Rightarrow> uint64" is "(div)" .
 lift_definition modulo_uint64 :: "uint64 \<Rightarrow> uint64 \<Rightarrow> uint64" is "(mod)" .
 instance by standard (transfer, simp add: algebra_simps)+
 end
 
 instantiation uint64 :: linorder begin
 lift_definition less_uint64 :: "uint64 \<Rightarrow> uint64 \<Rightarrow> bool" is "(<)" .
 lift_definition less_eq_uint64 :: "uint64 \<Rightarrow> uint64 \<Rightarrow> bool" is "(\<le>)" .
 instance by standard (transfer, simp add: less_le_not_le linear)+
 end
 
 lemmas [code] = less_uint64.rep_eq less_eq_uint64.rep_eq
 
 instantiation uint64 :: bit_operations begin
-lift_definition bitNOT_uint64 :: "uint64 \<Rightarrow> uint64" is bitNOT .
-lift_definition bitAND_uint64 :: "uint64 \<Rightarrow> uint64 \<Rightarrow> uint64" is bitAND .
-lift_definition bitOR_uint64 :: "uint64 \<Rightarrow> uint64 \<Rightarrow> uint64" is bitOR .
-lift_definition bitXOR_uint64 :: "uint64 \<Rightarrow> uint64 \<Rightarrow> uint64" is bitXOR .
+lift_definition bitNOT_uint64 :: "uint64 \<Rightarrow> uint64" is NOT .
+lift_definition bitAND_uint64 :: "uint64 \<Rightarrow> uint64 \<Rightarrow> uint64" is \<open>(AND)\<close> .
+lift_definition bitOR_uint64 :: "uint64 \<Rightarrow> uint64 \<Rightarrow> uint64" is \<open>(OR)\<close> .
+lift_definition bitXOR_uint64 :: "uint64 \<Rightarrow> uint64 \<Rightarrow> uint64" is \<open>(XOR)\<close> .
 lift_definition test_bit_uint64 :: "uint64 \<Rightarrow> nat \<Rightarrow> bool" is test_bit .
 lift_definition set_bit_uint64 :: "uint64 \<Rightarrow> nat \<Rightarrow> bool \<Rightarrow> uint64" is set_bit .
 lift_definition lsb_uint64 :: "uint64 \<Rightarrow> bool" is lsb .
 lift_definition shiftl_uint64 :: "uint64 \<Rightarrow> nat \<Rightarrow> uint64" is shiftl .
 lift_definition shiftr_uint64 :: "uint64 \<Rightarrow> nat \<Rightarrow> uint64" is shiftr .
 lift_definition msb_uint64 :: "uint64 \<Rightarrow> bool" is msb .
 instance ..
 end
 
 instantiation uint64 :: bit_comprehension begin
 lift_definition set_bits_uint64 :: "(nat \<Rightarrow> bool) \<Rightarrow> uint64" is "set_bits" .
 instance ..
 end
 
 lemmas [code] = test_bit_uint64.rep_eq lsb_uint64.rep_eq msb_uint64.rep_eq
 
 instantiation uint64 :: equal begin
 lift_definition equal_uint64 :: "uint64 \<Rightarrow> uint64 \<Rightarrow> bool" is "equal_class.equal" .
 instance by standard (transfer, simp add: equal_eq)
 end
 
 lemmas [code] = equal_uint64.rep_eq
 
 instantiation uint64 :: size begin
 lift_definition size_uint64 :: "uint64 \<Rightarrow> nat" is "size" .
 instance ..
 end
 
 lemmas [code] = size_uint64.rep_eq
 
 lift_definition sshiftr_uint64 :: "uint64 \<Rightarrow> nat \<Rightarrow> uint64" (infixl ">>>" 55) is sshiftr .
 
 lift_definition uint64_of_int :: "int \<Rightarrow> uint64" is "word_of_int" .
 
 definition uint64_of_nat :: "nat \<Rightarrow> uint64"
 where "uint64_of_nat = uint64_of_int \<circ> int"
 
 lift_definition int_of_uint64 :: "uint64 \<Rightarrow> int" is "uint" .
 lift_definition nat_of_uint64 :: "uint64 \<Rightarrow> nat" is "unat" .
 
 definition integer_of_uint64 :: "uint64 \<Rightarrow> integer"
 where "integer_of_uint64 = integer_of_int o int_of_uint64"
 
 lemma bitval_integer_transfer [transfer_rule]:
   "(rel_fun (=) pcr_integer) of_bool of_bool"
 by(auto simp add: of_bool_def integer.pcr_cr_eq cr_integer_def split: bit.split)
 
 text \<open>Use pretty numerals from integer for pretty printing\<close>
 
 context includes integer.lifting begin
 
 lift_definition Uint64 :: "integer \<Rightarrow> uint64" is "word_of_int" .
 
 lemma Rep_uint64_numeral [simp]: "Rep_uint64 (numeral n) = numeral n"
 by(induction n)(simp_all add: one_uint64_def Abs_uint64_inverse numeral.simps plus_uint64_def)
 
 lemma numeral_uint64_transfer [transfer_rule]:
   "(rel_fun (=) cr_uint64) numeral numeral"
 by(auto simp add: cr_uint64_def)
 
 lemma numeral_uint64 [code_unfold]: "numeral n = Uint64 (numeral n)"
 by transfer simp
 
 lemma Rep_uint64_neg_numeral [simp]: "Rep_uint64 (- numeral n) = - numeral n"
 by(simp only: uminus_uint64_def)(simp add: Abs_uint64_inverse)
 
 lemma neg_numeral_uint64 [code_unfold]: "- numeral n = Uint64 (- numeral n)"
 by transfer(simp add: cr_uint64_def)
 
 end
 
 lemma Abs_uint64_numeral [code_post]: "Abs_uint64 (numeral n) = numeral n"
 by(induction n)(simp_all add: one_uint64_def numeral.simps plus_uint64_def Abs_uint64_inverse)
 
 lemma Abs_uint64_0 [code_post]: "Abs_uint64 0 = 0"
 by(simp add: zero_uint64_def)
 
 lemma Abs_uint64_1 [code_post]: "Abs_uint64 1 = 1"
 by(simp add: one_uint64_def)
 
 section \<open>Code setup\<close>
 
 text \<open> For SML, we generate an implementation of unsigned 64-bit words using \verb$IntInf.int$.
   If @{ML "LargeWord.wordSize > 63"} of the Isabelle/ML runtime environment holds, then we assume
   that there is also a \<open>Word64\<close> structure available and accordingly replace the implementation
   for the target \verb$Eval$.
 \<close>
 code_printing code_module "Uint64" \<rightharpoonup> (SML) \<open>(* Test that words can handle numbers between 0 and 63 *)
 val _ = if 6 <= Word.wordSize then () else raise (Fail ("wordSize less than 6"));
 
 structure Uint64 : sig
   eqtype uint64;
   val zero : uint64;
   val one : uint64;
   val fromInt : IntInf.int -> uint64;
   val toInt : uint64 -> IntInf.int;
   val toLarge : uint64 -> LargeWord.word;
   val fromLarge : LargeWord.word -> uint64
   val plus : uint64 -> uint64 -> uint64;
   val minus : uint64 -> uint64 -> uint64;
   val times : uint64 -> uint64 -> uint64;
   val divide : uint64 -> uint64 -> uint64;
   val modulus : uint64 -> uint64 -> uint64;
   val negate : uint64 -> uint64;
   val less_eq : uint64 -> uint64 -> bool;
   val less : uint64 -> uint64 -> bool;
   val notb : uint64 -> uint64;
   val andb : uint64 -> uint64 -> uint64;
   val orb : uint64 -> uint64 -> uint64;
   val xorb : uint64 -> uint64 -> uint64;
   val shiftl : uint64 -> IntInf.int -> uint64;
   val shiftr : uint64 -> IntInf.int -> uint64;
   val shiftr_signed : uint64 -> IntInf.int -> uint64;
   val set_bit : uint64 -> IntInf.int -> bool -> uint64;
   val test_bit : uint64 -> IntInf.int -> bool;
 end = struct
 
 type uint64 = IntInf.int;
 
 val mask = 0xFFFFFFFFFFFFFFFF : IntInf.int;
 
 val zero = 0 : IntInf.int;
 
 val one = 1 : IntInf.int;
 
 fun fromInt x = IntInf.andb(x, mask);
 
 fun toInt x = x
 
 fun toLarge x = LargeWord.fromLargeInt (IntInf.toLarge x);
 
 fun fromLarge x = IntInf.fromLarge (LargeWord.toLargeInt x);
 
 fun plus x y = IntInf.andb(IntInf.+(x, y), mask);
 
 fun minus x y = IntInf.andb(IntInf.-(x, y), mask);
 
 fun negate x = IntInf.andb(IntInf.~(x), mask);
 
 fun times x y = IntInf.andb(IntInf.*(x, y), mask);
 
 fun divide x y = IntInf.div(x, y);
 
 fun modulus x y = IntInf.mod(x, y);
 
 fun less_eq x y = IntInf.<=(x, y);
 
 fun less x y = IntInf.<(x, y);
 
 fun notb x = IntInf.andb(IntInf.notb(x), mask);
 
 fun orb x y = IntInf.orb(x, y);
 
 fun andb x y = IntInf.andb(x, y);
 
 fun xorb x y = IntInf.xorb(x, y);
 
 val maxWord = IntInf.pow (2, Word.wordSize);
 
 fun shiftl x n = 
   if n < maxWord then IntInf.andb(IntInf.<< (x, Word.fromLargeInt (IntInf.toLarge n)), mask)
   else 0;
 
 fun shiftr x n =
   if n < maxWord then IntInf.~>> (x, Word.fromLargeInt (IntInf.toLarge n))
   else 0;
 
 val msb_mask = 0x8000000000000000 : IntInf.int;
 
 fun shiftr_signed x i =
   if IntInf.andb(x, msb_mask) = 0 then shiftr x i
   else if i >= 64 then 0xFFFFFFFFFFFFFFFF
   else let
     val x' = shiftr x i
     val m' = IntInf.andb(IntInf.<<(mask, Word.max(0w64 - Word.fromLargeInt (IntInf.toLarge i), 0w0)), mask)
   in IntInf.orb(x', m') end;
 
 fun test_bit x n =
   if n < maxWord then IntInf.andb (x, IntInf.<< (1, Word.fromLargeInt (IntInf.toLarge n))) <> 0
   else false;
 
 fun set_bit x n b =
   if n < 64 then
     if b then IntInf.orb (x, IntInf.<< (1, Word.fromLargeInt (IntInf.toLarge n)))
     else IntInf.andb (x, IntInf.notb (IntInf.<< (1, Word.fromLargeInt (IntInf.toLarge n))))
   else x;
 
 end
 \<close>
 code_reserved SML Uint64
 
 setup \<open>
 let
   val polyml64 = LargeWord.wordSize > 63;
   (* PolyML 5.6 has bugs in its Word64 implementation. We test for one such bug and refrain
      from using Word64 in that case. Testing is done with dynamic code evaluation such that
      the compiler does not choke on the Word64 structure, which need not be present in a 32bit
      environment. *)
   val error_msg = "Buggy Word64 structure";
   val test_code = 
    "val _ = if Word64.div (0w18446744073709551611 : Word64.word, 0w3) = 0w6148914691236517203 then ()\n" ^
    "else raise (Fail \"" ^ error_msg ^ "\");";
   val f = Exn.interruptible_capture (fn () => ML_Compiler.eval ML_Compiler.flags Position.none (ML_Lex.tokenize test_code))
   val use_Word64 = polyml64 andalso
     (case f () of 
        Exn.Res _ => true
      | Exn.Exn (e as ERROR m) => if String.isSuffix error_msg m then false else Exn.reraise e
      | Exn.Exn e => Exn.reraise e)
     ;
 
   val newline = "\n";
   val content = 
     "structure Uint64 : sig" ^ newline ^
     "  eqtype uint64;" ^ newline ^
     "  val zero : uint64;" ^ newline ^
     "  val one : uint64;" ^ newline ^
     "  val fromInt : IntInf.int -> uint64;" ^ newline ^
     "  val toInt : uint64 -> IntInf.int;" ^ newline ^
     "  val toLarge : uint64 -> LargeWord.word;" ^ newline ^
     "  val fromLarge : LargeWord.word -> uint64" ^ newline ^
     "  val plus : uint64 -> uint64 -> uint64;" ^ newline ^
     "  val minus : uint64 -> uint64 -> uint64;" ^ newline ^
     "  val times : uint64 -> uint64 -> uint64;" ^ newline ^
     "  val divide : uint64 -> uint64 -> uint64;" ^ newline ^
     "  val modulus : uint64 -> uint64 -> uint64;" ^ newline ^
     "  val negate : uint64 -> uint64;" ^ newline ^
     "  val less_eq : uint64 -> uint64 -> bool;" ^ newline ^
     "  val less : uint64 -> uint64 -> bool;" ^ newline ^
     "  val notb : uint64 -> uint64;" ^ newline ^
     "  val andb : uint64 -> uint64 -> uint64;" ^ newline ^
     "  val orb : uint64 -> uint64 -> uint64;" ^ newline ^
     "  val xorb : uint64 -> uint64 -> uint64;" ^ newline ^
     "  val shiftl : uint64 -> IntInf.int -> uint64;" ^ newline ^
     "  val shiftr : uint64 -> IntInf.int -> uint64;" ^ newline ^
     "  val shiftr_signed : uint64 -> IntInf.int -> uint64;" ^ newline ^
     "  val set_bit : uint64 -> IntInf.int -> bool -> uint64;" ^ newline ^
     "  val test_bit : uint64 -> IntInf.int -> bool;" ^ newline ^
     "end = struct" ^ newline ^
     "" ^ newline ^
     "type uint64 = Word64.word;" ^ newline ^
     "" ^ newline ^
     "val zero = (0wx0 : uint64);" ^ newline ^
     "" ^ newline ^
     "val one = (0wx1 : uint64);" ^ newline ^
     "" ^ newline ^
     "fun fromInt x = Word64.fromLargeInt (IntInf.toLarge x);" ^ newline ^
     "" ^ newline ^
     "fun toInt x = IntInf.fromLarge (Word64.toLargeInt x);"  ^ newline ^
     "" ^ newline ^
     "fun fromLarge x = Word64.fromLarge x;" ^ newline ^
     "" ^ newline ^
     "fun toLarge x = Word64.toLarge x;"  ^ newline ^
     "" ^ newline ^
     "fun plus x y = Word64.+(x, y);" ^ newline ^
     "" ^ newline ^
     "fun minus x y = Word64.-(x, y);" ^ newline ^
     "" ^ newline ^
     "fun negate x = Word64.~(x);" ^ newline ^
     "" ^ newline ^
     "fun times x y = Word64.*(x, y);" ^ newline ^
     "" ^ newline ^
     "fun divide x y = Word64.div(x, y);" ^ newline ^
     "" ^ newline ^
     "fun modulus x y = Word64.mod(x, y);" ^ newline ^
     "" ^ newline ^
     "fun less_eq x y = Word64.<=(x, y);" ^ newline ^
     "" ^ newline ^
     "fun less x y = Word64.<(x, y);" ^ newline ^
     "" ^ newline ^
     "fun set_bit x n b =" ^ newline ^
     "  let val mask = Word64.<< (0wx1, Word.fromLargeInt (IntInf.toLarge n))" ^ newline ^
     "  in if b then Word64.orb (x, mask)" ^ newline ^
     "     else Word64.andb (x, Word64.notb mask)" ^ newline ^
     "  end" ^ newline ^
     "" ^ newline ^
     "fun shiftl x n =" ^ newline ^
     "  Word64.<< (x, Word.fromLargeInt (IntInf.toLarge n))" ^ newline ^
     "" ^ newline ^
     "fun shiftr x n =" ^ newline ^
     "  Word64.>> (x, Word.fromLargeInt (IntInf.toLarge n))" ^ newline ^
     "" ^ newline ^
     "fun shiftr_signed x n =" ^ newline ^
     "  Word64.~>> (x, Word.fromLargeInt (IntInf.toLarge n))" ^ newline ^
     "" ^ newline ^
     "fun test_bit x n =" ^ newline ^
     "  Word64.andb (x, Word64.<< (0wx1, Word.fromLargeInt (IntInf.toLarge n))) <> Word64.fromInt 0" ^ newline ^
     "" ^ newline ^
     "val notb = Word64.notb" ^ newline ^
     "" ^ newline ^
     "fun andb x y = Word64.andb(x, y);" ^ newline ^
     "" ^ newline ^
     "fun orb x y = Word64.orb(x, y);" ^ newline ^
     "" ^ newline ^
     "fun xorb x y = Word64.xorb(x, y);" ^ newline ^
     "" ^ newline ^
     "end (*struct Uint64*)"
   val target_SML64 = "SML_word";
 in
   (if use_Word64 then Code_Target.set_printings (Code_Symbol.Module ("Uint64", [(Code_Runtime.target, SOME (content, []))])) else I)
   #> Code_Target.set_printings (Code_Symbol.Module ("Uint64", [(target_SML64, SOME (content, []))]))
 end
 \<close>
 
 code_printing code_module Uint64 \<rightharpoonup> (Haskell)
  \<open>module Uint64(Int64, Word64) where
 
   import Data.Int(Int64)
   import Data.Word(Word64)\<close>
 code_reserved Haskell Uint64
 
 text \<open>
   OCaml and Scala provide only signed 64bit numbers, so we use these and 
   implement sign-sensitive operations like comparisons manually.
 \<close>
 code_printing code_module "Uint64" \<rightharpoonup> (OCaml)
 \<open>module Uint64 : sig
   val less : int64 -> int64 -> bool
   val less_eq : int64 -> int64 -> bool
   val set_bit : int64 -> Z.t -> bool -> int64
   val shiftl : int64 -> Z.t -> int64
   val shiftr : int64 -> Z.t -> int64
   val shiftr_signed : int64 -> Z.t -> int64
   val test_bit : int64 -> Z.t -> bool
 end = struct
 
 (* negative numbers have their highest bit set, 
    so they are greater than positive ones *)
 let less x y =
   if Int64.compare x Int64.zero < 0 then
     Int64.compare y Int64.zero < 0 && Int64.compare x y < 0
   else Int64.compare y Int64.zero < 0 || Int64.compare x y < 0;;
 
 let less_eq x y =
   if Int64.compare x Int64.zero < 0 then
     Int64.compare y Int64.zero < 0 && Int64.compare x y <= 0
   else Int64.compare y Int64.zero < 0 || Int64.compare x y <= 0;;
 
 let set_bit x n b =
   let mask = Int64.shift_left Int64.one (Z.to_int n)
   in if b then Int64.logor x mask
      else Int64.logand x (Int64.lognot mask);;
 
 let shiftl x n = Int64.shift_left x (Z.to_int n);;
 
 let shiftr x n = Int64.shift_right_logical x (Z.to_int n);;
 
 let shiftr_signed x n = Int64.shift_right x (Z.to_int n);;
 
 let test_bit x n =
   Int64.compare 
     (Int64.logand x (Int64.shift_left Int64.one (Z.to_int n)))
     Int64.zero
   <> 0;;
 
 end;; (*struct Uint64*)\<close>
 code_reserved OCaml Uint64
 
 code_printing code_module Uint64 \<rightharpoonup> (Scala)
 \<open>object Uint64 {
 
 def less(x: Long, y: Long) : Boolean =
   if (x < 0) y < 0 && x < y
   else y < 0 || x < y
 
 def less_eq(x: Long, y: Long) : Boolean =
   if (x < 0) y < 0 && x <= y
   else y < 0 || x <= y
 
 def set_bit(x: Long, n: BigInt, b: Boolean) : Long =
   if (b)
     x | (1L << n.intValue)
   else
     x & (1L << n.intValue).unary_~
 
 def shiftl(x: Long, n: BigInt) : Long = x << n.intValue
 
 def shiftr(x: Long, n: BigInt) : Long = x >>> n.intValue
 
 def shiftr_signed(x: Long, n: BigInt) : Long = x >> n.intValue
 
 def test_bit(x: Long, n: BigInt) : Boolean =
   (x & (1L << n.intValue)) != 0
 
 } /* object Uint64 */\<close>
 code_reserved Scala Uint64
 
 text \<open>
   OCaml's conversion from Big\_int to int64 demands that the value fits int a signed 64-bit integer.
   The following justifies the implementation.
 \<close>
 
 definition Uint64_signed :: "integer \<Rightarrow> uint64" 
 where "Uint64_signed i = (if i < -(0x8000000000000000) \<or> i \<ge> 0x8000000000000000 then undefined Uint64 i else Uint64 i)"
 
 lemma Uint64_code [code]:
   "Uint64 i = 
   (let i' = i AND 0xFFFFFFFFFFFFFFFF
    in if i' !! 63 then Uint64_signed (i' - 0x10000000000000000) else Uint64_signed i')"
 including undefined_transfer integer.lifting unfolding Uint64_signed_def
 by transfer(rule word_of_int_via_signed, simp_all add: bin_mask_numeral)
 
 lemma Uint64_signed_code [code abstract]:
   "Rep_uint64 (Uint64_signed i) = 
   (if i < -(0x8000000000000000) \<or> i \<ge> 0x8000000000000000 then Rep_uint64 (undefined Uint64 i) else word_of_int (int_of_integer_symbolic i))"
 unfolding Uint64_signed_def Uint64_def int_of_integer_symbolic_def word_of_integer_def
 by(simp add: Abs_uint64_inverse)
 
 text \<open>
   Avoid @{term Abs_uint64} in generated code, use @{term Rep_uint64'} instead. 
   The symbolic implementations for code\_simp use @{term Rep_uint64}.
 
   The new destructor @{term Rep_uint64'} is executable.
   As the simplifier is given the [code abstract] equations literally, 
   we cannot implement @{term Rep_uint64} directly, because that makes code\_simp loop.
 
   If code generation raises Match, some equation probably contains @{term Rep_uint64} 
   ([code abstract] equations for @{typ uint64} may use @{term Rep_uint64} because
   these instances will be folded away.)
 
   To convert @{typ "64 word"} values into @{typ uint64}, use @{term "Abs_uint64'"}.
 \<close>
 
 definition Rep_uint64' where [simp]: "Rep_uint64' = Rep_uint64"
 
 lemma Rep_uint64'_transfer [transfer_rule]:
   "rel_fun cr_uint64 (=) (\<lambda>x. x) Rep_uint64'"
 unfolding Rep_uint64'_def by(rule uint64.rep_transfer)
 
 lemma Rep_uint64'_code [code]: "Rep_uint64' x = (BITS n. x !! n)"
 by transfer simp
 
 lift_definition Abs_uint64' :: "64 word \<Rightarrow> uint64" is "\<lambda>x :: 64 word. x" .
 
 lemma Abs_uint64'_code [code]:
   "Abs_uint64' x = Uint64 (integer_of_int (uint x))"
 including integer.lifting by transfer simp
 
 declare [[code drop: "term_of_class.term_of :: uint64 \<Rightarrow> _"]]
 
 lemma term_of_uint64_code [code]:
   defines "TR \<equiv> typerep.Typerep" and "bit0 \<equiv> STR ''Numeral_Type.bit0''" 
   shows
   "term_of_class.term_of x = 
    Code_Evaluation.App (Code_Evaluation.Const (STR ''Uint64.uint64.Abs_uint64'') (TR (STR ''fun'') [TR (STR ''Word.word'') [TR bit0 [TR bit0 [TR bit0 [TR bit0 [TR bit0 [TR bit0 [TR (STR ''Numeral_Type.num1'') []]]]]]]], TR (STR ''Uint64.uint64'') []]))
        (term_of_class.term_of (Rep_uint64' x))"
 by(simp add: term_of_anything)
 
 code_printing
   type_constructor uint64 \<rightharpoonup>
   (SML) "Uint64.uint64" and
   (Haskell) "Uint64.Word64" and
   (OCaml) "int64" and
   (Scala) "Long"
 | constant Uint64 \<rightharpoonup>
   (SML) "Uint64.fromInt" and
   (Haskell) "(Prelude.fromInteger _ :: Uint64.Word64)" and
   (Haskell_Quickcheck) "(Prelude.fromInteger (Prelude.toInteger _) :: Uint64.Word64)" and
   (Scala) "_.longValue"
 | constant Uint64_signed \<rightharpoonup>
   (OCaml) "Z.to'_int64"
 | constant "0 :: uint64" \<rightharpoonup>
   (SML) "Uint64.zero" and
   (Haskell) "(0 :: Uint64.Word64)" and
   (OCaml) "Int64.zero" and
   (Scala) "0"
 | constant "1 :: uint64" \<rightharpoonup>
   (SML) "Uint64.one" and
   (Haskell) "(1 :: Uint64.Word64)" and
   (OCaml) "Int64.one" and
   (Scala) "1"
 | constant "plus :: uint64 \<Rightarrow> _ " \<rightharpoonup>
   (SML) "Uint64.plus" and
   (Haskell) infixl 6 "+" and
   (OCaml) "Int64.add" and
   (Scala) infixl 7 "+"
 | constant "uminus :: uint64 \<Rightarrow> _" \<rightharpoonup>
   (SML) "Uint64.negate" and
   (Haskell) "negate" and
   (OCaml) "Int64.neg" and
   (Scala) "!(- _)"
 | constant "minus :: uint64 \<Rightarrow> _" \<rightharpoonup>
   (SML) "Uint64.minus" and
   (Haskell) infixl 6 "-" and
   (OCaml) "Int64.sub" and
   (Scala) infixl 7 "-"
 | constant "times :: uint64 \<Rightarrow> _ \<Rightarrow> _" \<rightharpoonup>
   (SML) "Uint64.times" and
   (Haskell) infixl 7 "*" and
   (OCaml) "Int64.mul" and
   (Scala) infixl 8 "*"
 | constant "HOL.equal :: uint64 \<Rightarrow> _ \<Rightarrow> bool" \<rightharpoonup>
   (SML) "!((_ : Uint64.uint64) = _)" and
   (Haskell) infix 4 "==" and
   (OCaml) "(Int64.compare _ _ = 0)" and
   (Scala) infixl 5 "=="
 | class_instance uint64 :: equal \<rightharpoonup>
   (Haskell) -
 | constant "less_eq :: uint64 \<Rightarrow> _ \<Rightarrow> bool" \<rightharpoonup>
   (SML) "Uint64.less'_eq" and
   (Haskell) infix 4 "<=" and
   (OCaml) "Uint64.less'_eq" and
   (Scala) "Uint64.less'_eq"
 | constant "less :: uint64 \<Rightarrow> _ \<Rightarrow> bool" \<rightharpoonup>
   (SML) "Uint64.less" and
   (Haskell) infix 4 "<" and
   (OCaml) "Uint64.less" and
   (Scala) "Uint64.less"
-| constant "bitNOT :: uint64 \<Rightarrow> _" \<rightharpoonup>
+| constant "NOT :: uint64 \<Rightarrow> _" \<rightharpoonup>
   (SML) "Uint64.notb" and
   (Haskell) "Data'_Bits.complement" and
   (OCaml) "Int64.lognot" and
   (Scala) "_.unary'_~"
-| constant "bitAND :: uint64 \<Rightarrow> _" \<rightharpoonup>
+| constant "(AND) :: uint64 \<Rightarrow> _" \<rightharpoonup>
   (SML) "Uint64.andb" and
   (Haskell) infixl 7 "Data_Bits..&." and
   (OCaml) "Int64.logand" and
   (Scala) infixl 3 "&"
-| constant "bitOR :: uint64 \<Rightarrow> _" \<rightharpoonup>
+| constant "(OR) :: uint64 \<Rightarrow> _" \<rightharpoonup>
   (SML) "Uint64.orb" and
   (Haskell) infixl 5 "Data_Bits..|." and
   (OCaml) "Int64.logor" and
   (Scala) infixl 1 "|"
-| constant "bitXOR :: uint64 \<Rightarrow> _" \<rightharpoonup>
+| constant "(XOR) :: uint64 \<Rightarrow> _" \<rightharpoonup>
   (SML) "Uint64.xorb" and
   (Haskell) "Data'_Bits.xor" and
   (OCaml) "Int64.logxor" and
   (Scala) infixl 2 "^"
 
 definition uint64_divmod :: "uint64 \<Rightarrow> uint64 \<Rightarrow> uint64 \<times> uint64" where
   "uint64_divmod x y = 
   (if y = 0 then (undefined ((div) :: uint64 \<Rightarrow> _) x (0 :: uint64), undefined ((mod) :: uint64 \<Rightarrow> _) x (0 :: uint64)) 
   else (x div y, x mod y))"
 
 definition uint64_div :: "uint64 \<Rightarrow> uint64 \<Rightarrow> uint64" 
 where "uint64_div x y = fst (uint64_divmod x y)"
 
 definition uint64_mod :: "uint64 \<Rightarrow> uint64 \<Rightarrow> uint64" 
 where "uint64_mod x y = snd (uint64_divmod x y)"
 
 lemma div_uint64_code [code]: "x div y = (if y = 0 then 0 else uint64_div x y)"
 including undefined_transfer unfolding uint64_divmod_def uint64_div_def
 by transfer (simp add: word_div_def)
 
 lemma mod_uint64_code [code]: "x mod y = (if y = 0 then x else uint64_mod x y)"
 including undefined_transfer unfolding uint64_mod_def uint64_divmod_def
 by transfer (simp add: word_mod_def)
 
 definition uint64_sdiv :: "uint64 \<Rightarrow> uint64 \<Rightarrow> uint64"
 where [code del]:
   "uint64_sdiv x y =
    (if y = 0 then undefined ((div) :: uint64 \<Rightarrow> _) x (0 :: uint64)
     else Abs_uint64 (Rep_uint64 x sdiv Rep_uint64 y))"
 
 definition div0_uint64 :: "uint64 \<Rightarrow> uint64"
 where [code del]: "div0_uint64 x = undefined ((div) :: uint64 \<Rightarrow> _) x (0 :: uint64)"
 declare [[code abort: div0_uint64]]
 
 definition mod0_uint64 :: "uint64 \<Rightarrow> uint64"
 where [code del]: "mod0_uint64 x = undefined ((mod) :: uint64 \<Rightarrow> _) x (0 :: uint64)"
 declare [[code abort: mod0_uint64]]
 
 lemma uint64_divmod_code [code]:
   "uint64_divmod x y =
   (if 0x8000000000000000 \<le> y then if x < y then (0, x) else (1, x - y)
    else if y = 0 then (div0_uint64 x, mod0_uint64 x)
    else let q = (uint64_sdiv (x >> 1) y) << 1;
             r = x - q * y
         in if r \<ge> y then (q + 1, r - y) else (q, r))"
 including undefined_transfer unfolding uint64_divmod_def uint64_sdiv_def div0_uint64_def mod0_uint64_def
 by transfer(simp add: divmod_via_sdivmod)
 
 lemma uint64_sdiv_code [code abstract]:
   "Rep_uint64 (uint64_sdiv x y) =
    (if y = 0 then Rep_uint64 (undefined ((div) :: uint64 \<Rightarrow> _) x (0 :: uint64))
     else Rep_uint64 x sdiv Rep_uint64 y)"
 unfolding uint64_sdiv_def by(simp add: Abs_uint64_inverse)
 
 text \<open>
   Note that we only need a translation for signed division, but not for the remainder
   because @{thm uint64_divmod_code} computes both with division only.
 \<close>
 
 code_printing
   constant uint64_div \<rightharpoonup>
   (SML) "Uint64.divide" and
   (Haskell) "Prelude.div"
 | constant uint64_mod \<rightharpoonup>
   (SML) "Uint64.modulus" and
   (Haskell) "Prelude.mod"
 | constant uint64_divmod \<rightharpoonup>
   (Haskell) "divmod"
 | constant uint64_sdiv \<rightharpoonup>
   (OCaml) "Int64.div" and
   (Scala) "_ '/ _"
 
 definition uint64_test_bit :: "uint64 \<Rightarrow> integer \<Rightarrow> bool"
 where [code del]:
   "uint64_test_bit x n =
   (if n < 0 \<or> 63 < n then undefined (test_bit :: uint64 \<Rightarrow> _) x n
    else x !! (nat_of_integer n))"
 
 lemma test_bit_uint64_code [code]:
   "test_bit x n \<longleftrightarrow> n < 64 \<and> uint64_test_bit x (integer_of_nat n)"
 including undefined_transfer integer.lifting unfolding uint64_test_bit_def
 by transfer(auto cong: conj_cong dest: test_bit_size simp add: word_size)
 
 lemma uint64_test_bit_code [code]:
   "uint64_test_bit w n =
   (if n < 0 \<or> 63 < n then undefined (test_bit :: uint64 \<Rightarrow> _) w n else Rep_uint64 w !! nat_of_integer n)"
 unfolding uint64_test_bit_def
 by(simp add: test_bit_uint64.rep_eq)
 
 code_printing constant uint64_test_bit \<rightharpoonup>
   (SML) "Uint64.test'_bit" and
   (Haskell) "Data'_Bits.testBitBounded" and
   (OCaml) "Uint64.test'_bit" and
   (Scala) "Uint64.test'_bit" and
   (Eval) "(fn x => fn i => if i < 0 orelse i >= 64 then raise (Fail \"argument to uint64'_test'_bit out of bounds\") else Uint64.test'_bit x i)"
 
 definition uint64_set_bit :: "uint64 \<Rightarrow> integer \<Rightarrow> bool \<Rightarrow> uint64"
 where [code del]:
   "uint64_set_bit x n b =
   (if n < 0 \<or> 63 < n then undefined (set_bit :: uint64 \<Rightarrow> _) x n b
    else set_bit x (nat_of_integer n) b)"
 
 lemma set_bit_uint64_code [code]:
   "set_bit x n b = (if n < 64 then uint64_set_bit x (integer_of_nat n) b else x)"
 including undefined_transfer integer.lifting unfolding uint64_set_bit_def
 by(transfer)(auto cong: conj_cong simp add: not_less set_bit_beyond word_size)
 
 lemma uint64_set_bit_code [code abstract]:
   "Rep_uint64 (uint64_set_bit w n b) = 
   (if n < 0 \<or> 63 < n then Rep_uint64 (undefined (set_bit :: uint64 \<Rightarrow> _) w n b)
    else set_bit (Rep_uint64 w) (nat_of_integer n) b)"
 including undefined_transfer unfolding uint64_set_bit_def by transfer simp
 
 code_printing constant uint64_set_bit \<rightharpoonup>
   (SML) "Uint64.set'_bit" and
   (Haskell) "Data'_Bits.setBitBounded" and
   (OCaml) "Uint64.set'_bit" and
   (Scala) "Uint64.set'_bit" and
   (Eval) "(fn x => fn i => fn b => if i < 0 orelse i >= 64 then raise (Fail \"argument to uint64'_set'_bit out of bounds\") else Uint64.set'_bit x i b)"
 
 lift_definition uint64_set_bits :: "(nat \<Rightarrow> bool) \<Rightarrow> uint64 \<Rightarrow> nat \<Rightarrow> uint64" is set_bits_aux .
 
 lemma uint64_set_bits_code [code]:
   "uint64_set_bits f w n =
   (if n = 0 then w 
    else let n' = n - 1 in uint64_set_bits f ((w << 1) OR (if f n' then 1 else 0)) n')"
 by(transfer fixing: n)(cases n, simp_all)
 
 lemma set_bits_uint64 [code]:
   "(BITS n. f n) = uint64_set_bits f 0 64"
 by transfer(simp add: set_bits_conv_set_bits_aux)
 
 
 lemma lsb_code [code]: fixes x :: uint64 shows "lsb x = x !! 0"
 by transfer(simp add: word_lsb_def word_test_bit_def)
 
 
 definition uint64_shiftl :: "uint64 \<Rightarrow> integer \<Rightarrow> uint64"
 where [code del]:
   "uint64_shiftl x n = (if n < 0 \<or> 64 \<le> n then undefined (shiftl :: uint64 \<Rightarrow> _) x n else x << (nat_of_integer n))"
 
 lemma shiftl_uint64_code [code]: "x << n = (if n < 64 then uint64_shiftl x (integer_of_nat n) else 0)"
 including undefined_transfer integer.lifting unfolding uint64_shiftl_def
 by transfer(simp add: not_less shiftl_zero_size word_size)
 
 lemma uint64_shiftl_code [code abstract]:
   "Rep_uint64 (uint64_shiftl w n) =
   (if n < 0 \<or> 64 \<le> n then Rep_uint64 (undefined (shiftl :: uint64 \<Rightarrow> _) w n) else Rep_uint64 w << (nat_of_integer n))"
 including undefined_transfer unfolding uint64_shiftl_def by transfer simp
 
 code_printing constant uint64_shiftl \<rightharpoonup>
   (SML) "Uint64.shiftl" and
   (Haskell) "Data'_Bits.shiftlBounded" and
   (OCaml) "Uint64.shiftl" and
   (Scala) "Uint64.shiftl" and
   (Eval) "(fn x => fn i => if i < 0 orelse i >= 64 then raise (Fail \"argument to uint64'_shiftl out of bounds\") else Uint64.shiftl x i)"
 
 
 definition uint64_shiftr :: "uint64 \<Rightarrow> integer \<Rightarrow> uint64"
 where [code del]:
   "uint64_shiftr x n = (if n < 0 \<or> 64 \<le> n then undefined (shiftr :: uint64 \<Rightarrow> _) x n else x >> (nat_of_integer n))"
 
 lemma shiftr_uint64_code [code]: "x >> n = (if n < 64 then uint64_shiftr x (integer_of_nat n) else 0)"
 including undefined_transfer integer.lifting unfolding uint64_shiftr_def
 by transfer(simp add: not_less shiftr_zero_size word_size)
 
 lemma uint64_shiftr_code [code abstract]:
   "Rep_uint64 (uint64_shiftr w n) =
   (if n < 0 \<or> 64 \<le> n then Rep_uint64 (undefined (shiftr :: uint64 \<Rightarrow> _) w n) else Rep_uint64 w >> nat_of_integer n)"
 including undefined_transfer unfolding uint64_shiftr_def by transfer simp
 
 code_printing constant uint64_shiftr \<rightharpoonup>
   (SML) "Uint64.shiftr" and
   (Haskell) "Data'_Bits.shiftrBounded" and
   (OCaml) "Uint64.shiftr" and
   (Scala) "Uint64.shiftr" and
   (Eval) "(fn x => fn i => if i < 0 orelse i >= 64 then raise (Fail \"argument to uint64'_shiftr out of bounds\") else Uint64.shiftr x i)"
 
 
 definition uint64_sshiftr :: "uint64 \<Rightarrow> integer \<Rightarrow> uint64"
 where [code del]:
   "uint64_sshiftr x n =
   (if n < 0 \<or> 64 \<le> n then undefined sshiftr_uint64 x n else sshiftr_uint64 x (nat_of_integer n))"
 
 lemma sshiftr_beyond: fixes x :: "'a :: len word" shows
   "size x \<le> n \<Longrightarrow> x >>> n = (if x !! (size x - 1) then -1 else 0)"
 by(rule word_eqI)(simp add: nth_sshiftr word_size)
 
 lemma sshiftr_uint64_code [code]:
   "x >>> n = 
   (if n < 64 then uint64_sshiftr x (integer_of_nat n) else if x !! 63 then -1 else 0)"
 including undefined_transfer integer.lifting unfolding uint64_sshiftr_def
 by transfer(simp add: not_less sshiftr_beyond word_size)
 
 lemma uint64_sshiftr_code [code abstract]:
   "Rep_uint64 (uint64_sshiftr w n) =
   (if n < 0 \<or> 64 \<le> n then Rep_uint64 (undefined sshiftr_uint64 w n) else Rep_uint64 w >>> (nat_of_integer n))"
 including undefined_transfer unfolding uint64_sshiftr_def by transfer simp
 
 code_printing constant uint64_sshiftr \<rightharpoonup>
   (SML) "Uint64.shiftr'_signed" and
   (Haskell) 
     "(Prelude.fromInteger (Prelude.toInteger (Data'_Bits.shiftrBounded (Prelude.fromInteger (Prelude.toInteger _) :: Uint64.Int64) _)) :: Uint64.Word64)" and
   (OCaml) "Uint64.shiftr'_signed" and
   (Scala) "Uint64.shiftr'_signed" and
   (Eval) "(fn x => fn i => if i < 0 orelse i >= 64 then raise (Fail \"argument to uint64'_shiftr'_signed out of bounds\") else Uint64.shiftr'_signed x i)"
 
 
 lemma uint64_msb_test_bit: "msb x \<longleftrightarrow> (x :: uint64) !! 63"
 by transfer(simp add: msb_nth)
 
 lemma msb_uint64_code [code]: "msb x \<longleftrightarrow> uint64_test_bit x 63"
 by(simp add: uint64_test_bit_def uint64_msb_test_bit)
 
 lemma uint64_of_int_code [code]: "uint64_of_int i = Uint64 (integer_of_int i)"
 including integer.lifting by transfer simp
 
 lemma int_of_uint64_code [code]:
   "int_of_uint64 x = int_of_integer (integer_of_uint64 x)"
 by(simp add: integer_of_uint64_def)
 
 lemma nat_of_uint64_code [code]:
   "nat_of_uint64 x = nat_of_integer (integer_of_uint64 x)"
 unfolding integer_of_uint64_def including integer.lifting by transfer (simp add: unat_def)
 
 definition integer_of_uint64_signed :: "uint64 \<Rightarrow> integer"
 where
   "integer_of_uint64_signed n = (if n !! 63 then undefined integer_of_uint64 n else integer_of_uint64 n)"
 
 lemma integer_of_uint64_signed_code [code]:
   "integer_of_uint64_signed n =
   (if n !! 63 then undefined integer_of_uint64 n else integer_of_int (uint (Rep_uint64' n)))"
 unfolding integer_of_uint64_signed_def integer_of_uint64_def
 including undefined_transfer by transfer simp
 
 lemma integer_of_uint64_code [code]:
   "integer_of_uint64 n =
   (if n !! 63 then integer_of_uint64_signed (n AND 0x7FFFFFFFFFFFFFFF) OR 0x8000000000000000 else integer_of_uint64_signed n)"
 unfolding integer_of_uint64_def integer_of_uint64_signed_def o_def
 including undefined_transfer integer.lifting
 by transfer(auto simp add: word_ao_nth uint_and_mask_or_full mask_numeral mask_Suc_0 intro!: uint_and_mask_or_full[symmetric])
 
 code_printing
   constant "integer_of_uint64" \<rightharpoonup>
   (SML) "Uint64.toInt" and
   (Haskell) "Prelude.toInteger"
 | constant "integer_of_uint64_signed" \<rightharpoonup>
   (OCaml) "Z.of'_int64" and
   (Scala) "BigInt"
 
 section \<open>Quickcheck setup\<close>
 
 definition uint64_of_natural :: "natural \<Rightarrow> uint64"
 where "uint64_of_natural x \<equiv> Uint64 (integer_of_natural x)"
 
 instantiation uint64 :: "{random, exhaustive, full_exhaustive}" begin
 definition "random_uint64 \<equiv> qc_random_cnv uint64_of_natural"
 definition "exhaustive_uint64 \<equiv> qc_exhaustive_cnv uint64_of_natural"
 definition "full_exhaustive_uint64 \<equiv> qc_full_exhaustive_cnv uint64_of_natural"
 instance ..
 end
 
 instantiation uint64 :: narrowing begin
 
 interpretation quickcheck_narrowing_samples
   "\<lambda>i. let x = Uint64 i in (x, 0xFFFFFFFFFFFFFFFF - x)" "0"
   "Typerep.Typerep (STR ''Uint64.uint64'') []" .
 
 definition "narrowing_uint64 d = qc_narrowing_drawn_from (narrowing_samples d) d"
 declare [[code drop: "partial_term_of :: uint64 itself \<Rightarrow> _"]]
 lemmas partial_term_of_uint64 [code] = partial_term_of_code
 
 instance ..
 end
 
 no_notation sshiftr_uint64 (infixl ">>>" 55)
 
 end
diff --git a/thys/Native_Word/Uint8.thy b/thys/Native_Word/Uint8.thy
--- a/thys/Native_Word/Uint8.thy
+++ b/thys/Native_Word/Uint8.thy
@@ -1,579 +1,579 @@
 (*  Title:      Uint8.thy
     Author:     Andreas Lochbihler, ETH Zurich
 *)
 
 chapter \<open>Unsigned words of 8 bits\<close>
 
 theory Uint8 imports
   Code_Target_Word_Base
 begin
 
 text \<open>
   Restriction for OCaml code generation:
   OCaml does not provide an int8 type, so no special code generation 
   for this type is set up. If the theory \<open>Code_Target_Bits_Int\<close>
   is imported, the type \<open>uint8\<close> is emulated via @{typ "8 word"}.
 \<close>
 
 declare prod.Quotient[transfer_rule]
 
 section \<open>Type definition and primitive operations\<close>
 
 typedef uint8 = "UNIV :: 8 word set" ..
 
 setup_lifting type_definition_uint8
 
 text \<open>Use an abstract type for code generation to disable pattern matching on @{term Abs_uint8}.\<close>
 declare Rep_uint8_inverse[code abstype]
 
 declare Quotient_uint8[transfer_rule]
 
 instantiation uint8 :: "{neg_numeral, modulo, comm_monoid_mult, comm_ring}" begin
 lift_definition zero_uint8 :: uint8 is "0" .
 lift_definition one_uint8 :: uint8 is "1" .
 lift_definition plus_uint8 :: "uint8 \<Rightarrow> uint8 \<Rightarrow> uint8" is "(+)" .
 lift_definition minus_uint8 :: "uint8 \<Rightarrow> uint8 \<Rightarrow> uint8" is "(-)" .
 lift_definition uminus_uint8 :: "uint8 \<Rightarrow> uint8" is uminus .
 lift_definition times_uint8 :: "uint8 \<Rightarrow> uint8 \<Rightarrow> uint8" is "(*)" .
 lift_definition divide_uint8 :: "uint8 \<Rightarrow> uint8 \<Rightarrow> uint8" is "(div)" .
 lift_definition modulo_uint8 :: "uint8 \<Rightarrow> uint8 \<Rightarrow> uint8" is "(mod)" .
 instance by standard (transfer, simp add: algebra_simps)+
 end
 
 instantiation uint8 :: linorder begin
 lift_definition less_uint8 :: "uint8 \<Rightarrow> uint8 \<Rightarrow> bool" is "(<)" .
 lift_definition less_eq_uint8 :: "uint8 \<Rightarrow> uint8 \<Rightarrow> bool" is "(\<le>)" .
 instance by standard (transfer, simp add: less_le_not_le linear)+
 end
 
 lemmas [code] = less_uint8.rep_eq less_eq_uint8.rep_eq
 
 instantiation uint8 :: bit_operations begin
-lift_definition bitNOT_uint8 :: "uint8 \<Rightarrow> uint8" is bitNOT .
-lift_definition bitAND_uint8 :: "uint8 \<Rightarrow> uint8 \<Rightarrow> uint8" is bitAND .
-lift_definition bitOR_uint8 :: "uint8 \<Rightarrow> uint8 \<Rightarrow> uint8" is bitOR .
-lift_definition bitXOR_uint8 :: "uint8 \<Rightarrow> uint8 \<Rightarrow> uint8" is bitXOR .
+lift_definition bitNOT_uint8 :: "uint8 \<Rightarrow> uint8" is NOT .
+lift_definition bitAND_uint8 :: "uint8 \<Rightarrow> uint8 \<Rightarrow> uint8" is \<open>(AND)\<close> .
+lift_definition bitOR_uint8 :: "uint8 \<Rightarrow> uint8 \<Rightarrow> uint8" is \<open>(OR)\<close> .
+lift_definition bitXOR_uint8 :: "uint8 \<Rightarrow> uint8 \<Rightarrow> uint8" is \<open>(XOR)\<close> .
 lift_definition test_bit_uint8 :: "uint8 \<Rightarrow> nat \<Rightarrow> bool" is test_bit .
 lift_definition set_bit_uint8 :: "uint8 \<Rightarrow> nat \<Rightarrow> bool \<Rightarrow> uint8" is set_bit .
 lift_definition lsb_uint8 :: "uint8 \<Rightarrow> bool" is lsb .
 lift_definition shiftl_uint8 :: "uint8 \<Rightarrow> nat \<Rightarrow> uint8" is shiftl .
 lift_definition shiftr_uint8 :: "uint8 \<Rightarrow> nat \<Rightarrow> uint8" is shiftr .
 lift_definition msb_uint8 :: "uint8 \<Rightarrow> bool" is msb .
 instance ..
 end
 
 instantiation uint8 :: bit_comprehension begin
 lift_definition set_bits_uint8 :: "(nat \<Rightarrow> bool) \<Rightarrow> uint8" is "set_bits" .
 instance ..
 end
 
 lemmas [code] = test_bit_uint8.rep_eq lsb_uint8.rep_eq msb_uint8.rep_eq
 
 instantiation uint8 :: equal begin
 lift_definition equal_uint8 :: "uint8 \<Rightarrow> uint8 \<Rightarrow> bool" is "equal_class.equal" .
 instance by standard (transfer, simp add: equal_eq)
 end
 
 lemmas [code] = equal_uint8.rep_eq
 
 instantiation uint8 :: size begin
 lift_definition size_uint8 :: "uint8 \<Rightarrow> nat" is "size" .
 instance ..
 end
 
 lemmas [code] = size_uint8.rep_eq
 
 lift_definition sshiftr_uint8 :: "uint8 \<Rightarrow> nat \<Rightarrow> uint8" (infixl ">>>" 55) is sshiftr .
 
 lift_definition uint8_of_int :: "int \<Rightarrow> uint8" is "word_of_int" .
 
 definition uint8_of_nat :: "nat \<Rightarrow> uint8"
 where "uint8_of_nat = uint8_of_int \<circ> int"
 
 lift_definition int_of_uint8 :: "uint8 \<Rightarrow> int" is "uint" .
 lift_definition nat_of_uint8 :: "uint8 \<Rightarrow> nat" is "unat" .
 
 definition integer_of_uint8 :: "uint8 \<Rightarrow> integer"
 where "integer_of_uint8 = integer_of_int o int_of_uint8"
 
 text \<open>Use pretty numerals from integer for pretty printing\<close>
 
 context includes integer.lifting begin
 
 lift_definition Uint8 :: "integer \<Rightarrow> uint8" is "word_of_int" .
 
 lemma Rep_uint8_numeral [simp]: "Rep_uint8 (numeral n) = numeral n"
 by(induction n)(simp_all add: one_uint8_def Abs_uint8_inverse numeral.simps plus_uint8_def)
 
 lemma numeral_uint8_transfer [transfer_rule]:
   "(rel_fun (=) cr_uint8) numeral numeral"
 by(auto simp add: cr_uint8_def)
 
 lemma numeral_uint8 [code_unfold]: "numeral n = Uint8 (numeral n)"
 by transfer simp
 
 lemma Rep_uint8_neg_numeral [simp]: "Rep_uint8 (- numeral n) = - numeral n"
 by(simp only: uminus_uint8_def)(simp add: Abs_uint8_inverse)
 
 lemma neg_numeral_uint8 [code_unfold]: "- numeral n = Uint8 (- numeral n)"
 by transfer(simp add: cr_uint8_def)
 
 end
 
 lemma Abs_uint8_numeral [code_post]: "Abs_uint8 (numeral n) = numeral n"
 by(induction n)(simp_all add: one_uint8_def numeral.simps plus_uint8_def Abs_uint8_inverse)
 
 lemma Abs_uint8_0 [code_post]: "Abs_uint8 0 = 0"
 by(simp add: zero_uint8_def)
 
 lemma Abs_uint8_1 [code_post]: "Abs_uint8 1 = 1"
 by(simp add: one_uint8_def)
 
 section \<open>Code setup\<close>
 
 code_printing code_module Uint8 \<rightharpoonup> (SML)
 \<open>(* Test that words can handle numbers between 0 and 3 *)
 val _ = if 3 <= Word.wordSize then () else raise (Fail ("wordSize less than 3"));
 
 structure Uint8 : sig
   val set_bit : Word8.word -> IntInf.int -> bool -> Word8.word
   val shiftl : Word8.word -> IntInf.int -> Word8.word
   val shiftr : Word8.word -> IntInf.int -> Word8.word
   val shiftr_signed : Word8.word -> IntInf.int -> Word8.word
   val test_bit : Word8.word -> IntInf.int -> bool
 end = struct
 
 fun set_bit x n b =
   let val mask = Word8.<< (0wx1, Word.fromLargeInt (IntInf.toLarge n))
   in if b then Word8.orb (x, mask)
      else Word8.andb (x, Word8.notb mask)
   end
 
 fun shiftl x n =
   Word8.<< (x, Word.fromLargeInt (IntInf.toLarge n))
 
 fun shiftr x n =
   Word8.>> (x, Word.fromLargeInt (IntInf.toLarge n))
 
 fun shiftr_signed x n =
   Word8.~>> (x, Word.fromLargeInt (IntInf.toLarge n))
 
 fun test_bit x n =
   Word8.andb (x, Word8.<< (0wx1, Word.fromLargeInt (IntInf.toLarge n))) <> Word8.fromInt 0
 
 end; (* struct Uint8 *)\<close>
 code_reserved SML Uint8
 
 code_printing code_module Uint8 \<rightharpoonup> (Haskell)
  \<open>module Uint8(Int8, Word8) where
 
   import Data.Int(Int8)
   import Data.Word(Word8)\<close>
 code_reserved Haskell Uint8
 
 text \<open>
   Scala provides only signed 8bit numbers, so we use these and 
   implement sign-sensitive operations like comparisons manually.
 \<close>
 
 code_printing code_module Uint8 \<rightharpoonup> (Scala)
 \<open>object Uint8 {
 
 def less(x: Byte, y: Byte) : Boolean =
   if (x < 0) y < 0 && x < y
   else y < 0 || x < y
 
 def less_eq(x: Byte, y: Byte) : Boolean =
   if (x < 0) y < 0 && x <= y
   else y < 0 || x <= y
 
 def set_bit(x: Byte, n: BigInt, b: Boolean) : Byte =
   if (b)
     (x | (1 << n.intValue)).toByte
   else
     (x & (1 << n.intValue).unary_~).toByte
 
 def shiftl(x: Byte, n: BigInt) : Byte = (x << n.intValue).toByte
 
 def shiftr(x: Byte, n: BigInt) : Byte = ((x & 255) >>> n.intValue).toByte
 
 def shiftr_signed(x: Byte, n: BigInt) : Byte = (x >> n.intValue).toByte
 
 def test_bit(x: Byte, n: BigInt) : Boolean =
   (x & (1 << n.intValue)) != 0
 
 } /* object Uint8 */\<close>
 code_reserved Scala Uint8
 
 text \<open>
   Avoid @{term Abs_uint8} in generated code, use @{term Rep_uint8'} instead. 
   The symbolic implementations for code\_simp use @{term Rep_uint8}.
 
   The new destructor @{term Rep_uint8'} is executable.
   As the simplifier is given the [code abstract] equations literally, 
   we cannot implement @{term Rep_uint8} directly, because that makes code\_simp loop.
 
   If code generation raises Match, some equation probably contains @{term Rep_uint8} 
   ([code abstract] equations for @{typ uint8} may use @{term Rep_uint8} because
   these instances will be folded away.)
 
   To convert @{typ "8 word"} values into @{typ uint8}, use @{term "Abs_uint8'"}.
 \<close>
 
 definition Rep_uint8' where [simp]: "Rep_uint8' = Rep_uint8"
 
 lemma Rep_uint8'_transfer [transfer_rule]:
   "rel_fun cr_uint8 (=) (\<lambda>x. x) Rep_uint8'"
 unfolding Rep_uint8'_def by(rule uint8.rep_transfer)
 
 lemma Rep_uint8'_code [code]: "Rep_uint8' x = (BITS n. x !! n)"
 by transfer simp
 
 lift_definition Abs_uint8' :: "8 word \<Rightarrow> uint8" is "\<lambda>x :: 8 word. x" .
 
 lemma Abs_uint8'_code [code]: "Abs_uint8' x = Uint8 (integer_of_int (uint x))"
 including integer.lifting by transfer simp
 
 declare [[code drop: "term_of_class.term_of :: uint8 \<Rightarrow> _"]]
 
 lemma term_of_uint8_code [code]:
   defines "TR \<equiv> typerep.Typerep" and "bit0 \<equiv> STR ''Numeral_Type.bit0''" shows
   "term_of_class.term_of x = 
    Code_Evaluation.App (Code_Evaluation.Const (STR ''Uint8.uint8.Abs_uint8'') (TR (STR ''fun'') [TR (STR ''Word.word'') [TR bit0 [TR bit0 [TR bit0 [TR (STR ''Numeral_Type.num1'') []]]]], TR (STR ''Uint8.uint8'') []]))
        (term_of_class.term_of (Rep_uint8' x))"
 by(simp add: term_of_anything)
 
 lemma Uin8_code [code abstract]: "Rep_uint8 (Uint8 i) = word_of_int (int_of_integer_symbolic i)"
 unfolding Uint8_def int_of_integer_symbolic_def by(simp add: Abs_uint8_inverse)
 
 code_printing type_constructor uint8 \<rightharpoonup>
   (SML) "Word8.word" and
   (Haskell) "Uint8.Word8" and
   (Scala) "Byte"
 | constant Uint8 \<rightharpoonup> 
   (SML) "Word8.fromLargeInt (IntInf.toLarge _)" and
   (Haskell) "(Prelude.fromInteger _ :: Uint8.Word8)" and
   (Haskell_Quickcheck) "(Prelude.fromInteger (Prelude.toInteger _) :: Uint8.Word8)" and
   (Scala) "_.byteValue"
 | constant "0 :: uint8" \<rightharpoonup>
   (SML) "(Word8.fromInt 0)" and
   (Haskell) "(0 :: Uint8.Word8)" and
   (Scala) "0.toByte"
 | constant "1 :: uint8" \<rightharpoonup>
   (SML) "(Word8.fromInt 1)" and
   (Haskell) "(1 :: Uint8.Word8)" and
   (Scala) "1.toByte"
 | constant "plus :: uint8 \<Rightarrow> _ \<Rightarrow> _" \<rightharpoonup>
   (SML) "Word8.+ ((_), (_))" and
   (Haskell) infixl 6 "+" and
   (Scala) "(_ +/ _).toByte"
 | constant "uminus :: uint8 \<Rightarrow> _" \<rightharpoonup>
   (SML) "Word8.~" and
   (Haskell) "negate" and
   (Scala) "(- _).toByte"
 | constant "minus :: uint8 \<Rightarrow> _" \<rightharpoonup>
   (SML) "Word8.- ((_), (_))" and
   (Haskell) infixl 6 "-" and
   (Scala) "(_ -/ _).toByte"
 | constant "times :: uint8 \<Rightarrow> _ \<Rightarrow> _" \<rightharpoonup>
   (SML) "Word8.* ((_), (_))" and
   (Haskell) infixl 7 "*" and
   (Scala) "(_ */ _).toByte"
 | constant "HOL.equal :: uint8 \<Rightarrow> _ \<Rightarrow> bool" \<rightharpoonup>
   (SML) "!((_ : Word8.word) = _)" and
   (Haskell) infix 4 "==" and
   (Scala) infixl 5 "=="
 | class_instance uint8 :: equal \<rightharpoonup> (Haskell) -
 | constant "less_eq :: uint8 \<Rightarrow> _ \<Rightarrow> bool" \<rightharpoonup>
   (SML) "Word8.<= ((_), (_))" and
   (Haskell) infix 4 "<=" and
   (Scala) "Uint8.less'_eq"
 | constant "less :: uint8 \<Rightarrow> _ \<Rightarrow> bool" \<rightharpoonup>
   (SML) "Word8.< ((_), (_))" and
   (Haskell) infix 4 "<" and
   (Scala) "Uint8.less"
-| constant "bitNOT :: uint8 \<Rightarrow> _" \<rightharpoonup>
+| constant "NOT :: uint8 \<Rightarrow> _" \<rightharpoonup>
   (SML) "Word8.notb" and
   (Haskell) "Data'_Bits.complement" and
   (Scala) "_.unary'_~.toByte"
-| constant "bitAND :: uint8 \<Rightarrow> _" \<rightharpoonup>
+| constant "(AND) :: uint8 \<Rightarrow> _" \<rightharpoonup>
   (SML) "Word8.andb ((_),/ (_))" and
   (Haskell) infixl 7 "Data_Bits..&." and
   (Scala) "(_ & _).toByte"
-| constant "bitOR :: uint8 \<Rightarrow> _" \<rightharpoonup>
+| constant "(OR) :: uint8 \<Rightarrow> _" \<rightharpoonup>
   (SML) "Word8.orb ((_),/ (_))" and
   (Haskell) infixl 5 "Data_Bits..|." and
   (Scala) "(_ | _).toByte"
-| constant "bitXOR :: uint8 \<Rightarrow> _" \<rightharpoonup>
+| constant "(XOR) :: uint8 \<Rightarrow> _" \<rightharpoonup>
   (SML) "Word8.xorb ((_),/ (_))" and
   (Haskell) "Data'_Bits.xor" and
   (Scala) "(_ ^ _).toByte"
 
 definition uint8_divmod :: "uint8 \<Rightarrow> uint8 \<Rightarrow> uint8 \<times> uint8" where
   "uint8_divmod x y = 
   (if y = 0 then (undefined ((div) :: uint8 \<Rightarrow> _) x (0 :: uint8), undefined ((mod) :: uint8 \<Rightarrow> _) x (0 :: uint8)) 
   else (x div y, x mod y))"
 
 definition uint8_div :: "uint8 \<Rightarrow> uint8 \<Rightarrow> uint8" 
 where "uint8_div x y = fst (uint8_divmod x y)"
 
 definition uint8_mod :: "uint8 \<Rightarrow> uint8 \<Rightarrow> uint8" 
 where "uint8_mod x y = snd (uint8_divmod x y)"
 
 lemma div_uint8_code [code]: "x div y = (if y = 0 then 0 else uint8_div x y)"
 including undefined_transfer unfolding uint8_divmod_def uint8_div_def
 by transfer (simp add: word_div_def)
 
 lemma mod_uint8_code [code]: "x mod y = (if y = 0 then x else uint8_mod x y)"
 including undefined_transfer unfolding uint8_mod_def uint8_divmod_def
 by transfer (simp add: word_mod_def)
 
 definition uint8_sdiv :: "uint8 \<Rightarrow> uint8 \<Rightarrow> uint8"
 where
   "uint8_sdiv x y =
    (if y = 0 then undefined ((div) :: uint8 \<Rightarrow> _) x (0 :: uint8)
     else Abs_uint8 (Rep_uint8 x sdiv Rep_uint8 y))"
 
 definition div0_uint8 :: "uint8 \<Rightarrow> uint8"
 where [code del]: "div0_uint8 x = undefined ((div) :: uint8 \<Rightarrow> _) x (0 :: uint8)"
 declare [[code abort: div0_uint8]]
 
 definition mod0_uint8 :: "uint8 \<Rightarrow> uint8"
 where [code del]: "mod0_uint8 x = undefined ((mod) :: uint8 \<Rightarrow> _) x (0 :: uint8)"
 declare [[code abort: mod0_uint8]]
 
 lemma uint8_divmod_code [code]:
   "uint8_divmod x y =
   (if 0x80 \<le> y then if x < y then (0, x) else (1, x - y)
    else if y = 0 then (div0_uint8 x, mod0_uint8 x)
    else let q = (uint8_sdiv (x >> 1) y) << 1;
             r = x - q * y
         in if r \<ge> y then (q + 1, r - y) else (q, r))"
 including undefined_transfer unfolding uint8_divmod_def uint8_sdiv_def div0_uint8_def mod0_uint8_def
 by transfer(simp add: divmod_via_sdivmod)
 
 lemma uint8_sdiv_code [code abstract]:
   "Rep_uint8 (uint8_sdiv x y) =
    (if y = 0 then Rep_uint8 (undefined ((div) :: uint8 \<Rightarrow> _) x (0 :: uint8))
     else Rep_uint8 x sdiv Rep_uint8 y)"
 unfolding uint8_sdiv_def by(simp add: Abs_uint8_inverse)
 
 text \<open>
   Note that we only need a translation for signed division, but not for the remainder
   because @{thm uint8_divmod_code} computes both with division only.
 \<close>
 
 code_printing
   constant uint8_div \<rightharpoonup>
   (SML) "Word8.div ((_), (_))" and
   (Haskell) "Prelude.div"
 | constant uint8_mod \<rightharpoonup>
   (SML) "Word8.mod ((_), (_))" and
   (Haskell) "Prelude.mod"
 | constant uint8_divmod \<rightharpoonup>
   (Haskell) "divmod"
 | constant uint8_sdiv \<rightharpoonup>
   (Scala) "(_ '/ _).toByte"
 
 definition uint8_test_bit :: "uint8 \<Rightarrow> integer \<Rightarrow> bool"
 where [code del]:
   "uint8_test_bit x n =
   (if n < 0 \<or> 7 < n then undefined (test_bit :: uint8 \<Rightarrow> _) x n
    else x !! (nat_of_integer n))"
 
 lemma test_bit_uint8_code [code]:
   "test_bit x n \<longleftrightarrow> n < 8 \<and> uint8_test_bit x (integer_of_nat n)"
 including undefined_transfer integer.lifting unfolding uint8_test_bit_def
 by transfer(auto cong: conj_cong dest: test_bit_size simp add: word_size)
 
 lemma uint8_test_bit_code [code]:
   "uint8_test_bit w n =
   (if n < 0 \<or> 7 < n then undefined (test_bit :: uint8 \<Rightarrow> _) w n else Rep_uint8 w !! nat_of_integer n)"
 unfolding uint8_test_bit_def by(simp add: test_bit_uint8.rep_eq)
 
 code_printing constant uint8_test_bit \<rightharpoonup>
   (SML) "Uint8.test'_bit" and
   (Haskell) "Data'_Bits.testBitBounded" and
   (Scala) "Uint8.test'_bit" and
   (Eval) "(fn x => fn i => if i < 0 orelse i >= 8 then raise (Fail \"argument to uint8'_test'_bit out of bounds\") else Uint8.test'_bit x i)"
 
 
 definition uint8_set_bit :: "uint8 \<Rightarrow> integer \<Rightarrow> bool \<Rightarrow> uint8"
 where [code del]:
   "uint8_set_bit x n b =
   (if n < 0 \<or> 7 < n then undefined (set_bit :: uint8 \<Rightarrow> _) x n b
    else set_bit x (nat_of_integer n) b)"
 
 lemma set_bit_uint8_code [code]:
   "set_bit x n b = (if n < 8 then uint8_set_bit x (integer_of_nat n) b else x)"
 including undefined_transfer integer.lifting unfolding uint8_set_bit_def
 by(transfer)(auto cong: conj_cong simp add: not_less set_bit_beyond word_size)
 
 lemma uint8_set_bit_code [code abstract]:
   "Rep_uint8 (uint8_set_bit w n b) = 
   (if n < 0 \<or> 7 < n then Rep_uint8 (undefined (set_bit :: uint8 \<Rightarrow> _) w n b)
    else set_bit (Rep_uint8 w) (nat_of_integer n) b)"
 including undefined_transfer unfolding uint8_set_bit_def by transfer simp
 
 code_printing constant uint8_set_bit \<rightharpoonup>
   (SML) "Uint8.set'_bit" and
   (Haskell) "Data'_Bits.setBitBounded" and
   (Scala) "Uint8.set'_bit" and
   (Eval) "(fn x => fn i => fn b => if i < 0 orelse i >= 8 then raise (Fail \"argument to uint8'_set'_bit out of bounds\") else Uint8.set'_bit x i b)"
 
 
 lift_definition uint8_set_bits :: "(nat \<Rightarrow> bool) \<Rightarrow> uint8 \<Rightarrow> nat \<Rightarrow> uint8" is set_bits_aux .
 
 lemma uint8_set_bits_code [code]:
   "uint8_set_bits f w n =
   (if n = 0 then w 
    else let n' = n - 1 in uint8_set_bits f ((w << 1) OR (if f n' then 1 else 0)) n')"
 by(transfer fixing: n)(cases n, simp_all)
 
 lemma set_bits_uint8 [code]:
   "(BITS n. f n) = uint8_set_bits f 0 8"
 by transfer(simp add: set_bits_conv_set_bits_aux)
 
 
 lemma lsb_code [code]: fixes x :: uint8 shows "lsb x = x !! 0"
 by transfer(simp add: word_lsb_def word_test_bit_def)
 
 
 definition uint8_shiftl :: "uint8 \<Rightarrow> integer \<Rightarrow> uint8"
 where [code del]:
   "uint8_shiftl x n = (if n < 0 \<or> 8 \<le> n then undefined (shiftl :: uint8 \<Rightarrow> _) x n else x << (nat_of_integer n))"
 
 lemma shiftl_uint8_code [code]: "x << n = (if n < 8 then uint8_shiftl x (integer_of_nat n) else 0)"
 including undefined_transfer integer.lifting unfolding uint8_shiftl_def
 by transfer(simp add: not_less shiftl_zero_size word_size)
 
 lemma uint8_shiftl_code [code abstract]:
   "Rep_uint8 (uint8_shiftl w n) =
   (if n < 0 \<or> 8 \<le> n then Rep_uint8 (undefined (shiftl :: uint8 \<Rightarrow> _) w n)
    else Rep_uint8 w << nat_of_integer n)"
 including undefined_transfer unfolding uint8_shiftl_def by transfer simp
 
 code_printing constant uint8_shiftl \<rightharpoonup>
   (SML) "Uint8.shiftl" and
   (Haskell) "Data'_Bits.shiftlBounded" and
   (Scala) "Uint8.shiftl" and
   (Eval) "(fn x => fn i => if i < 0 orelse i >= 8 then raise (Fail \"argument to uint8'_shiftl out of bounds\") else Uint8.shiftl x i)"
 
 definition uint8_shiftr :: "uint8 \<Rightarrow> integer \<Rightarrow> uint8"
 where [code del]:
   "uint8_shiftr x n = (if n < 0 \<or> 8 \<le> n then undefined (shiftr :: uint8 \<Rightarrow> _) x n else x >> (nat_of_integer n))"
 
 lemma shiftr_uint8_code [code]: "x >> n = (if n < 8 then uint8_shiftr x (integer_of_nat n) else 0)"
 including undefined_transfer integer.lifting unfolding uint8_shiftr_def
 by transfer(simp add: not_less shiftr_zero_size word_size)
 
 lemma uint8_shiftr_code [code abstract]:
   "Rep_uint8 (uint8_shiftr w n) =
   (if n < 0 \<or> 8 \<le> n then Rep_uint8 (undefined (shiftr :: uint8 \<Rightarrow> _) w n) 
    else Rep_uint8 w >> nat_of_integer n)"
 including undefined_transfer unfolding uint8_shiftr_def by transfer simp
 
 code_printing constant uint8_shiftr \<rightharpoonup>
   (SML) "Uint8.shiftr" and
   (Haskell) "Data'_Bits.shiftrBounded" and
   (Scala) "Uint8.shiftr" and
   (Eval) "(fn x => fn i => if i < 0 orelse i >= 8 then raise (Fail \"argument to uint8'_shiftr out of bounds\") else Uint8.shiftr x i)"
 
 definition uint8_sshiftr :: "uint8 \<Rightarrow> integer \<Rightarrow> uint8"
 where [code del]:
   "uint8_sshiftr x n =
   (if n < 0 \<or> 8 \<le> n then undefined sshiftr_uint8 x n else sshiftr_uint8 x (nat_of_integer n))"
 
 lemma sshiftr_beyond: fixes x :: "'a :: len word" shows
   "size x \<le> n \<Longrightarrow> x >>> n = (if x !! (size x - 1) then -1 else 0)"
 by(rule word_eqI)(simp add: nth_sshiftr word_size)
 
 lemma sshiftr_uint8_code [code]:
   "x >>> n = 
   (if n < 8 then uint8_sshiftr x (integer_of_nat n) else if x !! 7 then -1 else 0)"
 including undefined_transfer integer.lifting unfolding uint8_sshiftr_def
 by transfer (simp add: not_less sshiftr_beyond word_size)
 
 lemma uint8_sshiftr_code [code abstract]:
   "Rep_uint8 (uint8_sshiftr w n) =
   (if n < 0 \<or> 8 \<le> n then Rep_uint8 (undefined sshiftr_uint8 w n)
    else Rep_uint8 w >>> nat_of_integer n)"
 including undefined_transfer unfolding uint8_sshiftr_def by transfer simp
 
 code_printing constant uint8_sshiftr \<rightharpoonup>
   (SML) "Uint8.shiftr'_signed" and
   (Haskell) 
     "(Prelude.fromInteger (Prelude.toInteger (Data'_Bits.shiftrBounded (Prelude.fromInteger (Prelude.toInteger _) :: Uint8.Int8) _)) :: Uint8.Word8)" and
   (Scala) "Uint8.shiftr'_signed" and
   (Eval) "(fn x => fn i => if i < 0 orelse i >= 8 then raise (Fail \"argument to uint8'_sshiftr out of bounds\") else Uint8.shiftr'_signed x i)"
 
 
 lemma uint8_msb_test_bit: "msb x \<longleftrightarrow> (x :: uint8) !! 7"
 by transfer(simp add: msb_nth)
 
 lemma msb_uint16_code [code]: "msb x \<longleftrightarrow> uint8_test_bit x 7"
 by(simp add: uint8_test_bit_def uint8_msb_test_bit)
 
 lemma uint8_of_int_code [code]: "uint8_of_int i = Uint8 (integer_of_int i)"
 including integer.lifting by transfer simp
 
 lemma int_of_uint8_code [code]:
   "int_of_uint8 x = int_of_integer (integer_of_uint8 x)"
 by(simp add: integer_of_uint8_def)
 
 lemma nat_of_uint8_code [code]:
   "nat_of_uint8 x = nat_of_integer (integer_of_uint8 x)"
 unfolding integer_of_uint8_def including integer.lifting by transfer (simp add: unat_def)
 
 definition integer_of_uint8_signed :: "uint8 \<Rightarrow> integer"
 where
   "integer_of_uint8_signed n = (if n !! 7 then undefined integer_of_uint8 n else integer_of_uint8 n)"
 
 lemma integer_of_uint8_signed_code [code]:
   "integer_of_uint8_signed n =
   (if n !! 7 then undefined integer_of_uint8 n else integer_of_int (uint (Rep_uint8' n)))"
 unfolding integer_of_uint8_signed_def integer_of_uint8_def
 including undefined_transfer by transfer simp
 
 lemma integer_of_uint8_code [code]:
   "integer_of_uint8 n =
   (if n !! 7 then integer_of_uint8_signed (n AND 0x7F) OR 0x80 else integer_of_uint8_signed n)"
 unfolding integer_of_uint8_def integer_of_uint8_signed_def o_def
 including undefined_transfer integer.lifting
 by transfer(auto simp add: word_ao_nth uint_and_mask_or_full mask_numeral mask_Suc_0 intro!: uint_and_mask_or_full[symmetric])
 
 code_printing
   constant "integer_of_uint8" \<rightharpoonup>
   (SML) "IntInf.fromLarge (Word8.toLargeInt _)" and
   (Haskell) "Prelude.toInteger"
 | constant "integer_of_uint8_signed" \<rightharpoonup>
   (Scala) "BigInt"
 
 section \<open>Quickcheck setup\<close>
 
 definition uint8_of_natural :: "natural \<Rightarrow> uint8"
 where "uint8_of_natural x \<equiv> Uint8 (integer_of_natural x)"
 
 instantiation uint8 :: "{random, exhaustive, full_exhaustive}" begin
 definition "random_uint8 \<equiv> qc_random_cnv uint8_of_natural"
 definition "exhaustive_uint8 \<equiv> qc_exhaustive_cnv uint8_of_natural"
 definition "full_exhaustive_uint8 \<equiv> qc_full_exhaustive_cnv uint8_of_natural"
 instance ..
 end
 
 instantiation uint8 :: narrowing begin
 
 interpretation quickcheck_narrowing_samples
   "\<lambda>i. let x = Uint8 i in (x, 0xFF - x)" "0"
   "Typerep.Typerep (STR ''Uint8.uint8'') []" .
 
 definition "narrowing_uint8 d = qc_narrowing_drawn_from (narrowing_samples d) d"
 declare [[code drop: "partial_term_of :: uint8 itself \<Rightarrow> _"]]
 lemmas partial_term_of_uint8 [code] = partial_term_of_code
 
 instance ..
 end
 
 no_notation sshiftr_uint8 (infixl ">>>" 55)
 
 end
diff --git a/thys/SPARCv8/SparcModel_MMU/MMU.thy b/thys/SPARCv8/SparcModel_MMU/MMU.thy
--- a/thys/SPARCv8/SparcModel_MMU/MMU.thy
+++ b/thys/SPARCv8/SparcModel_MMU/MMU.thy
@@ -1,312 +1,312 @@
 (*  Title:     Memory.thy
     Author:    David Sanán, Trinity College Dublin, 2012
                Zhe Hou, NTU, 2016.
 *)
 
 
 section \<open>Memory Management Unit (MMU)\<close>
 
 theory MMU
 imports Main RegistersOps Sparc_Types
 begin
 
 section \<open>MMU  Sizing\<close> 
 
 text\<open>
   We need some citation here for documentation about the MMU.
 \<close>
 text\<open>The MMU uses the Address Space Identifiers (ASI) to control memory access.
 ASI = 8, 10 are for user; ASI = 9, 11 are for supervisor.\<close>
 
 subsection "MMU Types"
 
 type_synonym word_PTE_flags = word8
 type_synonym word_length_PTE_flags = word_length8
 
 subsection "MMU length values"
 
 text\<open>Definitions for the length of the virtua address, page size,  
 virtual translation tables indexes, virtual address offset and Page protection flags\<close>
 
 
 definition length_entry_type :: "nat" 
 where "length_entry_type \<equiv> LENGTH(word_length_entry_type)" 
 definition length_phys_address:: "nat" 
 where "length_phys_address \<equiv> LENGTH(word_length_phys_address)"
 definition length_virtua_address:: "nat" 
 where "length_virtua_address \<equiv> LENGTH(word_length_virtua_address)"
 definition length_page:: "nat" where "length_page \<equiv> LENGTH(word_length_page)"
 definition length_t1:: "nat" where "length_t1 \<equiv> LENGTH(word_length_t1)"
 definition length_t2:: "nat" where "length_t2 \<equiv> LENGTH(word_length_t2)"
 definition length_t3:: "nat" where "length_t3 \<equiv> LENGTH(word_length_t3)"
 definition length_offset:: "nat" where "length_offset \<equiv> LENGTH(word_length_offset)"
 definition length_PTE_flags :: "nat" where 
 "length_PTE_flags \<equiv> LENGTH(word_length_PTE_flags)"
 
 subsection "MMU index values"
 
 definition va_t1_index :: "nat" where "va_t1_index \<equiv> length_virtua_address - length_t1"
 definition va_t2_index :: "nat" where "va_t2_index \<equiv> va_t1_index - length_t2"
 definition va_t3_index :: "nat" where "va_t3_index \<equiv> va_t2_index - length_t3"
 definition va_offset_index :: "nat" where "va_offset_index \<equiv> va_t3_index - length_offset"
 definition pa_page_index :: "nat" 
 where "pa_page_index \<equiv> length_phys_address - length_page"
 definition pa_offset_index :: "nat" where 
 "pa_offset_index \<equiv> pa_page_index -length_page"
 
 section \<open>MMU Definition\<close>
 
 record MMU_state =
    registers :: "MMU_context"
 (*   contexts:: context_table*)
 
 text \<open>The following functions access MMU registers via addresses. 
   See UT699LEON3FT manual page 35.\<close>
 
 definition mmu_reg_val:: "MMU_state \<Rightarrow> virtua_address \<Rightarrow> machine_word option"
 where "mmu_reg_val mmu_state addr \<equiv>
   if addr = 0x000 then \<comment> \<open>MMU control register\<close>
     Some ((registers mmu_state) CR)
   else if addr = 0x100 then \<comment> \<open>Context pointer register\<close>
     Some ((registers mmu_state) CTP)
   else if addr = 0x200 then \<comment> \<open>Context register\<close>
     Some ((registers mmu_state) CNR)
   else if addr = 0x300 then \<comment> \<open>Fault status register\<close>
     Some ((registers mmu_state) FTSR)
   else if addr = 0x400 then \<comment> \<open>Fault address register\<close>
     Some ((registers mmu_state) FAR)
   else None"
 
 definition mmu_reg_mod:: "MMU_state \<Rightarrow> virtua_address \<Rightarrow> machine_word \<Rightarrow>
   MMU_state option" where
 "mmu_reg_mod mmu_state addr w \<equiv>
   if addr = 0x000 then \<comment> \<open>MMU control register\<close>
     Some (mmu_state\<lparr>registers := (registers mmu_state)(CR := w)\<rparr>)
   else if addr = 0x100 then \<comment> \<open>Context pointer register\<close>
     Some (mmu_state\<lparr>registers := (registers mmu_state)(CTP := w)\<rparr>)
   else if addr = 0x200 then \<comment> \<open>Context register\<close>
     Some (mmu_state\<lparr>registers := (registers mmu_state)(CNR := w)\<rparr>)
   else if addr = 0x300 then \<comment> \<open>Fault status register\<close>
     Some (mmu_state\<lparr>registers := (registers mmu_state)(FTSR := w)\<rparr>)
   else if addr = 0x400 then \<comment> \<open>Fault address register\<close>
     Some (mmu_state\<lparr>registers := (registers mmu_state)(FAR := w)\<rparr>)
   else None"
 
 section \<open>Virtual Memory\<close>
 
 subsection \<open>MMU Auxiliary Definitions\<close>
 
 definition getCTPVal:: "MMU_state \<Rightarrow> machine_word"
 where "getCTPVal mmu \<equiv>  (registers mmu) CTP"
 
 definition getCNRVal::"MMU_state \<Rightarrow> machine_word"
 where "getCNRVal mmu \<equiv>  (registers mmu) CNR"
 
 
 text\<open>
  The physical context table address is got from the ConText Pointer register (CTP) and the 
 Context Register (CNR) MMU registers. 
  The CTP is shifted to align it with 
 the physical address (36 bits) and we add the table index given on CNR.
 CTP is right shifted 2 bits, cast to phys address and left shifted 6 bytes 
 to be aligned with the context register.  
 CNR is 2 bits left shifted for alignment with the context table.
 \<close>
 
 definition compose_context_table_addr :: "machine_word \<Rightarrow>machine_word 
                                           \<Rightarrow> phys_address"
 where 
  "compose_context_table_addr ctp cnr 
     \<equiv> ((ucast (ctp >> 2)) << 6) + (ucast cnr << 2)"
 
 subsection \<open>Virtual Address Translation\<close>
 
 text\<open>Get the context table phys address from the MMU registers\<close>
 definition get_context_table_addr :: "MMU_state \<Rightarrow> phys_address"
 where 
  "get_context_table_addr mmu 
      \<equiv> compose_context_table_addr (getCTPVal mmu) (getCNRVal mmu)"
 
 definition va_list_index :: "nat list" where
 "va_list_index \<equiv> [va_t1_index,va_t2_index,va_t3_index,0]"
 
 definition offset_index :: "nat list" where
 "offset_index 
   \<equiv> [ length_machine_word
     , length_machine_word-length_t1
     , length_machine_word-length_t1-length_t2
     , length_machine_word-length_t1-length_t2-length_t3
     ]"
 
 definition index_len_table :: "nat list" where "index_len_table \<equiv> [8,6,6,0]"
 
 definition n_context_tables :: "nat" where "n_context_tables \<equiv> 3"
 
 text \<open>The following are basic physical memory read functions. 
 At this level we don't need the write memory yet.\<close>
 
 definition mem_context_val:: "asi_type \<Rightarrow> phys_address \<Rightarrow> 
                       mem_context \<Rightarrow> mem_val_type option"
 where
 "mem_context_val asi add m \<equiv> 
   let asi8 = word_of_int 8;
       r1 = m asi add 
   in
   if r1 = None then
     m asi8 add
   else r1
 "
 
 text \<open>Given an ASI (word8), an address (word32) addr, 
         read the 32bit value from the memory addresses 
         starting from address addr' where addr' = addr 
         exception that the last two bits are 0's. 
         That is, read the data from 
         addr', addr'+1, addr'+2, addr'+3.\<close>
 definition mem_context_val_w32 :: "asi_type \<Rightarrow> phys_address \<Rightarrow> 
                            mem_context \<Rightarrow> word32 option"
 where
 "mem_context_val_w32 asi addr m \<equiv>
-  let addr' = bitAND addr 0b111111111111111111111111111111111100;
-      addr0 = bitOR addr' 0b000000000000000000000000000000000000;
-      addr1 = bitOR addr' 0b000000000000000000000000000000000001;
-      addr2 = bitOR addr' 0b000000000000000000000000000000000010;
-      addr3 = bitOR addr' 0b000000000000000000000000000000000011;
+  let addr' = (AND) addr 0b111111111111111111111111111111111100;
+      addr0 = (OR) addr' 0b000000000000000000000000000000000000;
+      addr1 = (OR) addr' 0b000000000000000000000000000000000001;
+      addr2 = (OR) addr' 0b000000000000000000000000000000000010;
+      addr3 = (OR) addr' 0b000000000000000000000000000000000011;
       r0 = mem_context_val asi addr0 m;
       r1 = mem_context_val asi addr1 m;
       r2 = mem_context_val asi addr2 m;
       r3 = mem_context_val asi addr3 m
   in
   if r0 = None \<or> r1 = None \<or> r2 = None \<or> r3 = None then
     None
   else
     let byte0 = case r0 of Some v \<Rightarrow> v;
         byte1 = case r1 of Some v \<Rightarrow> v;
         byte2 = case r2 of Some v \<Rightarrow> v;
         byte3 = case r3 of Some v \<Rightarrow> v 
     in
-    Some (bitOR (bitOR (bitOR ((ucast(byte0)) << 24) 
+    Some ((OR) ((OR) ((OR) ((ucast(byte0)) << 24) 
                               ((ucast(byte1)) << 16)) 
                        ((ucast(byte2)) << 8)) 
                 (ucast(byte3)))
 "
 
 text \<open>
   @{term "get_addr_from_table"} browses the page description tables  
   until it finds a PTE (bits==suc (suc 0).
 
   If it is a PTE it aligns the 24 most significant bits of the entry
   with the most significant bits of the phys address and or-ed with the offset,
    which will vary depending on the entry level. 
  In the case we are looking at the last table level (level 3),
    the offset is aligned to 0 otherwise it will be 2.
   
  If the table entry is a PTD (bits== Suc 0),
   the index is obtained from the virtual address depending on the current level and or-ed with the PTD. 
 \<close>
 
 function ptd_lookup:: "virtua_address \<Rightarrow> virtua_address \<Rightarrow>
 mem_context \<Rightarrow> nat \<Rightarrow> (phys_address \<times> PTE_flags) option" 
 where "ptd_lookup va pt m lvl = (
   if lvl > 3 then None
   else 
     let thislvl_offset = (
       if lvl = 1 then (ucast ((ucast (va >> 24))::word8))::word32
       else if lvl = 2 then (ucast ((ucast (va >> 18))::word6))::word32
       else (ucast ((ucast (va >> 12))::word6))::word32);
-        thislvl_addr = bitOR pt thislvl_offset;
+        thislvl_addr = (OR) pt thislvl_offset;
         thislvl_data = mem_context_val_w32 (word_of_int 9) (ucast thislvl_addr) m
     in
     case thislvl_data of 
     Some v \<Rightarrow> (
-      let et_val = bitAND v 0b00000000000000000000000000000011 in
+      let et_val = (AND) v 0b00000000000000000000000000000011 in
       if et_val = 0 then \<comment> \<open>Invalid\<close>
         None
       else if et_val = 1 then \<comment> \<open>Page Table Descriptor\<close>
-        let ptp = bitAND v 0b11111111111111111111111111111100 in
+        let ptp = (AND) v 0b11111111111111111111111111111100 in
         ptd_lookup va ptp m (lvl+1)
       else if et_val = 2 then \<comment> \<open>Page Table Entry\<close>
         let ppn = (ucast (v >> 8))::word24;
             va_offset = (ucast ((ucast va)::word12))::word36
         in
-        Some ((bitOR (((ucast ppn)::word36) << 12) va_offset), 
+        Some (((OR) (((ucast ppn)::word36) << 12) va_offset), 
               ((ucast v)::word8))
       else \<comment> \<open>\<open>et_val = 3\<close>, reserved.\<close>
         None
     )
     |None \<Rightarrow> None)
 "
 by pat_completeness auto
 termination  
 by (relation "measure (\<lambda> (va, (pt, (m, lvl))). 4 - lvl)") auto
 
 definition get_acc_flag:: "PTE_flags \<Rightarrow> word3" where
 "get_acc_flag w8 \<equiv> (ucast (w8 >> 2))::word3"
 
 definition mmu_readable:: "word3 \<Rightarrow> asi_type \<Rightarrow> bool" where
 "mmu_readable f asi \<equiv>
   if uint asi \<in> {8, 10} then
     if uint f \<in> {0,1,2,3,5} then True
     else False
   else if uint asi \<in> {9, 11} then
     if uint f \<in> {0,1,2,3,5,6,7} then True
     else False
   else False
 "
 
 definition mmu_writable:: "word3 \<Rightarrow> asi_type \<Rightarrow> bool" where
 "mmu_writable f asi \<equiv>
   if uint asi \<in> {8, 10} then
     if uint f \<in> {1,3} then True
     else False
   else if uint asi \<in> {9, 11} then
     if uint f \<in> {1,3,5,7} then True
     else False
   else False
 "
 
 definition virt_to_phys :: "virtua_address \<Rightarrow> MMU_state  \<Rightarrow> mem_context \<Rightarrow> 
                             (phys_address \<times> PTE_flags) option"
 where 
  "virt_to_phys va mmu m \<equiv> 
     let ctp_val = mmu_reg_val mmu (0x100);
         cnr_val = mmu_reg_val mmu (0x200);
         mmu_cr_val = (registers mmu) CR
     in
-    if bitAND mmu_cr_val 1 \<noteq> 0 then \<comment> \<open>MMU enabled.\<close>
+    if (AND) mmu_cr_val 1 \<noteq> 0 then \<comment> \<open>MMU enabled.\<close>
       case (ctp_val,cnr_val) of
       (Some v1, Some v2) \<Rightarrow>
-        let context_table_entry = bitOR ((v1 >> 11) << 11)
-            ((bitAND v2 0b00000000000000000000000111111111) << 2);
+        let context_table_entry = (OR) ((v1 >> 11) << 11)
+            (((AND) v2 0b00000000000000000000000111111111) << 2);
             context_table_data = mem_context_val_w32 (word_of_int 9) 
               (ucast context_table_entry) m
         in (
         case context_table_data of
         Some lvl1_page_table \<Rightarrow>
           ptd_lookup va lvl1_page_table m 1
         |None \<Rightarrow> None)
       |_ \<Rightarrow> None
     else Some ((ucast va), ((0b11101111)::word8)) 
 "
 
 text \<open>
 \newpage
 
 The below function gives the initial values of MMU registers.
 In particular, the MMU context register CR is 0 because:
 We don't know the bits for IMPL, VER, and SC;
 the bits for PSO are 0s because we use TSO;
 the reserved bits are 0s;
 we assume NF bits are 0s;
 and most importantly, the E bit is 0 because when the machine 
 starts up, MMU is disabled. 
 An initial boot procedure (bootloader or something like that) should 
 configure the MMU and then enable it if the OS uses MMU.\<close>
 
 definition MMU_registers_init :: "MMU_context"
 where "MMU_registers_init r \<equiv> 0" 
 
 definition mmu_setup :: "MMU_state"
 where "mmu_setup \<equiv> \<lparr>registers=MMU_registers_init\<rparr>"
 
 end
diff --git a/thys/SPARCv8/SparcModel_MMU/Sparc_Execution.thy b/thys/SPARCv8/SparcModel_MMU/Sparc_Execution.thy
--- a/thys/SPARCv8/SparcModel_MMU/Sparc_Execution.thy
+++ b/thys/SPARCv8/SparcModel_MMU/Sparc_Execution.thy
@@ -1,431 +1,431 @@
 (*
  * Copyright 2016, NTU
  *
  * This software may be distributed and modified according to the terms of
  * the BSD 2-Clause license. Note that NO WARRANTY is provided.
  * See "LICENSE_BSD2.txt" for details.
  *
  * Author: Zhe Hou, David Sanan.
  *)
 
 theory Sparc_Execution
 imports Main Sparc_Instruction Sparc_State Sparc_Types 
 "HOL-Eisbach.Eisbach_Tools"
 begin
 
 primrec sum :: "nat \<Rightarrow> nat" where
 "sum 0 = 0" |
 "sum (Suc n) = Suc n + sum n"
 
 definition select_trap :: "unit \<Rightarrow> ('a,unit) sparc_state_monad"
 where "select_trap _ \<equiv>
   do
     traps \<leftarrow> gets (\<lambda>s. (get_trap_set s));
     rt_val \<leftarrow> gets (\<lambda>s. (reset_trap_val s));
     psr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PSR s));
     et_val \<leftarrow> gets (\<lambda>s. (get_ET psr_val));
     modify (\<lambda>s. (emp_trap_set s));
     if rt_val = True then \<comment> \<open>ignore \<open>ET\<close>, and leave \<open>tt\<close> unchaged\<close>
       return ()
     else if et_val = 0 then \<comment> \<open>go to error mode, machine needs reset\<close>
       do
         set_err_mode True;
         set_exe_mode False;
         fail ()
       od
     \<comment> \<open>By the SPARCv8 manual only 1 of the following traps could be in traps.\<close>
     else if data_store_error \<in> traps  then
       do
         write_cpu_tt (0b00101011::word8);
         return ()
       od
     else if instruction_access_error \<in> traps then
       do
         write_cpu_tt (0b00100001::word8);
         return ()
       od
     else if r_register_access_error \<in> traps then
       do
         write_cpu_tt (0b00100000::word8);
         return ()
       od
     else if instruction_access_exception \<in> traps then
       do
         write_cpu_tt (0b00000001::word8);
         return ()
       od
     else if privileged_instruction \<in> traps then  
       do
         write_cpu_tt (0b00000011::word8);
         return ()
       od
     else if illegal_instruction \<in> traps then
       do
         write_cpu_tt (0b00000010::word8);
         return ()
       od
     else if fp_disabled \<in> traps then
       do
         write_cpu_tt (0b00000100::word8);
         return ()
       od
     else if cp_disabled \<in> traps then
       do
         write_cpu_tt (0b00100100::word8);
         return ()
       od
     else if unimplemented_FLUSH \<in> traps then
       do
         write_cpu_tt (0b00100101::word8);
         return ()
       od
     else if window_overflow \<in> traps then
       do
         write_cpu_tt (0b00000101::word8);
         return ()
       od
     else if window_underflow \<in> traps then
       do
         write_cpu_tt (0b00000110::word8);
         return ()
       od  
     else if mem_address_not_aligned \<in> traps then
       do
         write_cpu_tt (0b00000111::word8);
         return ()
       od
     else if fp_exception \<in> traps then
       do  
         write_cpu_tt (0b00001000::word8);
         return ()
       od
     else if cp_exception \<in> traps then
       do
         write_cpu_tt (0b00101000::word8);
         return ()
       od
     else if data_access_error \<in> traps then
       do
         write_cpu_tt (0b00101001::word8);
         return ()
       od
     else if data_access_exception \<in> traps then
       do
         write_cpu_tt (0b00001001::word8);
         return ()
       od  
     else if tag_overflow \<in> traps then
       do
         write_cpu_tt (0b00001010::word8);
         return ()
       od
     else if division_by_zero \<in> traps then
       do
         write_cpu_tt (0b00101010::word8);
         return ()
       od
     else if trap_instruction \<in> traps then
       do 
         ticc_trap_type \<leftarrow> gets (\<lambda>s. (ticc_trap_type_val s));
         write_cpu_tt (word_cat (1::word1) ticc_trap_type);
         return ()
       od
     \<^cancel>\<open>else if interrupt_level > 0 then\<close>
     \<comment> \<open>We don't consider \<open>interrupt_level\<close>\<close>
     else return ()
   od"
 
 definition exe_trap_st_pc :: "unit \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "exe_trap_st_pc _ \<equiv>
   do
     annul \<leftarrow> gets (\<lambda>s. (annul_val s));
     pc_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PC s));
     npc_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val nPC s));
     curr_win \<leftarrow> get_curr_win();
     if annul = False then
       do
         write_reg pc_val curr_win (word_of_int 17);
         write_reg npc_val curr_win (word_of_int 18);
         return ()
       od
     else \<comment> \<open>\<open>annul = True\<close>\<close>
       do
         write_reg npc_val curr_win (word_of_int 17);
         write_reg (npc_val + 4) curr_win (word_of_int 18);
         set_annul False;
         return ()
       od
   od"
 
 definition exe_trap_wr_pc :: "unit \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "exe_trap_wr_pc _ \<equiv>
   do
     psr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PSR s));
     new_psr_val \<leftarrow> gets (\<lambda>s. (update_S (1::word1) psr_val));
     write_cpu new_psr_val PSR;
     reset_trap \<leftarrow> gets (\<lambda>s. (reset_trap_val s));
     tbr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val TBR s));
     if reset_trap = False then
       do
         write_cpu tbr_val PC;
         write_cpu (tbr_val + 4) nPC;
         return ()
       od
     else \<comment> \<open>\<open>reset_trap = True\<close>\<close>
       do
         write_cpu 0 PC;
         write_cpu 4 nPC;
         set_reset_trap False;
         return ()
       od
   od"
   
 definition execute_trap :: "unit \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "execute_trap _ \<equiv>
   do
     select_trap();
     err_mode \<leftarrow> gets (\<lambda>s. (err_mode_val s));
     if err_mode = True then 
       \<comment> \<open>The SparcV8 manual doesn't say what to do.\<close>
       return ()
     else
       do
         psr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PSR s));
         s_val \<leftarrow> gets (\<lambda>s. ((ucast (get_S psr_val))::word1));
         curr_win \<leftarrow> get_curr_win();
         new_cwp \<leftarrow> gets (\<lambda>s. ((word_of_int (((uint curr_win) - 1) mod NWINDOWS)))::word5);
         new_psr_val \<leftarrow> gets (\<lambda>s. (update_PSR_exe_trap new_cwp (0::word1) s_val psr_val));
         write_cpu new_psr_val PSR;          
         exe_trap_st_pc();         
         exe_trap_wr_pc();
         return ()
       od  
   od"
 
 definition dispatch_instruction :: "instruction \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "dispatch_instruction instr \<equiv> 
   let instr_name = fst instr in
   do
     traps \<leftarrow> gets (\<lambda>s. (get_trap_set s));
     if traps = {} then 
       if instr_name \<in> {load_store_type LDSB,load_store_type LDUB,
         load_store_type LDUBA,load_store_type LDUH,load_store_type LD,
         load_store_type LDA,load_store_type LDD} then
         load_instr instr
       else if instr_name \<in> {load_store_type STB,load_store_type STH,
         load_store_type ST,load_store_type STA,load_store_type STD} then
         store_instr instr
       else if instr_name \<in> {sethi_type SETHI} then
         sethi_instr instr
       else if instr_name \<in> {nop_type NOP} then
         nop_instr instr
       else if instr_name \<in> {logic_type ANDs,logic_type ANDcc,logic_type ANDN,
         logic_type ANDNcc,logic_type ORs,logic_type ORcc,logic_type ORN,
         logic_type XORs,logic_type XNOR} then
         logical_instr instr
       else if instr_name \<in> {shift_type SLL,shift_type SRL,shift_type SRA} then
         shift_instr instr
       else if instr_name \<in> {arith_type ADD,arith_type ADDcc,arith_type ADDX} then
         add_instr instr
       else if instr_name \<in> {arith_type SUB,arith_type SUBcc,arith_type SUBX} then
         sub_instr instr
       else if instr_name \<in> {arith_type UMUL,arith_type SMUL,arith_type SMULcc} then
         mul_instr instr
       else if instr_name \<in> {arith_type UDIV,arith_type UDIVcc,arith_type SDIV} then
         div_instr instr
       else if instr_name \<in> {ctrl_type SAVE,ctrl_type RESTORE} then
         save_restore_instr instr
       else if instr_name \<in> {call_type CALL} then
         call_instr instr
       else if instr_name \<in> {ctrl_type JMPL} then
         jmpl_instr instr
       else if instr_name \<in> {ctrl_type RETT} then
         rett_instr instr
       else if instr_name \<in> {sreg_type RDY,sreg_type RDPSR,sreg_type RDWIM,
         sreg_type RDTBR} then
         read_state_reg_instr instr
       else if instr_name \<in> {sreg_type WRY,sreg_type WRPSR,sreg_type WRWIM,
         sreg_type WRTBR} then 
         write_state_reg_instr instr
       else if instr_name \<in> {load_store_type FLUSH} then
         flush_instr instr
       else if instr_name \<in> {bicc_type BE,bicc_type BNE,bicc_type BGU,
         bicc_type BLE,bicc_type BL,bicc_type BGE,bicc_type BNEG,bicc_type BG,
         bicc_type BCS,bicc_type BLEU,bicc_type BCC,bicc_type BA,bicc_type BN} then
         branch_instr instr
       else fail ()
     else return ()
   od"
 
 definition supported_instruction :: "sparc_operation \<Rightarrow> bool"
 where "supported_instruction instr \<equiv>
   if instr \<in> {load_store_type LDSB,load_store_type LDUB,load_store_type LDUBA,
               load_store_type LDUH,load_store_type LD,load_store_type LDA,
               load_store_type LDD,
               load_store_type STB,load_store_type STH,load_store_type ST,
               load_store_type STA,load_store_type STD,
               sethi_type SETHI,
               nop_type NOP,
               logic_type ANDs,logic_type ANDcc,logic_type ANDN,logic_type ANDNcc,
               logic_type ORs,logic_type ORcc,logic_type ORN,logic_type XORs,
               logic_type XNOR,
               shift_type SLL,shift_type SRL,shift_type SRA,
               arith_type ADD,arith_type ADDcc,arith_type ADDX,
               arith_type SUB,arith_type SUBcc,arith_type SUBX,
               arith_type UMUL,arith_type SMUL,arith_type SMULcc,
               arith_type UDIV,arith_type UDIVcc,arith_type SDIV,
               ctrl_type SAVE,ctrl_type RESTORE,
               call_type CALL,
               ctrl_type JMPL,
               ctrl_type RETT,
               sreg_type RDY,sreg_type RDPSR,sreg_type RDWIM,sreg_type RDTBR,
               sreg_type WRY,sreg_type WRPSR,sreg_type WRWIM,sreg_type WRTBR,
               load_store_type FLUSH,
               bicc_type BE,bicc_type BNE,bicc_type BGU,bicc_type BLE,
               bicc_type BL,bicc_type BGE,bicc_type BNEG,bicc_type BG,
               bicc_type BCS,bicc_type BLEU,bicc_type BCC,bicc_type BA,
               bicc_type BN} 
     then True
   else False
 "
 
 definition execute_instr_sub1 :: "instruction \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "execute_instr_sub1 instr \<equiv>
   do
     instr_name \<leftarrow> gets (\<lambda>s. (fst instr));
     traps2 \<leftarrow> gets (\<lambda>s. (get_trap_set s));
     if traps2 = {} \<and> instr_name \<notin> {call_type CALL,ctrl_type RETT,ctrl_type JMPL,
                                    bicc_type BE,bicc_type BNE,bicc_type BGU,
                                    bicc_type BLE,bicc_type BL,bicc_type BGE,
                                    bicc_type BNEG,bicc_type BG,
                                    bicc_type BCS,bicc_type BLEU,bicc_type BCC,
                                    bicc_type BA,bicc_type BN} then
     do
       npc_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val nPC s));
       write_cpu npc_val PC;
       write_cpu (npc_val + 4) nPC;
       return ()
     od
     else return ()
   od"
 
 definition execute_instruction :: "unit \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "execute_instruction _ \<equiv> 
   do
     traps \<leftarrow> gets (\<lambda>s. (get_trap_set s));
     if traps = {} then 
     do
       exe_mode \<leftarrow> gets (\<lambda>s. (exe_mode_val s));
       if exe_mode = True then
       do
         modify (\<lambda>s. (delayed_pool_write s));
         fetch_result \<leftarrow> gets (\<lambda>s. (fetch_instruction s));
         case fetch_result of 
         Inl e1 \<Rightarrow> (do \<comment> \<open>Memory address in PC is not aligned.\<close>
                       \<comment> \<open>Actually, SparcV8 manual doens't check alignment here.\<close>
                     raise_trap instruction_access_exception;
                     return ()
                   od) 
         | Inr v1 \<Rightarrow> (do
           dec \<leftarrow> gets (\<lambda>s. (decode_instruction v1));
           case dec of 
             Inl e2 \<Rightarrow> (\<comment> \<open>Instruction is ill-formatted.\<close>
                         fail ()
                       )
             | Inr v2 \<Rightarrow> (do
               instr \<leftarrow> gets (\<lambda>s. (v2));
               annul \<leftarrow> gets (\<lambda>s. (annul_val s));
               if annul = False then 
               do
                 dispatch_instruction instr;
                 execute_instr_sub1 instr;
                 return ()
               od
               else \<comment> \<open>\<open>annul \<noteq> False\<close>\<close>
               do
                 set_annul False;
                 npc_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val nPC s));
                 write_cpu npc_val PC;
                 write_cpu (npc_val + 4) nPC;
                 return ()
               od
             od)
         od) 
       od
       else return () \<comment> \<open>Not in \<open>execute_mode\<close>.\<close>
     od
     else \<comment> \<open>traps is not empty, which means \<open>trap = 1\<close>.\<close>
     do
       execute_trap();
       return ()
     od
   od"
 
 definition NEXT :: "('a::len0)sparc_state \<Rightarrow> ('a)sparc_state option"
 where "NEXT s \<equiv> case execute_instruction () s of (_,True) \<Rightarrow> None
 | (s',False) \<Rightarrow> Some (snd s')"
 
 definition good_context :: "('a::len0) sparc_state \<Rightarrow> bool"
 where "good_context s \<equiv> 
   let traps = get_trap_set s;
       psr_val = cpu_reg_val PSR s;
       et_val = get_ET psr_val;
       rt_val = reset_trap_val s
   in
   if traps \<noteq> {} \<and> rt_val = False \<and> et_val = 0 then False \<comment> \<open>enter \<open>error_mode\<close> in \<open>select_traps\<close>.\<close>
   else
     let s' = delayed_pool_write s in
     case fetch_instruction s' of
     \<comment> \<open>\<open>instruction_access_exception\<close> is handled in the next state.\<close>
     Inl _ \<Rightarrow> True 
     |Inr v \<Rightarrow> (
       case decode_instruction v of 
       Inl _ \<Rightarrow> False 
       |Inr instr \<Rightarrow> (
         let annul = annul_val s' in
         if annul = True then True
         else \<comment> \<open>\<open>annul = False\<close>\<close>
           if supported_instruction (fst instr) then
             \<comment> \<open>The only instruction that could fail is \<open>RETT\<close>.\<close>
             if (fst instr) = ctrl_type RETT then
               let curr_win_r = (get_CWP (cpu_reg_val PSR s'));
                   new_cwp_int_r = (((uint curr_win_r) + 1) mod NWINDOWS);
                   wim_val_r = cpu_reg_val WIM s';
                   psr_val_r = cpu_reg_val PSR s';
                   et_val_r = get_ET psr_val_r;
                   s_val_r = (ucast (get_S psr_val_r))::word1;
                   op_list_r = snd instr;
                   addr_r = get_addr (snd instr) s'
               in
               if et_val_r = 1 then True
               else if s_val_r = 0 then False
               else if (get_WIM_bit (nat new_cwp_int_r) wim_val_r) \<noteq> 0 then False
-              else if (bitAND addr_r (0b00000000000000000000000000000011::word32)) \<noteq> 0 then False
+              else if ((AND) addr_r (0b00000000000000000000000000000011::word32)) \<noteq> 0 then False
               else True
             else True
           else False \<comment> \<open>Unsupported instruction.\<close>
       )  
     )
 "
 
 function (sequential) seq_exec:: "nat \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "seq_exec 0 = return ()"
  |
 "seq_exec n =  (do execute_instruction();
                   (seq_exec (n-1))
                od)
 "
 by pat_completeness auto
 termination by lexicographic_order
 
 type_synonym leon3_state = "(word_length5) sparc_state"
 
 type_synonym ('e) leon3_state_monad = "(leon3_state, 'e) det_monad"
 
 definition execute_leon3_instruction:: "unit \<Rightarrow> (unit) leon3_state_monad"
 where "execute_leon3_instruction \<equiv> execute_instruction"
 
 definition seq_exec_leon3:: "nat \<Rightarrow> (unit) leon3_state_monad"
 where "seq_exec_leon3 \<equiv> seq_exec"
 
 end
diff --git a/thys/SPARCv8/SparcModel_MMU/Sparc_Instruction.thy b/thys/SPARCv8/SparcModel_MMU/Sparc_Instruction.thy
--- a/thys/SPARCv8/SparcModel_MMU/Sparc_Instruction.thy
+++ b/thys/SPARCv8/SparcModel_MMU/Sparc_Instruction.thy
@@ -1,2788 +1,2788 @@
 (*
  * Copyright 2016, NTU
  *
  * This software may be distributed and modified according to the terms of
  * the BSD 2-Clause license. Note that NO WARRANTY is provided.
  * See "LICENSE_BSD2.txt" for details.
  *
  * Author: Zhe Hou, David Sanan.
  *)
 
 section \<open>SPARC instruction model\<close>
 theory Sparc_Instruction
 imports Main Sparc_Types Sparc_State "HOL-Eisbach.Eisbach_Tools"
 begin
 text\<open>
 This theory provides a formal model for assembly instruction to be executed in the model.
 
 An instruction is defined as a tuple composed of a @{term sparc_operation} element,
 defining the operation the instruction carries out, and a list of operands 
 @{term inst_operand}. @{term inst_operand} can be a user register @{term user_reg} 
 or a memory address @{term mem_add_type}.
 \<close>
 datatype inst_operand = 
 W5 word5
 |W30 word30
 |W22 word22
 |Cond  word4
 |Flag word1
 |Asi asi_type
 |Simm13 word13 
 |Opf word9
 |Imm7 word7
 
 primrec get_operand_w5::"inst_operand \<Rightarrow> word5"
 where "get_operand_w5 (W5 r) = r"
 
 primrec get_operand_w30::"inst_operand \<Rightarrow> word30"
 where "get_operand_w30 (W30 r) = r"
 
 primrec get_operand_w22::"inst_operand \<Rightarrow> word22"
 where "get_operand_w22 (W22 r) = r"
 
 primrec get_operand_cond::"inst_operand \<Rightarrow> word4"
 where "get_operand_cond (Cond r) = r"
 
 primrec get_operand_flag::"inst_operand \<Rightarrow> word1"
 where "get_operand_flag (Flag r) = r"
 
 primrec get_operand_asi::"inst_operand \<Rightarrow> asi_type"
 where "get_operand_asi (Asi r) = r"
 
 primrec get_operand_simm13::"inst_operand \<Rightarrow> word13"
 where "get_operand_simm13 (Simm13 r) = r"
 
 primrec get_operand_opf::"inst_operand \<Rightarrow> word9"
 where "get_operand_opf (Opf r) = r"
 
 primrec get_operand_imm7:: "inst_operand \<Rightarrow> word7"
 where "get_operand_imm7 (Imm7 r) = r"
 
 type_synonym instruction = "(sparc_operation \<times> inst_operand list)"
 
 definition get_op::"word32 \<Rightarrow> int"
 where "get_op w \<equiv> uint (w >> 30)"
 
 definition get_op2::"word32 \<Rightarrow> int"
 where "get_op2 w \<equiv> 
   let mask_op2 = 0b00000001110000000000000000000000 in
-  uint ((bitAND mask_op2 w) >> 22)"
+  uint (((AND) mask_op2 w) >> 22)"
 
 definition get_op3::"word32 \<Rightarrow> int"
 where "get_op3 w \<equiv> 
   let mask_op3 = 0b00000001111110000000000000000000 in 
-  uint ((bitAND mask_op3 w) >> 19)"
+  uint (((AND) mask_op3 w) >> 19)"
 
 definition get_disp30::"word32 \<Rightarrow> int"
 where "get_disp30 w \<equiv> 
   let mask_disp30 = 0b00111111111111111111111111111111 in
-  uint (bitAND mask_disp30 w)"
+  uint ((AND) mask_disp30 w)"
 
 definition get_a::"word32 \<Rightarrow> int"
 where "get_a w \<equiv>
   let mask_a = 0b00100000000000000000000000000000 in
-  uint ((bitAND mask_a w) >> 29)"
+  uint (((AND) mask_a w) >> 29)"
 
 definition get_cond::"word32 \<Rightarrow> int"
 where "get_cond w \<equiv>
   let mask_cond = 0b00011110000000000000000000000000 in
-  uint ((bitAND mask_cond w) >> 25)"
+  uint (((AND) mask_cond w) >> 25)"
 
 definition get_disp_imm22::"word32 \<Rightarrow> int"
 where "get_disp_imm22 w \<equiv>
   let mask_disp_imm22 = 0b00000000001111111111111111111111 in
-  uint (bitAND mask_disp_imm22 w)"
+  uint ((AND) mask_disp_imm22 w)"
 
 definition get_rd::"word32 \<Rightarrow> int"
 where "get_rd w \<equiv>
   let mask_rd = 0b00111110000000000000000000000000 in
-  uint ((bitAND mask_rd w) >> 25)"
+  uint (((AND) mask_rd w) >> 25)"
 
 definition get_rs1::"word32 \<Rightarrow> int"
 where "get_rs1 w \<equiv>
   let mask_rs1 = 0b00000000000001111100000000000000 in
-  uint ((bitAND mask_rs1 w) >> 14)"
+  uint (((AND) mask_rs1 w) >> 14)"
 
 definition get_i::"word32 \<Rightarrow> int"
 where "get_i w \<equiv>
   let mask_i = 0b00000000000000000010000000000000 in
-  uint ((bitAND mask_i w) >> 13)"
+  uint (((AND) mask_i w) >> 13)"
 
 definition get_opf::"word32 \<Rightarrow> int"
 where "get_opf w \<equiv> 
   let mask_opf = 0b00000000000000000011111111100000 in
-  uint ((bitAND mask_opf w) >> 5)"
+  uint (((AND) mask_opf w) >> 5)"
 
 definition get_rs2::"word32 \<Rightarrow> int"
 where "get_rs2 w \<equiv>
   let mask_rs2 = 0b00000000000000000000000000011111 in
-  uint (bitAND mask_rs2 w)"
+  uint ((AND) mask_rs2 w)"
 
 definition get_simm13::"word32 \<Rightarrow> int"
 where "get_simm13 w \<equiv>
   let mask_simm13 = 0b00000000000000000001111111111111 in
-  uint (bitAND mask_simm13 w)"
+  uint ((AND) mask_simm13 w)"
 
 definition get_asi::"word32 \<Rightarrow> int"
 where "get_asi w \<equiv>
   let mask_asi = 0b00000000000000000001111111100000 in
-  uint ((bitAND mask_asi w) >> 5)"
+  uint (((AND) mask_asi w) >> 5)"
 
 definition get_trap_cond:: "word32 \<Rightarrow> int"
 where "get_trap_cond w \<equiv>
   let mask_cond = 0b00011110000000000000000000000000 in
-  uint ((bitAND mask_cond w) >> 25)"
+  uint (((AND) mask_cond w) >> 25)"
 
 definition get_trap_imm7:: "word32 \<Rightarrow> int"
 where "get_trap_imm7 w \<equiv>
   let mask_imm7 = 0b00000000000000000000000001111111 in
-  uint (bitAND mask_imm7 w)"
+  uint ((AND) mask_imm7 w)"
 
 definition parse_instr_f1::"word32 \<Rightarrow> 
   (Exception list + instruction)"
 where \<comment> \<open>\<open>CALL\<close>, with a single operand \<open>disp30+"00"\<close>\<close>
 "parse_instr_f1 w \<equiv>                                                     
   Inr (call_type CALL,[W30 (word_of_int (get_disp30 w))])"
 
 definition parse_instr_f2::"word32 \<Rightarrow> 
   (Exception list + instruction)"
 where "parse_instr_f2 w \<equiv>
   let op2 = get_op2 w in
   if op2 = uint(0b100::word3) then \<comment> \<open>\<open>SETHI\<close> or \<open>NOP\<close>\<close>
     let rd = get_rd w in
     let imm22 = get_disp_imm22 w in
     if rd = 0 \<and> imm22 = 0 then \<comment> \<open>\<open>NOP\<close>\<close>
       Inr (nop_type NOP,[])
     else \<comment> \<open>\<open>SETHI\<close>, with operands \<open>[imm22,rd]\<close>\<close>
       Inr (sethi_type SETHI,[(W22 (word_of_int imm22)),
                    (W5 (word_of_int rd))])
   else if op2 = uint(0b010::word3) then \<comment> \<open>\<open>Bicc\<close>, with operands \<open>[a,disp22]\<close>\<close>
     let cond = get_cond w in
     let flaga = Flag (word_of_int (get_a w)) in
     let disp22 = W22 (word_of_int (get_disp_imm22 w)) in
     if cond = uint(0b0001::word4) then \<comment> \<open>\<open>BE\<close>\<close>
       Inr (bicc_type BE,[flaga,disp22])
     else if cond = uint(0b1001::word4) then \<comment> \<open>\<open>BNE\<close>\<close>
       Inr (bicc_type BNE,[flaga,disp22])
     else if cond = uint(0b1100::word4) then \<comment> \<open>\<open>BGU\<close>\<close>
       Inr (bicc_type BGU,[flaga,disp22])
     else if cond = uint(0b0010::word4) then \<comment> \<open>\<open>BLE\<close>\<close>
       Inr (bicc_type BLE,[flaga,disp22])
     else if cond = uint(0b0011::word4) then \<comment> \<open>\<open>BL\<close>\<close>
       Inr (bicc_type BL,[flaga,disp22])
     else if cond = uint(0b1011::word4) then \<comment> \<open>\<open>BGE\<close>\<close>
       Inr (bicc_type BGE,[flaga,disp22])
     else if cond = uint(0b0110::word4) then \<comment> \<open>\<open>BNEG\<close>\<close>
       Inr (bicc_type BNEG,[flaga,disp22])
     else if cond = uint(0b1010::word4) then \<comment> \<open>\<open>BG\<close>\<close>
       Inr (bicc_type BG,[flaga,disp22])
     else if cond = uint(0b0101::word4) then \<comment> \<open>\<open>BCS\<close>\<close>
       Inr (bicc_type BCS,[flaga,disp22])
     else if cond = uint(0b0100::word4) then \<comment> \<open>\<open>BLEU\<close>\<close>
       Inr (bicc_type BLEU,[flaga,disp22])
     else if cond = uint(0b1101::word4) then \<comment> \<open>\<open>BCC\<close>\<close>
       Inr (bicc_type BCC,[flaga,disp22])
     else if cond = uint(0b1000::word4) then \<comment> \<open>\<open>BA\<close>\<close>
       Inr (bicc_type BA,[flaga,disp22])
     else if cond = uint(0b0000::word4) then \<comment> \<open>\<open>BN\<close>\<close>
       Inr (bicc_type BN,[flaga,disp22])
     else if cond = uint(0b1110::word4) then \<comment> \<open>\<open>BPOS\<close>\<close>
       Inr (bicc_type BPOS,[flaga,disp22])
     else if cond = uint(0b1111::word4) then \<comment> \<open>\<open>BVC\<close>\<close>
       Inr (bicc_type BVC,[flaga,disp22])
     else if cond = uint(0b0111::word4) then \<comment> \<open>\<open>BVS\<close>\<close>
       Inr (bicc_type BVS,[flaga,disp22])
     else Inl [invalid_cond_f2]
   else Inl [invalid_op2_f2]
 "
 
 text \<open>We don't consider floating-point operations, 
         so we don't consider the third type of format 3.\<close>
 definition parse_instr_f3::"word32 \<Rightarrow> (Exception list + instruction)"
 where "parse_instr_f3 w \<equiv>
   let this_op = get_op w in
   let rd = get_rd w in
   let op3 = get_op3 w in
   let rs1 = get_rs1 w in
   let flagi = get_i w in
   let asi = get_asi w in
   let rs2 = get_rs2 w in
   let simm13 = get_simm13 w in
   if this_op = uint(0b11::word2) then \<comment> \<open>Load and Store\<close>
   \<comment> \<open>If an instruction accesses alternative space but \<open>flagi = 1\<close>,\<close>
   \<comment> \<open>may need to throw a trap.\<close>
     if op3 = uint(0b001001::word6) then \<comment> \<open>\<open>LDSB\<close>\<close>
       if flagi = 1 then \<comment> \<open>Operant list is \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (load_store_type LDSB,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>Operant list is \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (load_store_type LDSB,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b011001::word6) then \<comment> \<open>\<open>LDSBA\<close>\<close>
        Inr (load_store_type LDSBA,[(Flag (word_of_int flagi)),
                          (W5 (word_of_int rs1)),
                          (W5 (word_of_int rs2)),
                          (Asi (word_of_int asi)),
                          (W5 (word_of_int rd))])
     else if op3 = uint(0b001010::word6) then \<comment> \<open>\<open>LDSH\<close>\<close>
       if flagi = 1 then \<comment> \<open>Operant list is \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (load_store_type LDSH,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>Operant list is \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (load_store_type LDSH,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b011010::word6) then \<comment> \<open>\<open>LDSHA\<close>\<close>
        Inr (load_store_type LDSHA,[(Flag (word_of_int flagi)),
                          (W5 (word_of_int rs1)),
                          (W5 (word_of_int rs2)),
                          (Asi (word_of_int asi)),
                          (W5 (word_of_int rd))])
     else if op3 = uint(0b000001::word6) then \<comment> \<open>\<open>LDUB\<close>\<close>
       if flagi = 1 then \<comment> \<open>Operant list is \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (load_store_type LDUB,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>Operant list is \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (load_store_type LDUB,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b010001::word6) then \<comment> \<open>\<open>LDUBA\<close>\<close>
        Inr (load_store_type LDUBA,[(Flag (word_of_int flagi)),
                          (W5 (word_of_int rs1)),
                          (W5 (word_of_int rs2)),
                          (Asi (word_of_int asi)),
                          (W5 (word_of_int rd))])
     else if op3 = uint(0b000010::word6) then \<comment> \<open>\<open>LDUH\<close>\<close>
       if flagi = 1 then \<comment> \<open>Operant list is \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (load_store_type LDUH,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>Operant list is \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (load_store_type LDUH,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b010010::word6) then \<comment> \<open>\<open>LDUHA\<close>\<close>
        Inr (load_store_type LDUHA,[(Flag (word_of_int flagi)),
                          (W5 (word_of_int rs1)),
                          (W5 (word_of_int rs2)),
                          (Asi (word_of_int asi)),
                          (W5 (word_of_int rd))])
     else if op3 = uint(0b000000::word6) then \<comment> \<open>\<open>LD\<close>\<close>
       if flagi = 1 then \<comment> \<open>Operant list is \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (load_store_type LD,[(Flag (word_of_int flagi)),
                       (W5 (word_of_int rs1)),
                       (Simm13 (word_of_int simm13)),
                       (W5 (word_of_int rd))])
       else \<comment> \<open>Operant list is \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (load_store_type LD,[(Flag (word_of_int flagi)),
                       (W5 (word_of_int rs1)),
                       (W5 (word_of_int rs2)),
                       (W5 (word_of_int rd))])
     else if op3 = uint(0b010000::word6) then \<comment> \<open>\<open>LDA\<close>\<close>
        Inr (load_store_type LDA,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int rs2)),
                        (Asi (word_of_int asi)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b000011::word6) then \<comment> \<open>\<open>LDD\<close>\<close>
       if flagi = 1 then \<comment> \<open>Operant list is \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (load_store_type LDD,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (Simm13 (word_of_int simm13)),
                        (W5 (word_of_int rd))])
       else \<comment> \<open>Operant list is \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (load_store_type LDD,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int rs2)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b010011::word6) then \<comment> \<open>\<open>LDDA\<close>\<close>
        Inr (load_store_type LDDA,[(Flag (word_of_int flagi)),
                          (W5 (word_of_int rs1)),
                          (W5 (word_of_int rs2)),
                          (Asi (word_of_int asi)),
                          (W5 (word_of_int rd))])
     else if op3 = uint(0b001101::word6) then \<comment> \<open>\<open>LDSTUB\<close>\<close>
       if flagi = 1 then \<comment> \<open>Operant list is \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (load_store_type LDSTUB,[(Flag (word_of_int flagi)),
                       (W5 (word_of_int rs1)),
                       (Simm13 (word_of_int simm13)),
                       (W5 (word_of_int rd))])
       else \<comment> \<open>Operant list is \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (load_store_type LDSTUB,[(Flag (word_of_int flagi)),
                       (W5 (word_of_int rs1)),
                       (W5 (word_of_int rs2)),
                       (W5 (word_of_int rd))])
     else if op3 = uint(0b011101::word6) then \<comment> \<open>\<open>LDSTUBA\<close>\<close>
        Inr (load_store_type LDSTUBA,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int rs2)),
                        (Asi (word_of_int asi)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b000101::word6) then \<comment> \<open>\<open>STB\<close>\<close>
       if flagi = 1 then \<comment> \<open>Operant list is \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (load_store_type STB,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (Simm13 (word_of_int simm13)),
                        (W5 (word_of_int rd))])
       else \<comment> \<open>Operant list is \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (load_store_type STB,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int rs2)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b010101::word6) then \<comment> \<open>\<open>STBA\<close>\<close>
        Inr (load_store_type STBA,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int rs2)),
                        (Asi (word_of_int asi)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b000110::word6) then \<comment> \<open>\<open>STH\<close>\<close>
       if flagi = 1 then \<comment> \<open>Operant list is \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (load_store_type STH,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (Simm13 (word_of_int simm13)),
                        (W5 (word_of_int rd))])
       else \<comment> \<open>Operant list is \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (load_store_type STH,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int rs2)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b010110::word6) then \<comment> \<open>\<open>STHA\<close>\<close>
        Inr (load_store_type STHA,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int rs2)),
                        (Asi (word_of_int asi)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b000100::word6) then \<comment> \<open>\<open>ST\<close>\<close>
       if flagi = 1 then \<comment> \<open>Operant list is \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (load_store_type ST,[(Flag (word_of_int flagi)),
                       (W5 (word_of_int rs1)),
                       (Simm13 (word_of_int simm13)),
                       (W5 (word_of_int rd))])
       else \<comment> \<open>Operant list is \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (load_store_type ST,[(Flag (word_of_int flagi)),
                       (W5 (word_of_int rs1)),
                       (W5 (word_of_int rs2)),
                       (W5 (word_of_int rd))])
     else if op3 = uint(0b010100::word6) then \<comment> \<open>\<open>STA\<close>\<close>
        Inr (load_store_type STA,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int rs2)),
                        (Asi (word_of_int asi)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b000111::word6) then \<comment> \<open>\<open>STD\<close>\<close>
       if flagi = 1 then \<comment> \<open>Operant list is \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (load_store_type STD,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (Simm13 (word_of_int simm13)),
                        (W5 (word_of_int rd))])
       else \<comment> \<open>Operant list is \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (load_store_type STD,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int rs2)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b010111::word6) then \<comment> \<open>\<open>STDA\<close>\<close>
        Inr (load_store_type STDA,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int rs2)),
                        (Asi (word_of_int asi)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b001111::word6) then \<comment> \<open>\<open>SWAP\<close>\<close>
       if flagi = 1 then \<comment> \<open>Operant list is \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (load_store_type SWAP,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (Simm13 (word_of_int simm13)),
                        (W5 (word_of_int rd))])
       else \<comment> \<open>Operant list is \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (load_store_type SWAP,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int rs2)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b011111::word6) then \<comment> \<open>\<open>SWAPA\<close>\<close>
        Inr (load_store_type SWAPA,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int rs2)),
                        (Asi (word_of_int asi)),
                        (W5 (word_of_int rd))])
     else Inl [invalid_op3_f3_op11]
   else if this_op = uint(0b10::word2) then \<comment> \<open>Others\<close>
     if op3 = uint(0b111000::word6) then \<comment> \<open>\<open>JMPL\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (ctrl_type JMPL,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (ctrl_type JMPL,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b111001::word6) then \<comment> \<open>\<open>RETT\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2]\<close>\<close>
          Inr (ctrl_type RETT,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2))])
       else \<comment> \<open>return \<open>[i,rs1,simm13]\<close>\<close>
          Inr (ctrl_type RETT,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13))])
     \<comment> \<open>The following are Read and Write instructions,\<close>
     \<comment> \<open>only return \<open>[rs1,rd]\<close> as operand.\<close>
     else if op3 = uint(0b101000::word6) \<and> rs1 \<noteq> 0 then \<comment> \<open>\<open>RDASR\<close>\<close>
       if rs1 = uint(0b01111::word6) \<and> rd = 0 then \<comment> \<open>\<open>STBAR\<close> is a special case of \<open>RDASR\<close>\<close>
         Inr (load_store_type STBAR,[])
       else Inr (sreg_type RDASR,[(W5 (word_of_int rs1)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b101000::word6) \<and> rs1 = 0 then \<comment> \<open>\<open>RDY\<close>\<close>
        Inr (sreg_type RDY,[(W5 (word_of_int rs1)),
                      (W5 (word_of_int rd))])
     else if op3 = uint(0b101001::word6) then \<comment> \<open>\<open>RDPSR\<close>\<close>
        Inr (sreg_type RDPSR,[(W5 (word_of_int rs1)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b101010::word6) then \<comment> \<open>\<open>RDWIM\<close>\<close>
        Inr (sreg_type RDWIM,[(W5 (word_of_int rs1)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b101011::word6) then \<comment> \<open>\<open>RDTBR\<close>\<close>
        Inr (sreg_type RDTBR,[(W5 (word_of_int rs1)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b110000::word6) \<and> rd \<noteq> 0 then \<comment> \<open>\<open>WRASR\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (sreg_type WRASR,[(Flag (word_of_int flagi)),
                          (W5 (word_of_int rs1)),
                          (W5 (word_of_int rs2)),
                          (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (sreg_type WRASR,[(Flag (word_of_int flagi)),
                          (W5 (word_of_int rs1)),
                          (Simm13 (word_of_int simm13)),
                          (W5 (word_of_int rd))])
     else if op3 = uint(0b110000::word6) \<and> rd = 0 then \<comment> \<open>\<open>WRY\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (sreg_type WRY,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int rs2)),
                        (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (sreg_type WRY,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (Simm13 (word_of_int simm13)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b110001::word6) then \<comment> \<open>\<open>WRPSR\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (sreg_type WRPSR,[(Flag (word_of_int flagi)),
                          (W5 (word_of_int rs1)),
                          (W5 (word_of_int rs2)),
                          (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (sreg_type WRPSR,[(Flag (word_of_int flagi)),
                          (W5 (word_of_int rs1)),
                          (Simm13 (word_of_int simm13)),
                          (W5 (word_of_int rd))])
     else if op3 = uint(0b110010::word6) then \<comment> \<open>\<open>WRWIM\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (sreg_type WRWIM,[(Flag (word_of_int flagi)),
                          (W5 (word_of_int rs1)),
                          (W5 (word_of_int rs2)),
                          (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (sreg_type WRWIM,[(Flag (word_of_int flagi)),
                          (W5 (word_of_int rs1)),
                          (Simm13 (word_of_int simm13)),
                          (W5 (word_of_int rd))])
     else if op3 = uint(0b110011::word6) then \<comment> \<open>\<open>WRTBR\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (sreg_type WRTBR,[(Flag (word_of_int flagi)),
                          (W5 (word_of_int rs1)),
                          (W5 (word_of_int rs2)),
                          (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (sreg_type WRTBR,[(Flag (word_of_int flagi)),
                          (W5 (word_of_int rs1)),
                          (Simm13 (word_of_int simm13)),
                          (W5 (word_of_int rd))])
     \<comment> \<open>\<open>FLUSH\<close> instruction\<close>
     else if op3 = uint(0b111011::word6) then \<comment> \<open>\<open>FLUSH\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[1,rs1,rs2]\<close>\<close>
          Inr (load_store_type FLUSH,[(Flag (word_of_int flagi)),
                          (W5 (word_of_int rs1)),
                          (W5 (word_of_int rs2))])
       else \<comment> \<open>return \<open>[i,rs1,simm13]\<close>\<close>
          Inr (load_store_type FLUSH,[(Flag (word_of_int flagi)),
                          (W5 (word_of_int rs1)),
                          (Simm13 (word_of_int simm13))])
     \<comment> \<open>The following are arithmetic instructions.\<close>
     else if op3 = uint(0b000001::word6) then \<comment> \<open>\<open>AND\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (logic_type ANDs,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (logic_type ANDs,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b010001::word6) then \<comment> \<open>\<open>ANDcc\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (logic_type ANDcc,[(Flag (word_of_int flagi)),
                          (W5 (word_of_int rs1)),
                          (W5 (word_of_int rs2)),
                          (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (logic_type ANDcc,[(Flag (word_of_int flagi)),
                          (W5 (word_of_int rs1)),
                          (Simm13 (word_of_int simm13)),
                          (W5 (word_of_int rd))])
     else if op3 = uint(0b000101::word6) then \<comment> \<open>\<open>ANDN\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (logic_type ANDN,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (logic_type ANDN,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b010101::word6) then \<comment> \<open>\<open>ANDNcc\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (logic_type ANDNcc,[(Flag (word_of_int flagi)),
                           (W5 (word_of_int rs1)),
                           (W5 (word_of_int rs2)),
                           (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (logic_type ANDNcc,[(Flag (word_of_int flagi)),
                           (W5 (word_of_int rs1)),
                           (Simm13 (word_of_int simm13)),
                           (W5 (word_of_int rd))])
     else if op3 = uint(0b000010::word6) then \<comment> \<open>\<open>OR\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (logic_type ORs,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int rs2)),
                        (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (logic_type ORs,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (Simm13 (word_of_int simm13)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b010010::word6) then \<comment> \<open>\<open>ORcc\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (logic_type ORcc,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (logic_type ORcc,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b000110::word6) then \<comment> \<open>\<open>ORN\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (logic_type ORN,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int rs2)),
                        (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (logic_type ORN,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (Simm13 (word_of_int simm13)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b010110::word6) then \<comment> \<open>\<open>ORNcc\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (logic_type ORNcc,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int rs2)),
                        (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (logic_type ORNcc,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (Simm13 (word_of_int simm13)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b000011::word6) then \<comment> \<open>\<open>XORs\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (logic_type XORs,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (logic_type XORs,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b010011::word6) then \<comment> \<open>\<open>XORcc\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (logic_type XORcc,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int rs2)),
                        (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (logic_type XORcc,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (Simm13 (word_of_int simm13)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b000111::word6) then \<comment> \<open>\<open>XNOR\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (logic_type XNOR,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (logic_type XNOR,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b010111::word6) then \<comment> \<open>\<open>XNORcc\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (logic_type XNORcc,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int rs2)),
                        (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (logic_type XNORcc,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (Simm13 (word_of_int simm13)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b100101::word6) then \<comment> \<open>\<open>SLL\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (shift_type SLL,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int rs2)),
                        (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,shcnt,rd]\<close>\<close>
         let shcnt = rs2 in
          Inr (shift_type SLL,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int shcnt)),
                        (W5 (word_of_int rd))])
     else if op3 = uint (0b100110::word6) then \<comment> \<open>\<open>SRL\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (shift_type SRL,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int rs2)),
                        (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,shcnt,rd]\<close>\<close>
         let shcnt = rs2 in
          Inr (shift_type SRL,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int shcnt)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b100111::word6) then \<comment> \<open>\<open>SRA\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (shift_type SRA,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int rs2)),
                        (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,shcnt,rd]\<close>\<close>
         let shcnt = rs2 in
          Inr (shift_type SRA,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int shcnt)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b000000::word6) then \<comment> \<open>\<open>ADD\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (arith_type ADD,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int rs2)),
                        (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (arith_type ADD,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (Simm13 (word_of_int simm13)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b010000::word6) then \<comment> \<open>\<open>ADDcc\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (arith_type ADDcc,[(Flag (word_of_int flagi)),
                          (W5 (word_of_int rs1)),
                          (W5 (word_of_int rs2)),
                          (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (arith_type ADDcc,[(Flag (word_of_int flagi)),
                          (W5 (word_of_int rs1)),
                          (Simm13 (word_of_int simm13)),
                          (W5 (word_of_int rd))])
     else if op3 = uint(0b001000::word6) then \<comment> \<open>\<open>ADDX\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (arith_type ADDX,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (arith_type ADDX,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b011000::word6) then \<comment> \<open>\<open>ADDXcc\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (arith_type ADDXcc,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (arith_type ADDXcc,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b100000::word6) then \<comment> \<open>\<open>TADDcc\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (arith_type TADDcc,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (arith_type TADDcc,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b100010::word6) then \<comment> \<open>\<open>TADDccTV\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (arith_type TADDccTV,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (arith_type TADDccTV,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b000100::word6) then \<comment> \<open>\<open>SUB\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (arith_type SUB,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (W5 (word_of_int rs2)),
                        (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (arith_type SUB,[(Flag (word_of_int flagi)),
                        (W5 (word_of_int rs1)),
                        (Simm13 (word_of_int simm13)),
                        (W5 (word_of_int rd))])
     else if op3 = uint(0b010100::word6) then \<comment> \<open>\<open>SUBcc\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (arith_type SUBcc,[(Flag (word_of_int flagi)),
                          (W5 (word_of_int rs1)),
                          (W5 (word_of_int rs2)),
                          (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (arith_type SUBcc,[(Flag (word_of_int flagi)),
                          (W5 (word_of_int rs1)),
                          (Simm13 (word_of_int simm13)),
                          (W5 (word_of_int rd))])
     else if op3 = uint(0b001100::word6) then \<comment> \<open>\<open>SUBX\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (arith_type SUBX,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (arith_type SUBX,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b011100::word6) then \<comment> \<open>\<open>SUBXcc\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (arith_type SUBXcc,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (arith_type SUBXcc,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b100001::word6) then \<comment> \<open>\<open>TSUBcc\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (arith_type TSUBcc,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (arith_type TSUBcc,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b100011::word6) then \<comment> \<open>\<open>TSUBccTV\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (arith_type TSUBccTV,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (arith_type TSUBccTV,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b100100::word6) then \<comment> \<open>\<open>MULScc\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (arith_type MULScc,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (arith_type MULScc,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b001010::word6) then \<comment> \<open>\<open>UMUL\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (arith_type UMUL,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (arith_type UMUL,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b011010::word6) then \<comment> \<open>\<open>UMULcc\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (arith_type UMULcc,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (arith_type UMULcc,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b001011::word6) then \<comment> \<open>\<open>SMUL\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (arith_type SMUL,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (arith_type SMUL,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b011011::word6) then \<comment> \<open>\<open>SMULcc\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (arith_type SMULcc,[(Flag (word_of_int flagi)),
                           (W5 (word_of_int rs1)),
                           (W5 (word_of_int rs2)),
                           (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (arith_type SMULcc,[(Flag (word_of_int flagi)),
                           (W5 (word_of_int rs1)),
                           (Simm13 (word_of_int simm13)),
                           (W5 (word_of_int rd))])
     else if op3 = uint(0b001110::word6) then \<comment> \<open>\<open>UDIV\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (arith_type UDIV,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (arith_type UDIV,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b011110::word6) then \<comment> \<open>\<open>UDIVcc\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (arith_type UDIVcc,[(Flag (word_of_int flagi)),
                           (W5 (word_of_int rs1)),
                           (W5 (word_of_int rs2)),
                           (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (arith_type UDIVcc,[(Flag (word_of_int flagi)),
                           (W5 (word_of_int rs1)),
                           (Simm13 (word_of_int simm13)),
                           (W5 (word_of_int rd))])
     else if op3 = uint(0b001111::word6) then \<comment> \<open>\<open>SDIV\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (arith_type SDIV,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (arith_type SDIV,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b011111::word6) then \<comment> \<open>\<open>SDIVcc\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (arith_type SDIVcc,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (arith_type SDIVcc,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b111100::word6) then \<comment> \<open>\<open>SAVE\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (ctrl_type SAVE,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (W5 (word_of_int rs2)),
                         (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (ctrl_type SAVE,[(Flag (word_of_int flagi)),
                         (W5 (word_of_int rs1)),
                         (Simm13 (word_of_int simm13)),
                         (W5 (word_of_int rd))])
     else if op3 = uint(0b111101::word6) then \<comment> \<open>\<open>RESTORE\<close>\<close>
       if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2,rd]\<close>\<close>
          Inr (ctrl_type RESTORE,[(Flag (word_of_int flagi)),
                            (W5 (word_of_int rs1)),
                            (W5 (word_of_int rs2)),
                            (W5 (word_of_int rd))])
       else \<comment> \<open>return \<open>[i,rs1,simm13,rd]\<close>\<close>
          Inr (ctrl_type RESTORE,[(Flag (word_of_int flagi)),
                            (W5 (word_of_int rs1)),
                            (Simm13 (word_of_int simm13)),
                            (W5 (word_of_int rd))])
     else if op3 = uint(0b111010::word6) then \<comment> \<open>\<open>Ticc\<close>\<close>
       let trap_cond = get_trap_cond w in
       let trap_imm7 = get_trap_imm7 w in
       if trap_cond = uint(0b1000::word4) then \<comment> \<open>\<open>TA\<close>\<close>
         if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2]\<close>\<close>
           Inr (ticc_type TA,[(Flag (word_of_int flagi)),
                    (W5 (word_of_int rs1)),
                    (W5 (word_of_int rs2))])
         else \<comment> \<open>return \<open>[i,rs1,trap_imm7]\<close>\<close>
           Inr (ticc_type TA,[(Flag (word_of_int flagi)),
                     (W5 (word_of_int rs1)),
                     (Imm7 (word_of_int trap_imm7))])
       else if trap_cond = uint(0b0000::word4) then \<comment> \<open>\<open>TN\<close>\<close>
         if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2]\<close>\<close>
           Inr (ticc_type TN,[(Flag (word_of_int flagi)),
                    (W5 (word_of_int rs1)),
                    (W5 (word_of_int rs2))])
         else \<comment> \<open>return \<open>[i,rs1,trap_imm7]\<close>\<close>
           Inr (ticc_type TN,[(Flag (word_of_int flagi)),
                     (W5 (word_of_int rs1)),
                     (Imm7 (word_of_int trap_imm7))])
       else if trap_cond = uint(0b1001::word4) then \<comment> \<open>\<open>TNE\<close>\<close>
         if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2]\<close>\<close>
           Inr (ticc_type TNE,[(Flag (word_of_int flagi)),
                    (W5 (word_of_int rs1)),
                    (W5 (word_of_int rs2))])
         else \<comment> \<open>return \<open>[i,rs1,trap_imm7]\<close>\<close>
           Inr (ticc_type TNE,[(Flag (word_of_int flagi)),
                     (W5 (word_of_int rs1)),
                     (Imm7 (word_of_int trap_imm7))])
       else if trap_cond = uint(0b0001::word4) then \<comment> \<open>\<open>TE\<close>\<close>
         if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2]\<close>\<close>
           Inr (ticc_type TE,[(Flag (word_of_int flagi)),
                    (W5 (word_of_int rs1)),
                    (W5 (word_of_int rs2))])
         else \<comment> \<open>return \<open>[i,rs1,trap_imm7]\<close>\<close>
           Inr (ticc_type TE,[(Flag (word_of_int flagi)),
                     (W5 (word_of_int rs1)),
                     (Imm7 (word_of_int trap_imm7))])
       else if trap_cond = uint(0b1010::word4) then \<comment> \<open>\<open>TG\<close>\<close>
         if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2]\<close>\<close>
           Inr (ticc_type TG,[(Flag (word_of_int flagi)),
                    (W5 (word_of_int rs1)),
                    (W5 (word_of_int rs2))])
         else \<comment> \<open>return \<open>[i,rs1,trap_imm7]\<close>\<close>
           Inr (ticc_type TG,[(Flag (word_of_int flagi)),
                     (W5 (word_of_int rs1)),
                     (Imm7 (word_of_int trap_imm7))])
       else if trap_cond = uint(0b0010::word4) then \<comment> \<open>\<open>TLE\<close>\<close>
         if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2]\<close>\<close>
           Inr (ticc_type TLE,[(Flag (word_of_int flagi)),
                    (W5 (word_of_int rs1)),
                    (W5 (word_of_int rs2))])
         else \<comment> \<open>return \<open>[i,rs1,trap_imm7]\<close>\<close>
           Inr (ticc_type TLE,[(Flag (word_of_int flagi)),
                     (W5 (word_of_int rs1)),
                     (Imm7 (word_of_int trap_imm7))])
       else if trap_cond = uint(0b1011::word4) then \<comment> \<open>\<open>TGE\<close>\<close>
         if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2]\<close>\<close>
           Inr (ticc_type TGE,[(Flag (word_of_int flagi)),
                    (W5 (word_of_int rs1)),
                    (W5 (word_of_int rs2))])
         else \<comment> \<open>return \<open>[i,rs1,trap_imm7]\<close>\<close>
           Inr (ticc_type TGE,[(Flag (word_of_int flagi)),
                     (W5 (word_of_int rs1)),
                     (Imm7 (word_of_int trap_imm7))])
       else if trap_cond = uint(0b0011::word4) then \<comment> \<open>\<open>TL\<close>\<close>
         if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2]\<close>\<close>
           Inr (ticc_type TL,[(Flag (word_of_int flagi)),
                    (W5 (word_of_int rs1)),
                    (W5 (word_of_int rs2))])
         else \<comment> \<open>return \<open>[i,rs1,trap_imm7]\<close>\<close>
           Inr (ticc_type TL,[(Flag (word_of_int flagi)),
                     (W5 (word_of_int rs1)),
                     (Imm7 (word_of_int trap_imm7))])
       else if trap_cond = uint(0b1100::word4) then \<comment> \<open>\<open>TGU\<close>\<close>
         if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2]\<close>\<close>
           Inr (ticc_type TGU,[(Flag (word_of_int flagi)),
                    (W5 (word_of_int rs1)),
                    (W5 (word_of_int rs2))])
         else \<comment> \<open>return \<open>[i,rs1,trap_imm7]\<close>\<close>
           Inr (ticc_type TGU,[(Flag (word_of_int flagi)),
                     (W5 (word_of_int rs1)),
                     (Imm7 (word_of_int trap_imm7))])
       else if trap_cond = uint(0b0100::word4) then \<comment> \<open>\<open>TLEU\<close>\<close>
         if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2]\<close>\<close>
           Inr (ticc_type TLEU,[(Flag (word_of_int flagi)),
                    (W5 (word_of_int rs1)),
                    (W5 (word_of_int rs2))])
         else \<comment> \<open>return \<open>[i,rs1,trap_imm7]\<close>\<close>
           Inr (ticc_type TLEU,[(Flag (word_of_int flagi)),
                     (W5 (word_of_int rs1)),
                     (Imm7 (word_of_int trap_imm7))])
       else if trap_cond = uint(0b1101::word4) then \<comment> \<open>\<open>TCC\<close>\<close>
         if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2]\<close>\<close>
           Inr (ticc_type TCC,[(Flag (word_of_int flagi)),
                    (W5 (word_of_int rs1)),
                    (W5 (word_of_int rs2))])
         else \<comment> \<open>return \<open>[i,rs1,trap_imm7]\<close>\<close>
           Inr (ticc_type TCC,[(Flag (word_of_int flagi)),
                     (W5 (word_of_int rs1)),
                     (Imm7 (word_of_int trap_imm7))])
       else if trap_cond = uint(0b0101::word4) then \<comment> \<open>\<open>TCS\<close>\<close>
         if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2]\<close>\<close>
           Inr (ticc_type TCS,[(Flag (word_of_int flagi)),
                    (W5 (word_of_int rs1)),
                    (W5 (word_of_int rs2))])
         else \<comment> \<open>return \<open>[i,rs1,trap_imm7]\<close>\<close>
           Inr (ticc_type TCS,[(Flag (word_of_int flagi)),
                     (W5 (word_of_int rs1)),
                     (Imm7 (word_of_int trap_imm7))])
       else if trap_cond = uint(0b1110::word4) then \<comment> \<open>\<open>TPOS\<close>\<close>
         if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2]\<close>\<close>
           Inr (ticc_type TPOS,[(Flag (word_of_int flagi)),
                    (W5 (word_of_int rs1)),
                    (W5 (word_of_int rs2))])
         else \<comment> \<open>return \<open>[i,rs1,trap_imm7]\<close>\<close>
           Inr (ticc_type TPOS,[(Flag (word_of_int flagi)),
                     (W5 (word_of_int rs1)),
                     (Imm7 (word_of_int trap_imm7))])
       else if trap_cond = uint(0b0110::word4) then \<comment> \<open>\<open>TNEG\<close>\<close>
         if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2]\<close>\<close>
           Inr (ticc_type TNEG,[(Flag (word_of_int flagi)),
                    (W5 (word_of_int rs1)),
                    (W5 (word_of_int rs2))])
         else \<comment> \<open>return \<open>[i,rs1,trap_imm7]\<close>\<close>
           Inr (ticc_type TNEG,[(Flag (word_of_int flagi)),
                     (W5 (word_of_int rs1)),
                     (Imm7 (word_of_int trap_imm7))])
       else if trap_cond = uint(0b1111::word4) then \<comment> \<open>\<open>TVC\<close>\<close>
         if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2]\<close>\<close>
           Inr (ticc_type TVC,[(Flag (word_of_int flagi)),
                    (W5 (word_of_int rs1)),
                    (W5 (word_of_int rs2))])
         else \<comment> \<open>return \<open>[i,rs1,trap_imm7]\<close>\<close>
           Inr (ticc_type TVC,[(Flag (word_of_int flagi)),
                     (W5 (word_of_int rs1)),
                     (Imm7 (word_of_int trap_imm7))])
       else if trap_cond = uint(0b0111::word4) then \<comment> \<open>\<open>TVS\<close>\<close>
         if flagi = 0 then \<comment> \<open>return \<open>[i,rs1,rs2]\<close>\<close>
           Inr (ticc_type TVS,[(Flag (word_of_int flagi)),
                    (W5 (word_of_int rs1)),
                    (W5 (word_of_int rs2))])
         else \<comment> \<open>return \<open>[i,rs1,trap_imm7]\<close>\<close>
           Inr (ticc_type TVS,[(Flag (word_of_int flagi)),
                     (W5 (word_of_int rs1)),
                     (Imm7 (word_of_int trap_imm7))])
       else Inl [invalid_trap_cond]     
     else Inl [invalid_op3_f3_op10]
   else Inl [invalid_op_f3]
 "
 
 text \<open>Read the word32 value from the Program Counter in the current state. 
         Find the instruction in the memory address of the word32 value. 
         Return a word32 value of the insturction.\<close>
 definition fetch_instruction::"('a) sparc_state \<Rightarrow>
   (Exception list + word32)"
 where "fetch_instruction s \<equiv> 
   \<comment> \<open>\<open>pc_val\<close> is the 32-bit memory address of the instruction.\<close>
   let pc_val = cpu_reg_val PC s;
       psr_val = cpu_reg_val PSR s;
       s_val = get_S psr_val;
       asi = if s_val = 0 then word_of_int 8 else word_of_int 9
   in
   \<comment> \<open>Check if \<open>pc_val\<close> is aligned to 4-byte (32-bit) boundary.\<close>
   \<comment> \<open>That is, check if the least significant two bits of\<close>
   \<comment> \<open>\<open>pc_val\<close> are 0s.\<close>
-    if uint(bitAND (0b00000000000000000000000000000011) pc_val) = 0 then
+    if uint((AND) (0b00000000000000000000000000000011) pc_val) = 0 then
     \<comment> \<open>Get the 32-bit value from the address of \<open>pc_val\<close>\<close>
     \<comment> \<open>to the address of \<open>pc_val+3\<close>\<close>
         let (mem_result,n_s) = memory_read asi pc_val s in
         case mem_result of 
          None \<Rightarrow> Inl [fetch_instruction_error]
         |Some v \<Rightarrow> Inr v
     else Inl [fetch_instruction_error]
 "
 
 text \<open>Decode the word32 value of an instruction into 
         the name of the instruction and its operands.\<close>
 definition decode_instruction::"word32 \<Rightarrow> 
   Exception list + instruction"
 where "decode_instruction w \<equiv> 
   let this_op = get_op w in 
   if this_op = uint(0b01::word2) then \<comment> \<open>Instruction format 1\<close>
     parse_instr_f1 w
   else if this_op = uint(0b00::word2) then \<comment> \<open>Instruction format 2\<close>
     parse_instr_f2 w
   else \<comment> \<open>\<open>op = 11 0r 10\<close>, instruction format 3\<close>
     parse_instr_f3 w
 "
 
 text \<open>Get the current window from the PSR\<close>
 definition get_curr_win::"unit \<Rightarrow> ('a,('a::len0 window_size)) sparc_state_monad"
 where "get_curr_win _ \<equiv> 
   do
     curr_win \<leftarrow> gets (\<lambda>s. (ucast (get_CWP (cpu_reg_val PSR s))));
     return curr_win 
   od"
 
 text \<open>Operational semantics for CALL\<close>
 definition call_instr::"instruction \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "call_instr instr \<equiv>
   let op_list = snd instr;
       mem_addr = ((ucast (get_operand_w30 (op_list!0)))::word32) << 2
   in
   do
     curr_win \<leftarrow> get_curr_win();
     pc_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PC s));
     npc_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val nPC s));
     write_reg pc_val curr_win (word_of_int 15);
     write_cpu npc_val PC;
     write_cpu (pc_val + mem_addr) nPC;
     return ()
   od"
 
 text\<open>Evaluate icc based on the bits N, Z, V, C in PSR 
        and the type of branching instruction. 
        See Sparcv8 manual Page 178.\<close>
 definition eval_icc::"sparc_operation \<Rightarrow> word1 \<Rightarrow> word1 \<Rightarrow> word1 \<Rightarrow> word1 \<Rightarrow> int"
 where
 "eval_icc instr_name n_val z_val v_val c_val \<equiv>
     if instr_name = bicc_type BNE then
       if z_val = 0 then 1 else 0
     else if instr_name = bicc_type BE then 
       if z_val = 1 then 1 else 0
     else if instr_name = bicc_type BG then
-      if (bitOR z_val (n_val XOR v_val)) = 0 then 1 else 0
+      if ((OR) z_val (n_val XOR v_val)) = 0 then 1 else 0
     else if instr_name = bicc_type BLE then
-      if (bitOR z_val (n_val XOR v_val)) = 1 then 1 else 0
+      if ((OR) z_val (n_val XOR v_val)) = 1 then 1 else 0
     else if instr_name = bicc_type BGE then
       if (n_val XOR v_val) = 0 then 1 else 0
     else if instr_name = bicc_type BL then
       if (n_val XOR v_val) = 1 then 1 else 0
     else if instr_name = bicc_type BGU then
       if (c_val = 0 \<and> z_val = 0) then 1 else 0
     else if instr_name = bicc_type BLEU then
       if (c_val = 1 \<or> z_val = 1) then 1 else 0
     else if instr_name = bicc_type BCC then
       if c_val = 0 then 1 else 0
     else if instr_name = bicc_type BCS then
       if c_val = 1 then 1 else 0
     else if instr_name = bicc_type BNEG then
       if n_val = 1 then 1 else 0
     else if instr_name = bicc_type BA then 1
     else if instr_name = bicc_type BN then 0
     else if instr_name = bicc_type BPOS then
       if n_val = 0 then 1 else 0
     else if instr_name = bicc_type BVC then
       if v_val = 0 then 1 else 0
     else if instr_name = bicc_type BVS then
       if v_val = 1 then 1 else 0
     else -1
 "
 
 definition branch_instr_sub1:: "sparc_operation \<Rightarrow> ('a) sparc_state \<Rightarrow> int"
 where "branch_instr_sub1 instr_name s \<equiv>
   let n_val = get_icc_N ((cpu_reg s) PSR);
       z_val = get_icc_Z ((cpu_reg s) PSR);
       v_val = get_icc_V ((cpu_reg s) PSR);
       c_val = get_icc_C ((cpu_reg s) PSR)
   in
   eval_icc instr_name n_val z_val v_val c_val"
 
 text \<open>Operational semantics for Branching insturctions. 
         Return exception or a bool value for annulment. 
         If the bool value is 1, then the delay instruciton 
         is not executed, otherwise the delay instruction
         is executed.\<close>
 definition branch_instr::"instruction \<Rightarrow> ('a,unit) sparc_state_monad"
 where "branch_instr instr \<equiv>
   let instr_name = fst instr;
       op_list = snd instr;
       disp22 = get_operand_w22 (op_list!1);
       flaga = get_operand_flag (op_list!0)
   in
   do
     icc_val \<leftarrow> gets( \<lambda>s. (branch_instr_sub1 instr_name s));
     npc_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val nPC s));
     pc_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PC s));
     write_cpu npc_val PC;    
     if icc_val = 1 then 
       do
         write_cpu (pc_val + (sign_ext24 (((ucast(disp22))::word24) << 2))) nPC;
         if (instr_name = bicc_type BA) \<and> (flaga = 1) then 
           do
             set_annul True;
             return ()
           od
         else
           return ()
       od
     else \<comment> \<open>\<open>icc_val = 0\<close>\<close>
       do
         write_cpu (npc_val + 4) nPC;
         if flaga = 1 then
           do                
             set_annul True;
             return ()
           od
         else return ()
       od
   od"
 
 text \<open>Operational semantics for NOP\<close>
 definition nop_instr::"instruction \<Rightarrow> ('a,unit) sparc_state_monad"
 where "nop_instr instr \<equiv> return ()"
 
 text \<open>Operational semantics for SETHI\<close>
 definition sethi_instr::"instruction \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "sethi_instr instr \<equiv>
   let op_list = snd instr;
       imm22 = get_operand_w22 (op_list!0); 
       rd = get_operand_w5 (op_list!1)
   in
   if rd \<noteq> 0 then
     do
       curr_win \<leftarrow> get_curr_win();
       write_reg (((ucast(imm22))::word32) << 10) curr_win rd;
       return ()
     od
   else return ()
 "
 
 text \<open>
   Get \<open>operand2\<close> based on the flag \<open>i\<close>, \<open>rs1\<close>, \<open>rs2\<close>, and \<open>simm13\<close>.
   If \<open>i = 0\<close> then \<open>operand2 = r[rs2]\<close>,
   else \<open>operand2 = sign_ext13(simm13)\<close>.
   \<open>op_list\<close> should be \<open>[i,rs1,rs2,\<dots>]\<close> or \<open>[i,rs1,simm13,\<dots>]\<close>.
 \<close>
 definition get_operand2::"inst_operand list \<Rightarrow> ('a::len0) sparc_state
   \<Rightarrow> virtua_address"
 where "get_operand2 op_list s \<equiv>
   let flagi = get_operand_flag (op_list!0);
       curr_win = ucast (get_CWP (cpu_reg_val PSR s))
   in
   if flagi = 0 then
     let rs2 = get_operand_w5 (op_list!2);
         rs2_val = user_reg_val curr_win rs2 s
     in rs2_val
   else
     let ext_simm13 = sign_ext13 (get_operand_simm13 (op_list!2)) in
     ext_simm13
 "
 
 text \<open>
   Get \<open>operand2_val\<close> based on the flag \<open>i\<close>, \<open>rs1\<close>, \<open>rs2\<close>, and \<open>simm13\<close>.
   If \<open>i = 0\<close> then \<open>operand2_val = uint r[rs2]\<close>,
   else \<open>operand2_val = sint sign_ext13(simm13)\<close>.
   \<open>op_list\<close> should be \<open>[i,rs1,rs2,\<dots>]\<close> or \<open>[i,rs1,simm13,\<dots>]\<close>.
 \<close>
 definition get_operand2_val::"inst_operand list \<Rightarrow> ('a::len0) sparc_state \<Rightarrow> int"
 where "get_operand2_val op_list s \<equiv>
   let flagi = get_operand_flag (op_list!0);
       curr_win = ucast (get_CWP (cpu_reg_val PSR s))
   in
   if flagi = 0 then
     let rs2 = get_operand_w5 (op_list!2);
         rs2_val = user_reg_val curr_win rs2 s
     in sint rs2_val
   else
     let ext_simm13 = sign_ext13 (get_operand_simm13 (op_list!2)) in
     sint ext_simm13
 "
 
 text \<open>
   Get the address based on the flag \<open>i\<close>, \<open>rs1\<close>, \<open>rs2\<close>, and \<open>simm13\<close>.
   If \<open>i = 0\<close> then \<open>addr = r[rs1] + r[rs2]\<close>,
   else \<open>addr = r[rs1] + sign_ext13(simm13)\<close>.
   \<open>op_list\<close> should be \<open>[i,rs1,rs2,\<dots>]\<close> or \<open>[i,rs1,simm13,\<dots>]\<close>.
 \<close>
 definition get_addr::"inst_operand list \<Rightarrow> ('a::len0) sparc_state \<Rightarrow> virtua_address"
 where "get_addr op_list s \<equiv>
   let rs1 = get_operand_w5 (op_list!1);
       curr_win = ucast (get_CWP (cpu_reg_val PSR s));
       rs1_val = user_reg_val curr_win rs1 s;
       op2 = get_operand2 op_list s
   in
   (rs1_val + op2)
 "
 
 text \<open>Operational semantics for JMPL\<close>
 definition jmpl_instr::"instruction \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "jmpl_instr instr \<equiv>
   let op_list = snd instr;
       rd = get_operand_w5 (op_list!3)      
   in
   do
     curr_win \<leftarrow> get_curr_win();
     jmp_addr \<leftarrow> gets (\<lambda>s. (get_addr op_list s));
-    if (bitAND jmp_addr 0b00000000000000000000000000000011) \<noteq> 0 then
+    if ((AND) jmp_addr 0b00000000000000000000000000000011) \<noteq> 0 then
       do
         raise_trap mem_address_not_aligned;
         return ()
       od
     else
       do
         rd_next_val \<leftarrow> gets (\<lambda>s. (if rd \<noteq> 0 then
                                     (cpu_reg_val PC s)
                                   else 
                                     user_reg_val curr_win rd s));
         write_reg rd_next_val curr_win rd;
         npc_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val nPC s));
         write_cpu npc_val PC;
         write_cpu jmp_addr nPC;
         return ()
       od
   od"
 
 text \<open>Operational semantics for RETT\<close>
 definition rett_instr :: "instruction \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "rett_instr instr \<equiv>
   let op_list = snd instr in
   do
     psr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PSR s));
     curr_win \<leftarrow> gets (\<lambda>s. (get_CWP (cpu_reg_val PSR s)));
     new_cwp \<leftarrow> gets (\<lambda>s. (word_of_int (((uint curr_win) + 1) mod NWINDOWS)));
     new_cwp_int \<leftarrow> gets (\<lambda>s. ((uint curr_win) + 1) mod NWINDOWS);
     addr \<leftarrow> gets (\<lambda>s. (get_addr op_list s));
     et_val \<leftarrow> gets (\<lambda>s. ((ucast (get_ET psr_val))::word1));
     s_val \<leftarrow> gets (\<lambda>s. ((ucast (get_S psr_val))::word1));
     ps_val \<leftarrow> gets (\<lambda>s. ((ucast (get_PS psr_val))::word1));
     wim_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val WIM s));
     npc_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val nPC s));
     if et_val = 1 then
       if s_val = 0 then 
         do
           raise_trap privileged_instruction;
           return ()
         od
       else
         do
           raise_trap illegal_instruction;
           return ()
         od
     else if s_val = 0 then
       do 
         write_cpu_tt (0b00000011::word8);
         set_exe_mode False;
         set_err_mode True;
         raise_trap privileged_instruction;
         fail ()
       od
     else if (get_WIM_bit (nat new_cwp_int) wim_val) \<noteq> 0 then
       do
         write_cpu_tt (0b00000110::word8);
         set_exe_mode False;
         set_err_mode True;
         raise_trap window_underflow;
         fail ()
       od
-    else if (bitAND addr (0b00000000000000000000000000000011::word32)) \<noteq> 0 then
+    else if ((AND) addr (0b00000000000000000000000000000011::word32)) \<noteq> 0 then
       do
         write_cpu_tt (0b00000111::word8);
         set_exe_mode False;
         set_err_mode True;
         raise_trap mem_address_not_aligned;
         fail ()
       od
     else
       do
         write_cpu npc_val PC;
         write_cpu addr nPC;
         new_psr_val \<leftarrow> gets (\<lambda>s. (update_PSR_rett new_cwp 1 ps_val psr_val));
         write_cpu new_psr_val PSR;
         return ()
       od
   od"
 
 definition save_retore_sub1 :: "word32 \<Rightarrow> word5 \<Rightarrow> word5 \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "save_retore_sub1 result new_cwp rd \<equiv>
   do
   psr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PSR s));
   new_psr_val \<leftarrow> gets (\<lambda>s. (update_CWP new_cwp psr_val));
   write_cpu new_psr_val PSR; \<comment> \<open>Change \<open>CWP\<close> to the new window value.\<close>
   write_reg result (ucast new_cwp) rd; \<comment> \<open>Write result in \<open>rd\<close> of the new window.\<close>
   return ()
   od"
 
 text \<open>Operational semantics for SAVE and RESTORE.\<close>
 definition save_restore_instr :: "instruction \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "save_restore_instr instr \<equiv>
   let instr_name = fst instr;
       op_list = snd instr;
       rd = get_operand_w5 (op_list!3)
   in
   do
     psr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PSR s));
     curr_win \<leftarrow> get_curr_win();
     wim_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val WIM s));
     if instr_name = ctrl_type SAVE then 
       do
         new_cwp \<leftarrow> gets (\<lambda>s. ((word_of_int (((uint curr_win) - 1) mod NWINDOWS)))::word5);
         if (get_WIM_bit (unat new_cwp) wim_val) \<noteq> 0 then 
           do
             raise_trap window_overflow;
             return ()
           od
         else
           do
             result \<leftarrow> gets (\<lambda>s. (get_addr op_list s)); \<comment> \<open>operands are from the old window.\<close>
             save_retore_sub1 result new_cwp rd
           od
       od
     else \<comment> \<open>\<open>instr_name = RESTORE\<close>\<close>
       do
         new_cwp \<leftarrow> gets (\<lambda>s. ((word_of_int (((uint curr_win) + 1) mod NWINDOWS)))::word5);
         if (get_WIM_bit (unat new_cwp) wim_val) \<noteq> 0 then 
           do
             raise_trap window_underflow;
             return ()
           od
         else
           do
             result \<leftarrow> gets (\<lambda>s. (get_addr op_list s)); \<comment> \<open>operands are from the old window.\<close>
             save_retore_sub1 result new_cwp rd
           od
       od
   od"
 
 definition flush_cache_line :: "word32 \<Rightarrow> ('a,unit) sparc_state_monad"
 where "flush_cache_line \<equiv> undefined"
 
 definition flush_Ibuf_and_pipeline :: "word32 \<Rightarrow> ('a,unit) sparc_state_monad"
 where "flush_Ibuf_and_pipeline \<equiv> undefined"
 
 text \<open>Operational semantics for FLUSH. 
         Flush the all the caches.\<close>
 definition flush_instr :: "instruction \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "flush_instr instr \<equiv>
   let op_list = snd instr in
   do
     addr \<leftarrow> gets (\<lambda>s. (get_addr op_list s));
     modify (\<lambda>s. (flush_cache_all s));
     \<^cancel>\<open>flush_cache_line(addr);\<close>
     \<^cancel>\<open>flush_Ibuf_and_pipeline(addr);\<close>
     return ()
   od"
 
 text \<open>Operational semantics for read state register instructions. 
         We do not consider RDASR here.\<close>
 definition read_state_reg_instr :: "instruction \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "read_state_reg_instr instr \<equiv> 
   let instr_name = fst instr;
       op_list = snd instr;
       rs1 = get_operand_w5 (op_list!0);
       rd = get_operand_w5 (op_list!1)
   in
   do  
     curr_win \<leftarrow> get_curr_win();
     psr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PSR s));
     s_val \<leftarrow> gets (\<lambda>s. (get_S psr_val));
     if (instr_name \<in> {sreg_type RDPSR,sreg_type RDWIM,sreg_type RDTBR} \<or> 
         (instr_name = sreg_type RDASR \<and> privileged_ASR rs1)) 
        \<and> ((ucast s_val)::word1) = 0 then
       do
         raise_trap privileged_instruction;
         return ()
       od
     else if illegal_instruction_ASR rs1 then 
       do
         raise_trap illegal_instruction;
         return ()
       od
     else if rd \<noteq> 0 then
       if instr_name = sreg_type RDY then
         do
           y_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val Y s));
           write_reg y_val curr_win rd;
           return ()
         od
       else if instr_name = sreg_type RDASR then
         do
           asr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val (ASR rs1) s));
           write_reg asr_val curr_win rd;
           return ()
         od
       else if instr_name = sreg_type RDPSR then
         do
           write_reg psr_val curr_win rd;
           return ()
         od
       else if instr_name = sreg_type RDWIM then
         do
           wim_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val WIM s));
           write_reg wim_val curr_win rd;
           return ()
         od
       else \<comment> \<open>Must be \<open>RDTBR\<close>.\<close>
         do
           tbr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val TBR s));
           write_reg tbr_val curr_win rd;
           return ()
         od      
     else return ()  
   od"
 
 text \<open>Operational semantics for write state register instructions. 
         We do not consider WRASR here.\<close>
 definition write_state_reg_instr :: "instruction \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "write_state_reg_instr instr \<equiv>
   let instr_name = fst instr;
       op_list = snd instr;
       rs1 = get_operand_w5 (op_list!1);
       rd = get_operand_w5 (op_list!3)
   in
   do
     curr_win \<leftarrow> get_curr_win();
     psr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PSR s));
     s_val \<leftarrow> gets (\<lambda>s. (get_S psr_val));
     op2 \<leftarrow> gets (\<lambda>s. (get_operand2 op_list s));
     rs1_val \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win rs1 s));
-    result \<leftarrow> gets (\<lambda>s. (bitXOR rs1_val op2));
+    result \<leftarrow> gets (\<lambda>s. ((XOR) rs1_val op2));
     if instr_name = sreg_type WRY then
       do
         modify (\<lambda>s. (delayed_pool_add (DELAYNUM, result, Y) s));
         return ()
       od 
     else if instr_name = sreg_type WRASR then
         if privileged_ASR rd \<and> s_val = 0 then
           do
             raise_trap privileged_instruction;
             return ()
           od
         else if illegal_instruction_ASR rd then
           do
             raise_trap illegal_instruction;
             return ()
           od
         else 
           do
             modify (\<lambda>s. (delayed_pool_add (DELAYNUM, result, (ASR rd)) s));
             return ()
           od
     else if instr_name = sreg_type WRPSR then
       if s_val = 0 then
         do
           raise_trap privileged_instruction;
           return ()
         od
       else if (uint ((ucast result)::word5)) \<ge> NWINDOWS then
         do
           raise_trap illegal_instruction;
           return ()
         od
       else 
         do \<comment> \<open>\<open>ET\<close> and \<open>PIL\<close> appear to be written IMMEDIATELY w.r.t. interrupts.\<close>
           pil_val \<leftarrow> gets (\<lambda>s. (get_PIL result));
           et_val \<leftarrow> gets (\<lambda>s. (get_ET result));
           new_psr_val \<leftarrow> gets (\<lambda>s. (update_PSR_et_pil et_val pil_val psr_val));
           write_cpu new_psr_val PSR;
           modify (\<lambda>s. (delayed_pool_add (DELAYNUM, result, PSR) s));
           return ()
         od
     else if instr_name = sreg_type WRWIM then
       if s_val = 0 then
         do
           raise_trap privileged_instruction;
           return ()
         od
       else 
         do \<comment> \<open>Don't write bits corresponding to non-existent windows.\<close>
           result_f \<leftarrow> gets (\<lambda>s. ((result << nat (32 - NWINDOWS)) >> nat (32 - NWINDOWS)));
           modify (\<lambda>s. (delayed_pool_add (DELAYNUM, result_f, WIM) s));
           return ()
         od
     else  \<comment> \<open>Must be \<open>WRTBR\<close>\<close>
       if s_val = 0 then
         do
           raise_trap privileged_instruction;
           return ()
         od
       else 
         do \<comment> \<open>Only write the bits \<open><31:12>\<close> of the result to \<open>TBR\<close>.\<close>
           tbr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val TBR s));
-          tbr_val_11_0 \<leftarrow> gets (\<lambda>s. (bitAND tbr_val 0b00000000000000000000111111111111));
-          result_tmp \<leftarrow> gets (\<lambda>s. (bitAND result 0b11111111111111111111000000000000));
-          result_f \<leftarrow> gets (\<lambda>s. (bitOR tbr_val_11_0 result_tmp));
+          tbr_val_11_0 \<leftarrow> gets (\<lambda>s. ((AND) tbr_val 0b00000000000000000000111111111111));
+          result_tmp \<leftarrow> gets (\<lambda>s. ((AND) result 0b11111111111111111111000000000000));
+          result_f \<leftarrow> gets (\<lambda>s. ((OR) tbr_val_11_0 result_tmp));
           modify (\<lambda>s. (delayed_pool_add (DELAYNUM, result_f, TBR) s));
           return ()
         od
   od"
 
 definition logical_result :: "sparc_operation \<Rightarrow> word32 \<Rightarrow> word32 \<Rightarrow> word32"
 where "logical_result instr_name rs1_val operand2 \<equiv>
   if (instr_name = logic_type ANDs) \<or> 
                             (instr_name = logic_type ANDcc) then
-                          bitAND rs1_val operand2     
+                          (AND) rs1_val operand2     
                          else if (instr_name = logic_type ANDN) \<or> 
                                  (instr_name = logic_type ANDNcc) then
-                          bitAND rs1_val (bitNOT operand2)
+                          (AND) rs1_val (NOT operand2)
                          else if (instr_name = logic_type ORs) \<or> 
                                  (instr_name = logic_type ORcc) then
-                          bitOR rs1_val operand2
+                          (OR) rs1_val operand2
                          else if instr_name \<in> {logic_type ORN,logic_type ORNcc} then 
-                          bitOR rs1_val (bitNOT operand2)
+                          (OR) rs1_val (NOT operand2)
                          else if instr_name \<in> {logic_type XORs,logic_type XORcc} then 
-                          bitXOR rs1_val operand2
+                          (XOR) rs1_val operand2
                          else \<comment> \<open>Must be \<open>XNOR\<close> or \<open>XNORcc\<close>\<close>
-                          bitXOR rs1_val (bitNOT operand2)
+                          (XOR) rs1_val (NOT operand2)
 "
 
 definition logical_new_psr_val :: "word32 \<Rightarrow> ('a) sparc_state \<Rightarrow> word32"
 where "logical_new_psr_val result s \<equiv>
   let psr_val = cpu_reg_val PSR s;
         n_val = (ucast (result >> 31))::word1;
         z_val = if (result = 0) then 1 else 0;
         v_val = 0;
         c_val = 0
   in
   update_PSR_icc n_val z_val v_val c_val psr_val
 "
 
 definition logical_instr_sub1 :: "sparc_operation \<Rightarrow> word32 \<Rightarrow> 
   ('a::len0,unit) sparc_state_monad"
 where
 "logical_instr_sub1 instr_name result \<equiv>
   if instr_name \<in> {logic_type ANDcc,logic_type ANDNcc,logic_type ORcc,
       logic_type ORNcc,logic_type XORcc,logic_type XNORcc} then
       do
         new_psr_val \<leftarrow> gets (\<lambda>s. (logical_new_psr_val result s));
         write_cpu new_psr_val PSR;
         return ()
       od
     else return () 
 "
 
 text \<open>Operational semantics for logical instructions.\<close>
 definition logical_instr :: "instruction \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "logical_instr instr \<equiv>
   let instr_name = fst instr;
       op_list = snd instr;
       rs1 = get_operand_w5 (op_list!1);
       rd = get_operand_w5 (op_list!3)
   in
   do
     operand2 \<leftarrow> gets (\<lambda>s. (get_operand2 op_list s));
     curr_win \<leftarrow> get_curr_win();
     rs1_val \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win rs1 s));
     rd_val \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win rd s));
     result \<leftarrow> gets (\<lambda>s. (logical_result instr_name rs1_val operand2));
     new_rd_val \<leftarrow> gets (\<lambda>s. (if rd \<noteq> 0 then result else rd_val));
     write_reg new_rd_val curr_win rd;
     logical_instr_sub1 instr_name result
   od"
 
 text \<open>Operational semantics for shift instructions.\<close>
 definition shift_instr :: "instruction \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "shift_instr instr \<equiv>
   let instr_name = fst instr;
       op_list = snd instr;
       flagi = get_operand_flag (op_list!0);
       rs1 = get_operand_w5 (op_list!1);
       rs2_shcnt = get_operand_w5 (op_list!2);
       rd = get_operand_w5 (op_list!3)
   in
   do
     curr_win \<leftarrow> get_curr_win();
     shift_count \<leftarrow> gets (\<lambda>s. (if flagi = 0 then 
                                 ucast (user_reg_val curr_win rs2_shcnt s) 
                               else rs2_shcnt));
     rs1_val \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win rs1 s));
     if (instr_name = shift_type SLL) \<and> (rd \<noteq> 0) then 
       do
         rd_val \<leftarrow> gets (\<lambda>s. (rs1_val << (unat shift_count)));
         write_reg rd_val curr_win rd;
         return ()
       od
     else if (instr_name = shift_type SRL) \<and> (rd \<noteq> 0) then
       do
         rd_val \<leftarrow> gets (\<lambda>s. (rs1_val >> (unat shift_count)));
         write_reg rd_val curr_win rd;
         return ()
       od
     else if (instr_name = shift_type SRA) \<and> (rd \<noteq> 0) then
       do
         rd_val \<leftarrow> gets (\<lambda>s. (rs1_val >>> (unat shift_count)));
         write_reg rd_val curr_win rd;
         return ()
       od
     else return ()
   od"
 
 definition add_instr_sub1 :: "sparc_operation \<Rightarrow> word32 \<Rightarrow> word32 \<Rightarrow> word32
   \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "add_instr_sub1 instr_name result rs1_val operand2 \<equiv>
   if instr_name \<in> {arith_type ADDcc,arith_type ADDXcc} then
       do
         psr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PSR s));
         result_31 \<leftarrow> gets (\<lambda>s. ((ucast (result >> 31))::word1));
         rs1_val_31 \<leftarrow> gets (\<lambda>s. ((ucast (rs1_val >> 31))::word1));
         operand2_31 \<leftarrow> gets (\<lambda>s. ((ucast (operand2 >> 31))::word1));
         new_n_val \<leftarrow> gets (\<lambda>s. (result_31));
         new_z_val \<leftarrow> gets (\<lambda>s. (if result = 0 then 1::word1 else 0::word1));
-        new_v_val \<leftarrow> gets (\<lambda>s. (bitOR (bitAND rs1_val_31 
-                                              (bitAND operand2_31 
-                                                      (bitNOT result_31))) 
-                                      (bitAND (bitNOT rs1_val_31) 
-                                              (bitAND (bitNOT operand2_31) 
+        new_v_val \<leftarrow> gets (\<lambda>s. ((OR) ((AND) rs1_val_31 
+                                              ((AND) operand2_31 
+                                                      (NOT result_31))) 
+                                      ((AND) (NOT rs1_val_31) 
+                                              ((AND) (NOT operand2_31) 
                                                       result_31))));
-        new_c_val \<leftarrow> gets (\<lambda>s. (bitOR (bitAND rs1_val_31 
+        new_c_val \<leftarrow> gets (\<lambda>s. ((OR) ((AND) rs1_val_31 
                                               operand2_31) 
-                                      (bitAND (bitNOT result_31) 
-                                              (bitOR rs1_val_31 
+                                      ((AND) (NOT result_31) 
+                                              ((OR) rs1_val_31 
                                                      operand2_31))));
         new_psr_val \<leftarrow> gets (\<lambda>s. (update_PSR_icc new_n_val 
                                                  new_z_val 
                                                  new_v_val 
                                                  new_c_val psr_val));
         write_cpu new_psr_val PSR;
         return ()
       od
     else return ()
 "
 
 text \<open>Operational semantics for add instructions. 
         These include ADD, ADDcc, ADDX.\<close>
 definition add_instr :: "instruction \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "add_instr instr \<equiv>
   let instr_name = fst instr;
       op_list = snd instr;
       rs1 = get_operand_w5 (op_list!1);
       rd = get_operand_w5 (op_list!3)
   in
   do
     operand2 \<leftarrow> gets (\<lambda>s. (get_operand2 op_list s));
     curr_win \<leftarrow> get_curr_win();
     rs1_val \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win rs1 s));
     psr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PSR s));
     c_val \<leftarrow> gets (\<lambda>s. (get_icc_C psr_val));
     result \<leftarrow> gets (\<lambda>s. (if (instr_name = arith_type ADD) \<or> 
                             (instr_name = arith_type ADDcc) then
                           rs1_val + operand2
                          else \<comment> \<open>Must be \<open>ADDX\<close> or \<open>ADDXcc\<close>\<close>
                           rs1_val + operand2 + (ucast c_val)));
     rd_val \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win rd s));
     new_rd_val \<leftarrow> gets (\<lambda>s. (if rd \<noteq> 0 then result else rd_val));
     write_reg new_rd_val curr_win rd;
     add_instr_sub1 instr_name result rs1_val operand2
   od"
 
 definition sub_instr_sub1 :: "sparc_operation \<Rightarrow> word32 \<Rightarrow> word32 \<Rightarrow> word32
   \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "sub_instr_sub1 instr_name result rs1_val operand2 \<equiv>
   if instr_name \<in> {arith_type SUBcc,arith_type SUBXcc} then
       do
         psr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PSR s));
         result_31 \<leftarrow> gets (\<lambda>s. ((ucast (result >> 31))::word1));
         rs1_val_31 \<leftarrow> gets (\<lambda>s. ((ucast (rs1_val >> 31))::word1));
         operand2_31 \<leftarrow> gets (\<lambda>s. ((ucast (operand2 >> 31))::word1));
         new_n_val \<leftarrow> gets (\<lambda>s. (result_31));
         new_z_val \<leftarrow> gets (\<lambda>s. (if result = 0 then 1::word1 else 0::word1));
-        new_v_val \<leftarrow> gets (\<lambda>s. (bitOR (bitAND rs1_val_31 
-                                              (bitAND (bitNOT operand2_31) 
-                                                      (bitNOT result_31))) 
-                                      (bitAND (bitNOT rs1_val_31) 
-                                              (bitAND operand2_31 
+        new_v_val \<leftarrow> gets (\<lambda>s. ((OR) ((AND) rs1_val_31 
+                                              ((AND) (NOT operand2_31) 
+                                                      (NOT result_31))) 
+                                      ((AND) (NOT rs1_val_31) 
+                                              ((AND) operand2_31 
                                                       result_31))));
-        new_c_val \<leftarrow> gets (\<lambda>s. (bitOR (bitAND (bitNOT rs1_val_31) 
+        new_c_val \<leftarrow> gets (\<lambda>s. ((OR) ((AND) (NOT rs1_val_31) 
                                               operand2_31) 
-                                      (bitAND result_31 
-                                              (bitOR (bitNOT rs1_val_31) 
+                                      ((AND) result_31 
+                                              ((OR) (NOT rs1_val_31) 
                                                      operand2_31))));
         new_psr_val \<leftarrow> gets (\<lambda>s. (update_PSR_icc new_n_val 
                                                  new_z_val 
                                                  new_v_val 
                                                  new_c_val psr_val));
         write_cpu new_psr_val PSR;
         return ()
       od
     else return ()
 "
 
 text \<open>Operational semantics for subtract instructions. 
         These include SUB, SUBcc, SUBX.\<close>
 definition sub_instr :: "instruction \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "sub_instr instr \<equiv>
   let instr_name = fst instr;
       op_list = snd instr;
       rs1 = get_operand_w5 (op_list!1);
       rd = get_operand_w5 (op_list!3)
   in
   do
     operand2 \<leftarrow> gets (\<lambda>s. (get_operand2 op_list s));
     curr_win \<leftarrow> get_curr_win();
     rs1_val \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win rs1 s));
     psr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PSR s));
     c_val \<leftarrow> gets (\<lambda>s. (get_icc_C psr_val));
     result \<leftarrow> gets (\<lambda>s. (if (instr_name = arith_type SUB) \<or> 
                             (instr_name = arith_type SUBcc) then
                           rs1_val - operand2
                          else \<comment> \<open>Must be \<open>SUBX\<close> or \<open>SUBXcc\<close>\<close>
                           rs1_val - operand2 - (ucast c_val)));
     rd_val \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win rd s));
     new_rd_val \<leftarrow> gets (\<lambda>s. (if rd \<noteq> 0 then result else rd_val));
     write_reg new_rd_val curr_win rd;
     sub_instr_sub1 instr_name result rs1_val operand2
   od"
 
 definition mul_instr_sub1 :: "sparc_operation \<Rightarrow> word32 \<Rightarrow> 
   ('a::len0,unit) sparc_state_monad"
 where "mul_instr_sub1 instr_name result \<equiv>
   if instr_name \<in> {arith_type SMULcc,arith_type UMULcc} then
       do
         psr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PSR s));
         new_n_val \<leftarrow> gets (\<lambda>s. ((ucast (result >> 31))::word1));
         new_z_val \<leftarrow> gets (\<lambda>s. (if result = 0 then 1 else 0));
         new_v_val \<leftarrow> gets (\<lambda>s. 0);
         new_c_val \<leftarrow> gets (\<lambda>s. 0);
         new_psr_val \<leftarrow> gets (\<lambda>s. (update_PSR_icc new_n_val 
                                                  new_z_val 
                                                  new_v_val 
                                                  new_c_val psr_val));
         write_cpu new_psr_val PSR;
         return ()
       od
     else return ()
 "
 
 text \<open>Operational semantics for multiply instructions.\<close>
 definition mul_instr :: "instruction \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "mul_instr instr \<equiv>
   let instr_name = fst instr;
       op_list = snd instr;
       rs1 = get_operand_w5 (op_list!1);
       rd = get_operand_w5 (op_list!3)
   in
   do
     operand2 \<leftarrow> gets (\<lambda>s. (get_operand2 op_list s));
     curr_win \<leftarrow> get_curr_win();
     rs1_val \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win rs1 s));
     psr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PSR s));
     result0 \<leftarrow> gets (\<lambda>s. (if instr_name \<in> {arith_type UMUL,arith_type UMULcc} then 
                             (word_of_int ((uint rs1_val) * 
                                           (uint operand2)))::word64
                           else \<comment> \<open>Must be \<open>SMUL\<close> or \<open>SMULcc\<close>\<close>
                             (word_of_int ((sint rs1_val) * 
                                           (sint operand2)))::word64));
     \<comment> \<open>whether to use \<open>ucast\<close> or \<open>scast\<close> does not matter below.\<close>
     y_val \<leftarrow> gets (\<lambda>s. ((ucast (result0 >> 32))::word32));
     write_cpu y_val Y;
     result \<leftarrow> gets (\<lambda>s. ((ucast result0)::word32));
     rd_val \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win rd s));
     new_rd_val \<leftarrow> gets (\<lambda>s. (if rd \<noteq> 0 then result else rd_val));
     write_reg new_rd_val curr_win rd;
     mul_instr_sub1 instr_name result
   od"
 
 definition div_comp_temp_64bit :: "instruction \<Rightarrow> word64 \<Rightarrow> 
   virtua_address \<Rightarrow> word64"
 where "div_comp_temp_64bit i y_rs1 operand2 \<equiv> 
   if ((fst i) = arith_type UDIV) \<or> ((fst i) = arith_type UDIVcc) then 
     (word_of_int ((uint y_rs1) div (uint operand2)))::word64
   else \<comment> \<open>Must be \<open>SDIV\<close> or \<open>SDIVcc\<close>.\<close>
     \<comment> \<open>Due to Isabelle's rounding method is not nearest to zero,\<close>
     \<comment> \<open>we have to implement division in a different way.\<close>
     let sop1 = sint y_rs1;
         sop2 = sint operand2;
         pop1 = abs sop1;
         pop2 = abs sop2
     in
     if sop1 > 0 \<and> sop2 > 0 then 
       (word_of_int (sop1 div sop2))
     else if sop1 > 0 \<and> sop2 < 0 then
       (word_of_int (- (sop1 div pop2)))
     else if sop1 < 0 \<and> sop2 > 0 then
       (word_of_int (- (pop1 div sop2)))
     else \<comment> \<open>\<open>sop1 < 0 \<and> sop2 < 0\<close>\<close>
       (word_of_int (pop1 div pop2))"
 
 definition div_comp_temp_V :: "instruction \<Rightarrow> word32 \<Rightarrow> word33 \<Rightarrow> word1"
 where "div_comp_temp_V i w32 w33 \<equiv> 
   if ((fst i) = arith_type UDIV) \<or> ((fst i) = arith_type UDIVcc) then
     if w32 = 0 then 0 else 1
   else \<comment> \<open>Must be \<open>SDIV\<close> or \<open>SDIVcc\<close>.\<close>
     if (w33 = 0) \<or> (w33 = (0b111111111111111111111111111111111::word33)) 
     then 0 else 1"
 
 definition div_comp_result :: "instruction \<Rightarrow> word1 \<Rightarrow> word64 \<Rightarrow> word32"
 where "div_comp_result i temp_V temp_64bit \<equiv>
   if temp_V = 1 then
     if ((fst i) = arith_type UDIV) \<or> ((fst i) = arith_type UDIVcc) then
       (0b11111111111111111111111111111111::word32)
     else if (fst i) \<in> {arith_type SDIV,arith_type SDIVcc} then  
       if temp_64bit > 0 then 
         (0b01111111111111111111111111111111::word32)
       else ((word_of_int (0 - (uint (0b10000000000000000000000000000000::word32))))::word32)
     else ((ucast temp_64bit)::word32)
   else ((ucast temp_64bit)::word32)"
 
 definition div_write_new_val :: "instruction \<Rightarrow> word32 \<Rightarrow> word1 \<Rightarrow> 
   ('a::len0,unit) sparc_state_monad"
 where "div_write_new_val i result temp_V \<equiv>
   if (fst i) \<in> {arith_type UDIVcc,arith_type SDIVcc} then
   do
     psr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PSR s));
     new_n_val \<leftarrow> gets (\<lambda>s. ((ucast (result >> 31))::word1));
     new_z_val \<leftarrow> gets (\<lambda>s. (if result = 0 then 1 else 0));
     new_v_val \<leftarrow> gets (\<lambda>s. temp_V);
     new_c_val \<leftarrow> gets (\<lambda>s. 0);
     new_psr_val \<leftarrow> gets (\<lambda>s. (update_PSR_icc new_n_val 
                                              new_z_val 
                                              new_v_val 
                                              new_c_val psr_val));
     write_cpu new_psr_val PSR;
     return ()
   od
   else return ()"
 
 definition div_comp :: "instruction \<Rightarrow> word5 \<Rightarrow> word5 \<Rightarrow> virtua_address \<Rightarrow>
   ('a::len0,unit) sparc_state_monad"
 where "div_comp instr rs1 rd operand2 \<equiv>
   do
     curr_win \<leftarrow> get_curr_win();
     rs1_val \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win rs1 s));
     
     y_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val Y s));
     y_rs1 \<leftarrow> gets (\<lambda>s. ((word_cat y_val rs1_val)::word64));
     temp_64bit \<leftarrow> gets (\<lambda>s. (div_comp_temp_64bit instr y_rs1 operand2));
     \<^cancel>\<open>result \<leftarrow>  gets (\<lambda>s. ((ucast temp_64bit)::word32));\<close>
     temp_high32 \<leftarrow> gets (\<lambda>s. ((ucast (temp_64bit >> 32))::word32));
     temp_high33 \<leftarrow> gets (\<lambda>s. ((ucast (temp_64bit >> 31))::word33));
     temp_V \<leftarrow> gets (\<lambda>s. (div_comp_temp_V instr temp_high32 temp_high33));
     result \<leftarrow> gets (\<lambda>s. (div_comp_result instr temp_V temp_64bit));
     rd_val \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win rd s));
     new_rd_val \<leftarrow> gets (\<lambda>s. (if rd \<noteq> 0 then result else rd_val));
     write_reg new_rd_val curr_win rd;
     div_write_new_val instr result temp_V 
   od"
 
 text \<open>Operational semantics for divide instructions.\<close>
 definition div_instr :: "instruction \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "div_instr instr \<equiv>
   let instr_name = fst instr;
       op_list = snd instr;
       rs1 = get_operand_w5 (op_list!1);
       rd = get_operand_w5 (op_list!3)
   in
   do
     operand2 \<leftarrow> gets (\<lambda>s. (get_operand2 op_list s));
     if (uint operand2) = 0 then 
       do
         raise_trap division_by_zero;
         return ()
       od
     else
       div_comp instr rs1 rd operand2
   od"
 
 definition ld_word0 :: "instruction \<Rightarrow> word32 \<Rightarrow> virtua_address \<Rightarrow>  word32"
 where "ld_word0 instr data_word address \<equiv>
   if (fst instr) \<in> {load_store_type LDSB,load_store_type LDUB,
     load_store_type LDUBA,load_store_type LDSBA} then                                     
     let byte = if (uint ((ucast address)::word2)) = 0 then
                  (ucast (data_word >> 24))::word8
                else if (uint ((ucast address)::word2)) = 1 then
                  (ucast (data_word >> 16))::word8
                else if (uint ((ucast address)::word2)) = 2 then
                  (ucast (data_word >> 8))::word8
                else \<comment> \<open>Must be 3.\<close>
                  (ucast data_word)::word8
     in
     if (fst instr) = load_store_type LDSB \<or> (fst instr) = load_store_type LDSBA then
       sign_ext8 byte
     else 
       zero_ext8 byte
   else if (fst instr) = load_store_type LDUH \<or> (fst instr) = load_store_type LDSH \<or> 
           (fst instr) = load_store_type LDSHA \<or> (fst instr) = load_store_type LDUHA
        then  
     let halfword = if (uint ((ucast address)::word2)) = 0 then
                      (ucast (data_word >> 16))::word16
                    else \<comment> \<open>Must be 2.\<close>
                      (ucast data_word)::word16
     in
     if (fst instr) = load_store_type LDSH \<or> (fst instr) = load_store_type LDSHA then
       sign_ext16 halfword
     else
       zero_ext16 halfword
   else \<comment> \<open>Must be LDD\<close>
     data_word
 "
 
 definition ld_asi :: "instruction \<Rightarrow> word1 \<Rightarrow> asi_type"
 where "ld_asi instr s_val \<equiv>
   if (fst instr) \<in> {load_store_type LDD,load_store_type LD,load_store_type LDUH,
     load_store_type LDSB,load_store_type LDUB,load_store_type LDSH} then
     if s_val = 0 then (word_of_int 10)::asi_type
     else (word_of_int 11)::asi_type
   else \<comment> \<open>Must be \<open>LDA\<close>, \<open>LDUBA\<close>, \<open>LDSBA\<close>, \<open>LDSHA\<close>, \<open>LDUHA\<close>, or \<open>LDDA\<close>.\<close>
     get_operand_asi ((snd instr)!3)
 "
 
 definition load_sub2 :: "virtua_address \<Rightarrow> asi_type \<Rightarrow> word5 \<Rightarrow> 
   ('a::len0) window_size \<Rightarrow> word32 \<Rightarrow> ('a,unit) sparc_state_monad"
 where "load_sub2 address asi rd curr_win word0 \<equiv>
   do
-    write_reg word0 curr_win (bitAND rd 0b11110);
+    write_reg word0 curr_win ((AND) rd 0b11110);
     (result1,new_state1) \<leftarrow> gets (\<lambda>s. (memory_read asi (address + 4) s));
     if result1 = None then
     do
       raise_trap data_access_exception;
       return ()
     od
     else
     do
       word1 \<leftarrow> gets (\<lambda>s. (case result1 of Some v \<Rightarrow> v));
       modify (\<lambda>s. (new_state1));
-      write_reg word1 curr_win (bitOR rd 1);
+      write_reg word1 curr_win ((OR) rd 1);
       return ()                                       
     od
   od"
 
 definition load_sub3 :: "instruction \<Rightarrow> ('a::len0) window_size \<Rightarrow>
   word5 \<Rightarrow> asi_type \<Rightarrow> virtua_address \<Rightarrow>
   ('a::len0,unit) sparc_state_monad"
 where "load_sub3 instr curr_win rd asi address \<equiv>
   do
     (result,new_state) \<leftarrow> gets (\<lambda>s. (memory_read asi address s));
     if result = None then
     do
       raise_trap data_access_exception;
       return ()
     od
     else
     do
       data_word \<leftarrow> gets (\<lambda>s. (case result of Some v \<Rightarrow> v));
       modify (\<lambda>s. (new_state));
       word0 \<leftarrow> gets (\<lambda>s. (ld_word0 instr data_word address));
       if rd \<noteq> 0 \<and> (fst instr) \<in> {load_store_type LD,load_store_type LDA,
         load_store_type LDUH,load_store_type LDSB,load_store_type LDUB,
         load_store_type LDUBA,load_store_type LDSH,load_store_type LDSHA,
         load_store_type LDUHA,load_store_type LDSBA} then
       do
         write_reg word0 curr_win rd;
         return ()
       od
       else \<comment> \<open>Must be \<open>LDD\<close> or \<open>LDDA\<close>\<close>
         load_sub2 address asi rd curr_win word0
     od
   od"
 
 definition load_sub1 :: "instruction \<Rightarrow> word5 \<Rightarrow> word1 \<Rightarrow>
   ('a::len0,unit) sparc_state_monad"
 where "load_sub1 instr rd s_val \<equiv>
   do
     curr_win \<leftarrow> get_curr_win();
     address \<leftarrow> gets (\<lambda>s. (get_addr (snd instr) s));
     asi \<leftarrow> gets (\<lambda>s. (ld_asi instr s_val));
     if (((fst instr) = load_store_type LDD \<or> (fst instr) = load_store_type LDDA) 
        \<and> ((ucast address)::word3) \<noteq> 0) 
          \<or> ((fst instr) \<in> {load_store_type LD,load_store_type LDA} 
             \<and> ((ucast address)::word2) \<noteq> 0)
          \<or> (((fst instr) = load_store_type LDUH \<or> (fst instr) = load_store_type LDUHA 
              \<or> (fst instr) = load_store_type LDSH \<or> (fst instr) = load_store_type LDSHA) 
             \<and> ((ucast address)::word1) \<noteq> 0)
     then
     do
       raise_trap mem_address_not_aligned;
       return ()
     od
     else
       load_sub3 instr curr_win rd asi address
   od"
 
 text \<open>Operational semantics for Load instructions.\<close>
 definition load_instr :: "instruction \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "load_instr instr \<equiv>
   let instr_name = fst instr;
       op_list = snd instr;
       flagi = get_operand_flag (op_list!0);
       rd = if instr_name \<in> {load_store_type LDUBA,load_store_type LDA,
         load_store_type LDSBA,load_store_type LDSHA,
         load_store_type LDSHA,load_store_type LDDA} then \<comment> \<open>\<open>rd\<close> is member 4\<close>
             get_operand_w5 (op_list!4)
            else \<comment> \<open>\<open>rd\<close> is member 3\<close>
             get_operand_w5 (op_list!3)
   in  
   do
     psr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PSR s));
     s_val \<leftarrow> gets (\<lambda>s. (get_S psr_val));
     if instr_name \<in> {load_store_type LDA,load_store_type LDUBA,
       load_store_type LDSBA,load_store_type LDSHA,
       load_store_type LDUHA,load_store_type LDDA} \<and> s_val = 0 then 
       do
         raise_trap privileged_instruction;
         return ()
       od
     else if instr_name \<in> {load_store_type LDA,load_store_type LDUBA,
       load_store_type LDSBA,load_store_type LDSHA,load_store_type LDUHA,
       load_store_type LDDA} \<and> flagi = 1 then
       do
         raise_trap illegal_instruction;
         return ()
       od
     else
       load_sub1 instr rd s_val        
   od"
 
 definition st_asi :: "instruction \<Rightarrow> word1 \<Rightarrow> asi_type"
 where "st_asi instr s_val \<equiv>
   if (fst instr) \<in> {load_store_type STD,load_store_type ST,
     load_store_type STH,load_store_type STB} then
     if s_val = 0 then (word_of_int 10)::asi_type
     else (word_of_int 11)::asi_type
   else \<comment> \<open>Must be \<open>STA\<close>, \<open>STBA\<close>, \<open>STHA\<close>, \<open>STDA\<close>.\<close>
     get_operand_asi ((snd instr)!3)
 "
 
 definition st_byte_mask :: "instruction \<Rightarrow> virtua_address \<Rightarrow> word4"
 where "st_byte_mask instr address \<equiv>
   if (fst instr) \<in> {load_store_type STD,load_store_type ST,
     load_store_type STA,load_store_type STDA} then 
     (0b1111::word4)
   else if (fst instr) \<in> {load_store_type STH,load_store_type STHA} then
     if ((ucast address)::word2) = 0 then
       (0b1100::word4)
     else \<comment> \<open>Must be 2.\<close>
       (0b0011::word4)
   else \<comment> \<open>Must be \<open>STB\<close> or \<open>STBA\<close>.\<close>
     if ((ucast address)::word2) = 0 then 
       (0b1000::word4)
     else if ((ucast address)::word2) = 1 then 
       (0b0100::word4)
     else if ((ucast address)::word2) = 2 then 
       (0b0010::word4)
     else \<comment> \<open>Must be 3.\<close>
       (0b0001::word4)
 "
 
 definition st_data0 :: "instruction \<Rightarrow> ('a::len0) window_size \<Rightarrow> 
   word5 \<Rightarrow> virtua_address \<Rightarrow> ('a) sparc_state \<Rightarrow> reg_type"
 where "st_data0 instr curr_win rd address s \<equiv>
   if (fst instr) \<in> {load_store_type STD,load_store_type STDA} then 
-    user_reg_val curr_win (bitAND rd 0b11110) s
+    user_reg_val curr_win ((AND) rd 0b11110) s
   else if (fst instr) \<in> {load_store_type ST,load_store_type STA} then 
     user_reg_val curr_win rd s
   else if (fst instr) \<in> {load_store_type STH,load_store_type STHA} then
     if ((ucast address)::word2) = 0 then 
       (user_reg_val curr_win rd s) << 16
     else \<comment> \<open>Must be 2.\<close>
       user_reg_val curr_win rd s
   else \<comment> \<open>Must be \<open>STB\<close> or \<open>STBA\<close>.\<close>
     if ((ucast address)::word2) = 0 then 
        (user_reg_val curr_win rd s) << 24
     else if ((ucast address)::word2) = 1 then
        (user_reg_val curr_win rd s) << 16
     else if ((ucast address)::word2) = 2 then
         (user_reg_val curr_win rd s) << 8
     else \<comment> \<open>Must be 3.\<close>
         user_reg_val curr_win rd s
 "
 
 definition store_sub2 :: "instruction \<Rightarrow> ('a::len0) window_size \<Rightarrow>
   word5 \<Rightarrow> asi_type \<Rightarrow> virtua_address \<Rightarrow> 
   ('a::len0,unit) sparc_state_monad"
 where "store_sub2 instr curr_win rd asi address \<equiv>
   do
     byte_mask \<leftarrow> gets (\<lambda>s. (st_byte_mask instr address));
     data0 \<leftarrow> gets (\<lambda>s. (st_data0 instr curr_win rd address s));
     result0 \<leftarrow> gets (\<lambda>s. (memory_write asi address byte_mask data0 s));
     if result0 = None then
     do
       raise_trap data_access_exception;
       return ()
     od
     else 
     do
       new_state \<leftarrow> gets (\<lambda>s. (case result0 of Some v \<Rightarrow> v));
       modify (\<lambda>s. (new_state));
       if (fst instr) \<in> {load_store_type STD,load_store_type STDA} then  
       do
-        data1 \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win (bitOR rd 0b00001) s));
+        data1 \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win ((OR) rd 0b00001) s));
         result1 \<leftarrow> gets (\<lambda>s. (memory_write asi (address + 4) (0b1111::word4) data1 s));
         if result1 = None then
         do
           raise_trap data_access_exception;
           return ()
         od
         else 
           do
           new_state1 \<leftarrow> gets (\<lambda>s. (case result1 of Some v \<Rightarrow> v));
           modify (\<lambda>s. (new_state1));
           return ()
           od
       od
       else
         return ()
     od
   od"
 
 definition store_sub1 :: "instruction \<Rightarrow> word5 \<Rightarrow> word1 \<Rightarrow> 
   ('a::len0,unit) sparc_state_monad"
 where "store_sub1 instr rd s_val \<equiv>
   do
     curr_win \<leftarrow> get_curr_win();
     address \<leftarrow> gets (\<lambda>s. (get_addr (snd instr) s));
     asi \<leftarrow> gets (\<lambda>s. (st_asi instr s_val));
     \<comment> \<open>The following code is intentionally long to match the definitions in SPARCv8.\<close>
     if ((fst instr) = load_store_type STH \<or> (fst instr) = load_store_type STHA) 
        \<and> ((ucast address)::word1) \<noteq> 0 then
     do  
       raise_trap mem_address_not_aligned;
       return ()
     od
     else if (fst instr) \<in> {load_store_type ST,load_store_type STA} 
             \<and> ((ucast address)::word2) \<noteq> 0 then
     do  
       raise_trap mem_address_not_aligned;
       return ()
     od
     else if (fst instr) \<in> {load_store_type STD,load_store_type STDA} 
             \<and> ((ucast address)::word3) \<noteq> 0 then
     do  
       raise_trap mem_address_not_aligned;
       return ()
     od
     else 
       store_sub2 instr curr_win rd asi address
   od"
 
 text \<open>Operational semantics for Store instructions.\<close>
 definition store_instr :: "instruction \<Rightarrow> 
   ('a::len0,unit) sparc_state_monad"
 where "store_instr instr \<equiv>
   let instr_name = fst instr;
       op_list = snd instr;
       flagi = get_operand_flag (op_list!0);
       rd = if instr_name \<in> {load_store_type STA,load_store_type STBA,
             load_store_type STHA,load_store_type STDA} then \<comment> \<open>\<open>rd\<close> is member 4\<close>
             get_operand_w5 (op_list!4)
            else \<comment> \<open>\<open>rd\<close> is member 3\<close>
             get_operand_w5 (op_list!3)
   in
   do   
     psr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PSR s));
     s_val \<leftarrow> gets (\<lambda>s. (get_S psr_val));
     if instr_name \<in> {load_store_type STA,load_store_type STDA,
       load_store_type STHA,load_store_type STBA} \<and> s_val = 0 then
       do
         raise_trap privileged_instruction;
         return ()
       od
     else if instr_name \<in> {load_store_type STA,load_store_type STDA,
       load_store_type STHA,load_store_type STBA} \<and> flagi = 1 then
       do
         raise_trap illegal_instruction;
         return ()
       od
     else
       store_sub1 instr rd s_val
   od"
 
 text \<open>The instructions below are not used by Xtratum and they are 
   not tested.\<close>
 
 definition ldst_asi :: "instruction \<Rightarrow> word1 \<Rightarrow> asi_type"
 where "ldst_asi instr s_val \<equiv>
   if (fst instr) \<in> {load_store_type LDSTUB} then
     if s_val = 0 then (word_of_int 10)::asi_type
     else (word_of_int 11)::asi_type
   else \<comment> \<open>Must be \<open>LDSTUBA\<close>.\<close>
     get_operand_asi ((snd instr)!3)
 "
 
 definition ldst_word0 :: "instruction \<Rightarrow> word32 \<Rightarrow> virtua_address \<Rightarrow>  word32"
 where "ldst_word0 instr data_word address \<equiv>                                 
   let byte = if (uint ((ucast address)::word2)) = 0 then
                  (ucast (data_word >> 24))::word8
                else if (uint ((ucast address)::word2)) = 1 then
                  (ucast (data_word >> 16))::word8
                else if (uint ((ucast address)::word2)) = 2 then
                  (ucast (data_word >> 8))::word8
                else \<comment> \<open>Must be 3.\<close>
                  (ucast data_word)::word8
   in
   zero_ext8 byte
 "
 
 definition ldst_byte_mask :: "instruction \<Rightarrow> virtua_address \<Rightarrow> word4"
 where "ldst_byte_mask instr address \<equiv>
     if ((ucast address)::word2) = 0 then 
       (0b1000::word4)
     else if ((ucast address)::word2) = 1 then 
       (0b0100::word4)
     else if ((ucast address)::word2) = 2 then 
       (0b0010::word4)
     else \<comment> \<open>Must be 3.\<close>
       (0b0001::word4)
 "
 
 definition load_store_sub1 :: "instruction \<Rightarrow> word5 \<Rightarrow> word1 \<Rightarrow>
   ('a::len0,unit) sparc_state_monad"
 where "load_store_sub1 instr rd s_val \<equiv>
   do
     curr_win \<leftarrow> get_curr_win();
     address \<leftarrow> gets (\<lambda>s. (get_addr (snd instr) s));
     asi \<leftarrow> gets (\<lambda>s. (ldst_asi instr s_val));
     \<comment> \<open>wait for locks to be lifted.\<close>
     \<comment> \<open>an implementation actually need only block when another \<open>LDSTUB\<close> or \<open>SWAP\<close>\<close>
     \<comment> \<open>is pending on the same byte in memory as the one addressed by this \<open>LDSTUB\<close>\<close>
     \<comment> \<open>Should wait when \<open>block_type = 1 \<or> block_word = 1\<close>\<close>
     \<comment> \<open>until another processes write both to be 0.\<close>
     \<comment> \<open>We implement this as setting \<open>pc\<close> as \<open>npc\<close> when the instruction\<close>
     \<comment> \<open>is blocked. This way, in the next iteration, we will still execution\<close>
     \<comment> \<open>the current instruction.\<close>
     block_byte \<leftarrow> gets (\<lambda>s. (pb_block_ldst_byte_val address s));
     block_word \<leftarrow> gets (\<lambda>s. (pb_block_ldst_word_val address s));
     if block_byte \<or> block_word then 
     do
       pc_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PC s));
       write_cpu pc_val nPC;
       return ()
     od  
     else 
     do
       modify (\<lambda>s. (pb_block_ldst_byte_mod address True s));
       (result,new_state) \<leftarrow> gets (\<lambda>s. (memory_read asi address s));
       if result = None then
       do
         raise_trap data_access_exception;
         return ()
       od
       else
       do
         data_word \<leftarrow> gets (\<lambda>s. (case result of Some v \<Rightarrow> v));
         modify (\<lambda>s. (new_state));
         byte_mask \<leftarrow> gets (\<lambda>s. (ldst_byte_mask instr address));
         data0 \<leftarrow> gets (\<lambda>s. (0b11111111111111111111111111111111::word32));
         result0 \<leftarrow> gets (\<lambda>s. (memory_write asi address byte_mask data0 s));  
         modify (\<lambda>s. (pb_block_ldst_byte_mod address False s));
         if result0 = None then
         do
           raise_trap data_access_exception;
           return ()
         od
         else
         do
           new_state1 \<leftarrow> gets (\<lambda>s. (case result0 of Some v \<Rightarrow> v));
           modify (\<lambda>s. (new_state1));
           word0 \<leftarrow> gets (\<lambda>s. (ldst_word0 instr data_word address));
           if rd \<noteq> 0 then
           do
             write_reg word0 curr_win rd;
             return ()
           od
           else 
             return ()
         od
       od
     od
   od"
 
 text \<open>Operational semantics for atomic load-store.\<close>
 definition load_store_instr :: "instruction \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "load_store_instr instr \<equiv>
   let instr_name = fst instr;
       op_list = snd instr;
       flagi = get_operand_flag (op_list!0);
       rd = if instr_name \<in> {load_store_type LDSTUBA} then \<comment> \<open>\<open>rd\<close> is member 4\<close>
             get_operand_w5 (op_list!4)
            else \<comment> \<open>\<open>rd\<close> is member 3\<close>
             get_operand_w5 (op_list!3)
   in
   do
     psr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PSR s));
     s_val \<leftarrow> gets (\<lambda>s. (get_S psr_val));
     if instr_name \<in> {load_store_type LDSTUBA} \<and> s_val = 0 then 
       do
         raise_trap privileged_instruction;
         return ()
       od
     else if instr_name \<in> {load_store_type LDSTUBA} \<and> flagi = 1 then
       do
         raise_trap illegal_instruction;
         return ()
       od
     else
       load_store_sub1 instr rd s_val
   od"
 
 definition swap_sub1 :: "instruction \<Rightarrow> word5 \<Rightarrow> word1 \<Rightarrow>
   ('a::len0,unit) sparc_state_monad"
 where "swap_sub1 instr rd s_val \<equiv>
   do
     curr_win \<leftarrow> get_curr_win();
     address \<leftarrow> gets (\<lambda>s. (get_addr (snd instr) s));
     asi \<leftarrow> gets (\<lambda>s. (ldst_asi instr s_val));    
     temp \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win rd s));
     \<comment> \<open>wait for locks to be lifted.\<close>
     \<comment> \<open>an implementation actually need only block when another \<open>LDSTUB\<close> or \<open>SWAP\<close>\<close>
     \<comment> \<open>is pending on the same byte in memory as the one addressed by this \<open>LDSTUB\<close>\<close>
     \<comment> \<open>Should wait when \<open>block_type = 1 \<or> block_word = 1\<close>\<close>
     \<comment> \<open>until another processes write both to be 0.\<close>
     \<comment> \<open>We implement this as setting \<open>pc\<close> as \<open>npc\<close> when the instruction\<close>
     \<comment> \<open>is blocked. This way, in the next iteration, we will still execution\<close>
     \<comment> \<open>the current instruction.\<close>
     block_byte \<leftarrow> gets (\<lambda>s. (pb_block_ldst_byte_val address s));
     block_word \<leftarrow> gets (\<lambda>s. (pb_block_ldst_word_val address s));
     if block_byte \<or> block_word then 
     do
       pc_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PC s));
       write_cpu pc_val nPC;
       return ()
     od  
     else 
     do  
       modify (\<lambda>s. (pb_block_ldst_word_mod address True s));
       (result,new_state) \<leftarrow> gets (\<lambda>s. (memory_read asi address s));
       if result = None then
       do
         raise_trap data_access_exception;
         return ()
       od
       else
       do
         word \<leftarrow> gets (\<lambda>s. (case result of Some v \<Rightarrow> v));
         modify (\<lambda>s. (new_state));
         byte_mask \<leftarrow> gets (\<lambda>s. (0b1111::word4));
         result0 \<leftarrow> gets (\<lambda>s. (memory_write asi address byte_mask temp s)); 
         modify (\<lambda>s. (pb_block_ldst_word_mod address False s));
         if result0 = None then
         do
           raise_trap data_access_exception;
           return ()
         od
         else
         do
           new_state1 \<leftarrow> gets (\<lambda>s. (case result0 of Some v \<Rightarrow> v));
           modify (\<lambda>s. (new_state1));
           if rd \<noteq> 0 then
           do
             write_reg word curr_win rd;
             return ()
           od
           else 
             return ()
         od
       od
     od
   od"
 
 text \<open>Operational semantics for swap.\<close>
 definition swap_instr :: "instruction \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "swap_instr instr \<equiv>
   let instr_name = fst instr;
       op_list = snd instr;
       flagi = get_operand_flag (op_list!0);
       rd = if instr_name \<in> {load_store_type SWAPA} then \<comment> \<open>\<open>rd\<close> is member 4\<close>
             get_operand_w5 (op_list!4)
            else \<comment> \<open>\<open>rd\<close> is member 3\<close>
             get_operand_w5 (op_list!3)
   in
   do
     psr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PSR s));
     s_val \<leftarrow> gets (\<lambda>s. (get_S psr_val));
     if instr_name \<in> {load_store_type SWAPA} \<and> s_val = 0 then 
       do
         raise_trap privileged_instruction;
         return ()
       od
     else if instr_name \<in> {load_store_type SWAPA} \<and> flagi = 1 then
       do
         raise_trap illegal_instruction;
         return ()
       od
     else
       swap_sub1 instr rd s_val
   od"
 
 definition bit2_zero :: "word2 \<Rightarrow> word1"
 where "bit2_zero w2 \<equiv> if w2 \<noteq> 0 then 1 else 0"
 
 text \<open>Operational semantics for tagged add instructions.\<close>
 definition tadd_instr :: "instruction \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "tadd_instr instr \<equiv>
   let instr_name = fst instr;
       op_list = snd instr;
       rs1 = get_operand_w5 (op_list!1);
       rd = get_operand_w5 (op_list!3)
   in
   do
     operand2 \<leftarrow> gets (\<lambda>s. (get_operand2 op_list s));
     curr_win \<leftarrow> get_curr_win();
     rs1_val \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win rs1 s));
     psr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PSR s));
     c_val \<leftarrow> gets (\<lambda>s. (get_icc_C psr_val));
     result \<leftarrow> gets (\<lambda>s. (rs1_val + operand2));
     result_31 \<leftarrow> gets (\<lambda>s. ((ucast (result >> 31))::word1));
     rs1_val_31 \<leftarrow> gets (\<lambda>s. ((ucast (rs1_val >> 31))::word1));
     operand2_31 \<leftarrow> gets (\<lambda>s. ((ucast (operand2 >> 31))::word1));
     rs1_val_2 \<leftarrow> gets (\<lambda>s. (bit2_zero ((ucast rs1_val)::word2)));
     operand2_2 \<leftarrow> gets (\<lambda>s. (bit2_zero ((ucast operand2)::word2)));
-    temp_V \<leftarrow> gets (\<lambda>s. (bitOR (bitOR (bitAND rs1_val_31 
-                                              (bitAND operand2_31 
-                                                      (bitNOT result_31))) 
-                                      (bitAND (bitNOT rs1_val_31) 
-                                              (bitAND (bitNOT operand2_31) 
+    temp_V \<leftarrow> gets (\<lambda>s. ((OR) ((OR) ((AND) rs1_val_31 
+                                              ((AND) operand2_31 
+                                                      (NOT result_31))) 
+                                      ((AND) (NOT rs1_val_31) 
+                                              ((AND) (NOT operand2_31) 
                                                       result_31)))
-                               (bitOR rs1_val_2 operand2_2)));
+                               ((OR) rs1_val_2 operand2_2)));
     if instr_name = arith_type TADDccTV \<and> temp_V = 1 then 
     do
       raise_trap tag_overflow;
       return ()
     od
     else 
     do
       rd_val \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win rd s));
       new_rd_val \<leftarrow> gets (\<lambda>s. (if rd \<noteq> 0 then result else rd_val));
       write_reg new_rd_val curr_win rd;      
       new_n_val \<leftarrow> gets (\<lambda>s. (result_31));
       new_z_val \<leftarrow> gets (\<lambda>s. (if result = 0 then 1::word1 else 0::word1));
       new_v_val \<leftarrow> gets (\<lambda>s. temp_V);
-      new_c_val \<leftarrow> gets (\<lambda>s. (bitOR (bitAND rs1_val_31 
+      new_c_val \<leftarrow> gets (\<lambda>s. ((OR) ((AND) rs1_val_31 
                                               operand2_31) 
-                                      (bitAND (bitNOT result_31) 
-                                              (bitOR rs1_val_31 
+                                      ((AND) (NOT result_31) 
+                                              ((OR) rs1_val_31 
                                                      operand2_31))));
       new_psr_val \<leftarrow> gets (\<lambda>s. (update_PSR_icc new_n_val 
                                                  new_z_val 
                                                  new_v_val 
                                                  new_c_val psr_val));
       write_cpu new_psr_val PSR;
       rd_val \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win rd s));
       new_rd_val \<leftarrow> gets (\<lambda>s. (if rd \<noteq> 0 then result else rd_val));
       write_reg new_rd_val curr_win rd;
       return ()
     od
   od"
 
 text \<open>Operational semantics for tagged add instructions.\<close>
 definition tsub_instr :: "instruction \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "tsub_instr instr \<equiv>
   let instr_name = fst instr;
       op_list = snd instr;
       rs1 = get_operand_w5 (op_list!1);
       rd = get_operand_w5 (op_list!3)
   in
   do
     operand2 \<leftarrow> gets (\<lambda>s. (get_operand2 op_list s));
     curr_win \<leftarrow> get_curr_win();
     rs1_val \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win rs1 s));
     psr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PSR s));
     c_val \<leftarrow> gets (\<lambda>s. (get_icc_C psr_val));
     result \<leftarrow> gets (\<lambda>s. (rs1_val - operand2));
     result_31 \<leftarrow> gets (\<lambda>s. ((ucast (result >> 31))::word1));
     rs1_val_31 \<leftarrow> gets (\<lambda>s. ((ucast (rs1_val >> 31))::word1));
     operand2_31 \<leftarrow> gets (\<lambda>s. ((ucast (operand2 >> 31))::word1));
     rs1_val_2 \<leftarrow> gets (\<lambda>s. (bit2_zero ((ucast rs1_val)::word2)));
     operand2_2 \<leftarrow> gets (\<lambda>s. (bit2_zero ((ucast operand2)::word2)));
-    temp_V \<leftarrow> gets (\<lambda>s. (bitOR (bitOR (bitAND rs1_val_31 
-                                              (bitAND operand2_31 
-                                                      (bitNOT result_31))) 
-                                      (bitAND (bitNOT rs1_val_31) 
-                                              (bitAND (bitNOT operand2_31) 
+    temp_V \<leftarrow> gets (\<lambda>s. ((OR) ((OR) ((AND) rs1_val_31 
+                                              ((AND) operand2_31 
+                                                      (NOT result_31))) 
+                                      ((AND) (NOT rs1_val_31) 
+                                              ((AND) (NOT operand2_31) 
                                                       result_31)))
-                               (bitOR rs1_val_2 operand2_2)));
+                               ((OR) rs1_val_2 operand2_2)));
     if instr_name = arith_type TSUBccTV \<and> temp_V = 1 then 
     do
       raise_trap tag_overflow;
       return ()
     od
     else 
     do
       rd_val \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win rd s));
       new_rd_val \<leftarrow> gets (\<lambda>s. (if rd \<noteq> 0 then result else rd_val));
       write_reg new_rd_val curr_win rd;      
       new_n_val \<leftarrow> gets (\<lambda>s. (result_31));
       new_z_val \<leftarrow> gets (\<lambda>s. (if result = 0 then 1::word1 else 0::word1));
       new_v_val \<leftarrow> gets (\<lambda>s. temp_V);
-      new_c_val \<leftarrow> gets (\<lambda>s. (bitOR (bitAND rs1_val_31 
+      new_c_val \<leftarrow> gets (\<lambda>s. ((OR) ((AND) rs1_val_31 
                                               operand2_31) 
-                                      (bitAND (bitNOT result_31) 
-                                              (bitOR rs1_val_31 
+                                      ((AND) (NOT result_31) 
+                                              ((OR) rs1_val_31 
                                                      operand2_31))));
       new_psr_val \<leftarrow> gets (\<lambda>s. (update_PSR_icc new_n_val 
                                                  new_z_val 
                                                  new_v_val 
                                                  new_c_val psr_val));
       write_cpu new_psr_val PSR;
       rd_val \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win rd s));
       new_rd_val \<leftarrow> gets (\<lambda>s. (if rd \<noteq> 0 then result else rd_val));
       write_reg new_rd_val curr_win rd;
       return ()
     od
   od"
 
 definition muls_op2 :: "inst_operand list \<Rightarrow> ('a::len0) sparc_state \<Rightarrow> word32"
 where "muls_op2 op_list s \<equiv>
   let y_val = cpu_reg_val Y s in
   if ((ucast y_val)::word1) = 0 then 0
   else get_operand2 op_list s
 "
 
 text \<open>Operational semantics for multiply step instruction.\<close>
 definition muls_instr :: "instruction \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "muls_instr instr \<equiv>
   let instr_name = fst instr;
       op_list = snd instr;
       rs1 = get_operand_w5 (op_list!1);
       rd = get_operand_w5 (op_list!3)
   in
   do
     curr_win \<leftarrow> get_curr_win();
     rs1_val \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win rs1 s));
     psr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PSR s));
     n_val \<leftarrow> gets (\<lambda>s. (get_icc_N psr_val));
     v_val \<leftarrow> gets (\<lambda>s. (get_icc_V psr_val));
     c_val \<leftarrow> gets (\<lambda>s. (get_icc_C psr_val));
     y_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val Y s));
-    operand1 \<leftarrow> gets (\<lambda>s. (word_cat (bitXOR n_val v_val) 
+    operand1 \<leftarrow> gets (\<lambda>s. (word_cat ((XOR) n_val v_val) 
                                     ((ucast (rs1_val >> 1))::word31)));
     operand2 \<leftarrow> gets (\<lambda>s. (muls_op2 op_list s));    
     result \<leftarrow> gets (\<lambda>s. (operand1 + operand2));
     new_y_val \<leftarrow> gets (\<lambda>s. (word_cat ((ucast rs1_val)::word1) ((ucast (y_val >> 1))::word31)));
     write_cpu new_y_val Y;
     rd_val \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win rd s));
     new_rd_val \<leftarrow> gets (\<lambda>s. (if rd \<noteq> 0 then result else rd_val));
     write_reg new_rd_val curr_win rd;
     result_31 \<leftarrow> gets (\<lambda>s. ((ucast (result >> 31))::word1));
     operand1_31 \<leftarrow> gets (\<lambda>s. ((ucast (operand1 >> 31))::word1));
     operand2_31 \<leftarrow> gets (\<lambda>s. ((ucast (operand2 >> 31))::word1));
     new_n_val \<leftarrow> gets (\<lambda>s. (result_31));
     new_z_val \<leftarrow> gets (\<lambda>s. (if result = 0 then 1::word1 else 0::word1));
-    new_v_val \<leftarrow> gets (\<lambda>s. (bitOR (bitAND operand1_31 
-                                  (bitAND operand2_31 
-                                     (bitNOT result_31))) 
-                                  (bitAND (bitNOT operand1_31) 
-                                     (bitAND (bitNOT operand2_31) 
+    new_v_val \<leftarrow> gets (\<lambda>s. ((OR) ((AND) operand1_31 
+                                  ((AND) operand2_31 
+                                     (NOT result_31))) 
+                                  ((AND) (NOT operand1_31) 
+                                     ((AND) (NOT operand2_31) 
                                              result_31))));
-    new_c_val \<leftarrow> gets (\<lambda>s. (bitOR (bitAND operand1_31 
+    new_c_val \<leftarrow> gets (\<lambda>s. ((OR) ((AND) operand1_31 
                                           operand2_31) 
-                                  (bitAND (bitNOT result_31) 
-                                          (bitOR operand1_31 
+                                  ((AND) (NOT result_31) 
+                                          ((OR) operand1_31 
                                                  operand2_31))));
     new_psr_val \<leftarrow> gets (\<lambda>s. (update_PSR_icc new_n_val 
                                              new_z_val 
                                              new_v_val 
                                              new_c_val psr_val));
     write_cpu new_psr_val PSR;
     return ()
   od"
 
 text\<open>Evaluate icc based on the bits N, Z, V, C in PSR 
        and the type of ticc instruction. 
        See Sparcv8 manual Page 182.\<close>
 definition trap_eval_icc::"sparc_operation \<Rightarrow> word1 \<Rightarrow> word1 \<Rightarrow> word1 \<Rightarrow> word1 \<Rightarrow> int"
 where "trap_eval_icc instr_name n_val z_val v_val c_val \<equiv>
     if instr_name = ticc_type TNE then
       if z_val = 0 then 1 else 0
     else if instr_name = ticc_type TE then 
       if z_val = 1 then 1 else 0
     else if instr_name = ticc_type TG then
-      if (bitOR z_val (n_val XOR v_val)) = 0 then 1 else 0
+      if ((OR) z_val (n_val XOR v_val)) = 0 then 1 else 0
     else if instr_name = ticc_type TLE then
-      if (bitOR z_val (n_val XOR v_val)) = 1 then 1 else 0
+      if ((OR) z_val (n_val XOR v_val)) = 1 then 1 else 0
     else if instr_name = ticc_type TGE then
       if (n_val XOR v_val) = 0 then 1 else 0
     else if instr_name = ticc_type TL then
       if (n_val XOR v_val) = 1 then 1 else 0
     else if instr_name = ticc_type TGU then
       if (c_val = 0 \<and> z_val = 0) then 1 else 0
     else if instr_name = ticc_type TLEU then
       if (c_val = 1 \<or> z_val = 1) then 1 else 0
     else if instr_name = ticc_type TCC then
       if c_val = 0 then 1 else 0
     else if instr_name = ticc_type TCS then
       if c_val = 1 then 1 else 0
     else if instr_name = ticc_type TPOS then
       if n_val = 0 then 1 else 0
     else if instr_name = ticc_type TNEG then
       if n_val = 1 then 1 else 0
     else if instr_name = ticc_type TVC then
       if v_val = 0 then 1 else 0
     else if instr_name = ticc_type TVS then
       if v_val = 1 then 1 else 0
     else if instr_name = ticc_type TA then 1
     else if instr_name = ticc_type TN then 0    
     else -1
 "
 
 text \<open>
   Get \<open>operand2\<close> for \<open>ticc\<close> based on the flag \<open>i\<close>, \<open>rs1\<close>, \<open>rs2\<close>, and \<open>trap_imm7\<close>.
   If \<open>i = 0\<close> then \<open>operand2 = r[rs2]\<close>,
   else \<open>operand2 = sign_ext7(trap_imm7)\<close>.
   \<open>op_list\<close> should be \<open>[i,rs1,rs2]\<close> or \<open>[i,rs1,trap_imm7]\<close>.
 \<close>
 definition get_trap_op2::"inst_operand list \<Rightarrow> ('a::len0) sparc_state
   \<Rightarrow> virtua_address"
 where "get_trap_op2 op_list s \<equiv>
   let flagi = get_operand_flag (op_list!0);
       curr_win = ucast (get_CWP (cpu_reg_val PSR s))
   in
   if flagi = 0 then
     let rs2 = get_operand_w5 (op_list!2);
         rs2_val = user_reg_val curr_win rs2 s
     in rs2_val
   else
     let ext_simm7 = sign_ext7 (get_operand_imm7 (op_list!2)) in
     ext_simm7
 "
 
 text \<open>Operational semantics for Ticc insturctions.\<close>
 definition ticc_instr::"instruction \<Rightarrow> 
   ('a::len0,unit) sparc_state_monad"
 where "ticc_instr instr \<equiv>
   let instr_name = fst instr;
       op_list = snd instr;
       rs1 = get_operand_w5 (op_list!1)
   in
   do
     n_val \<leftarrow> gets (\<lambda>s. get_icc_N ((cpu_reg s) PSR));
     z_val \<leftarrow> gets (\<lambda>s. get_icc_Z ((cpu_reg s) PSR));
     v_val \<leftarrow> gets (\<lambda>s. get_icc_V ((cpu_reg s) PSR));
     c_val \<leftarrow> gets (\<lambda>s. get_icc_C ((cpu_reg s) PSR));
     icc_val \<leftarrow> gets(\<lambda>s. (trap_eval_icc instr_name n_val z_val v_val c_val));
     curr_win \<leftarrow> get_curr_win();
     rs1_val \<leftarrow> gets (\<lambda>s. (user_reg_val curr_win rs1 s));
     trap_number \<leftarrow> gets (\<lambda>s. (rs1_val + (get_trap_op2 op_list s)));
     npc_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val nPC s));
     pc_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val PC s));  
     if icc_val = 1 then 
       do
         raise_trap trap_instruction;
         trap_number7 \<leftarrow> gets (\<lambda>s. ((ucast trap_number)::word7));
         modify (\<lambda>s. (ticc_trap_type_mod trap_number7 s)); 
         return ()
       od
     else \<comment> \<open>\<open>icc_val = 0\<close>\<close>
       do
         write_cpu npc_val PC;
         write_cpu (npc_val + 4) nPC;
         return ()
       od
   od"
 
 text \<open>Operational semantics for store barrier.\<close>
 definition store_barrier_instr::"instruction \<Rightarrow> ('a::len0,unit) sparc_state_monad"
 where "store_barrier_instr instr \<equiv>
   do
     modify (\<lambda>s. (store_barrier_pending_mod True s));
     return ()
   od"
 
 end
diff --git a/thys/SPARCv8/SparcModel_MMU/Sparc_Properties.thy b/thys/SPARCv8/SparcModel_MMU/Sparc_Properties.thy
--- a/thys/SPARCv8/SparcModel_MMU/Sparc_Properties.thy
+++ b/thys/SPARCv8/SparcModel_MMU/Sparc_Properties.thy
@@ -1,8565 +1,8565 @@
 (*
  * Copyright 2016, NTU
  *
  * This software may be distributed and modified according to the terms of
  * the BSD 2-Clause license. Note that NO WARRANTY is provided.
  * See "LICENSE_BSD2.txt" for details.
  *
  * Author: Zhe Hou.
  *)
 
 theory Sparc_Properties
 
 imports Main Sparc_Execution
 
 begin
 
 (*********************************************************************)
 
 section\<open>Single step theorem\<close>
 
 (*********************************************************************)
 
 text \<open>The following shows that, if the pre-state satisfies certain 
   conditions called \<open>good_context\<close>, there must be a defined post-state 
   after a single step execution.\<close>
 
 method save_restore_proof =
 ((simp add: save_restore_instr_def),
  (simp add: Let_def simpler_gets_def bind_def h1_def h2_def),
  (simp add: case_prod_unfold),
  (simp add: raise_trap_def simpler_modify_def),
  (simp add: simpler_gets_def bind_def h1_def h2_def),
  (simp add: save_retore_sub1_def),
  (simp add: write_cpu_def simpler_modify_def),
  (simp add: write_reg_def simpler_modify_def),
  (simp add: get_curr_win_def),
  (simp add: simpler_gets_def bind_def h1_def h2_def))
 
 method select_trap_proof0 = 
 ((simp add: select_trap_def exec_gets return_def),
  (simp add: DetMonad.bind_def h1_def h2_def simpler_modify_def),
  (simp add: write_cpu_tt_def write_cpu_def),
  (simp add: DetMonad.bind_def h1_def h2_def simpler_modify_def),
  (simp add: return_def simpler_gets_def))
 
 method select_trap_proof1 =
 ((simp add: select_trap_def exec_gets return_def),
  (simp add: DetMonad.bind_def h1_def h2_def simpler_modify_def),
  (simp add: write_cpu_tt_def write_cpu_def),
  (simp add: DetMonad.bind_def h1_def h2_def simpler_modify_def),
  (simp add: return_def simpler_gets_def),
  (simp add: emp_trap_set_def err_mode_val_def cpu_reg_mod_def))
 
 method dispatch_instr_proof1 =
 ((simp add: dispatch_instruction_def),
  (simp add: simpler_gets_def bind_def h1_def h2_def),
  (simp add: Let_def))
 
 method exe_proof_to_decode =
 ((simp add: execute_instruction_def),
  (simp add: exec_gets bind_def h1_def h2_def Let_def return_def),
  clarsimp,
  (simp add: simpler_gets_def bind_def h1_def h2_def Let_def simpler_modify_def),
  (simp add: return_def))
 
 method exe_proof_dispatch_rett =
 ((simp add: dispatch_instruction_def),
  (simp add: simpler_gets_def bind_def h1_def h2_def Let_def),
  (simp add: rett_instr_def),
  (simp add: simpler_gets_def bind_def h1_def h2_def Let_def))
 
 lemma write_cpu_result: "snd (write_cpu w r s) = False"
 by (simp add: write_cpu_def simpler_modify_def)
 
 lemma set_annul_result: "snd (set_annul b s) = False"
 by (simp add: set_annul_def simpler_modify_def)
 
 lemma raise_trap_result : "snd (raise_trap t s) = False"
 by (simp add: raise_trap_def simpler_modify_def)
 
 lemma rett_instr_result: "(fst i) = ctrl_type RETT \<and> 
   (get_ET (cpu_reg_val PSR s) \<noteq> 1 \<and>
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) \<noteq> 0 \<and>
   (get_WIM_bit (nat (((uint (get_CWP (cpu_reg_val PSR s))) + 1) mod NWINDOWS)) 
     (cpu_reg_val WIM s)) = 0 \<and>
-  (bitAND (get_addr (snd i) s) (0b00000000000000000000000000000011::word32)) = 0) \<Longrightarrow>
+  ((AND) (get_addr (snd i) s) (0b00000000000000000000000000000011::word32)) = 0) \<Longrightarrow>
   snd (rett_instr i s) = False"
 apply (simp add: rett_instr_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def)
 apply (simp add: write_cpu_def simpler_modify_def)
 apply (simp add: raise_trap_def simpler_modify_def)
 by (simp add: return_def)
 
 lemma call_instr_result: "(fst i) = call_type CALL \<Longrightarrow>
   snd (call_instr i s) = False"
 apply (simp add: call_instr_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def case_prod_unfold)
 apply (simp add: write_cpu_def write_reg_def)
 apply (simp add: get_curr_win_def get_CWP_def)
 by (simp add: simpler_modify_def simpler_gets_def)
 
 lemma branch_instr_result: "(fst i) \<in> {bicc_type BE,bicc_type BNE,bicc_type BGU,
  bicc_type BLE,bicc_type BL,bicc_type BGE,bicc_type BNEG,bicc_type BG,
  bicc_type BCS,bicc_type BLEU,bicc_type BCC,bicc_type BA,bicc_type BN}  \<Longrightarrow>
   snd (branch_instr i s) = False" 
 proof (cases "eval_icc (fst i) (get_icc_N ((cpu_reg s) PSR)) (get_icc_Z ((cpu_reg s) PSR))
                            (get_icc_V ((cpu_reg s) PSR)) (get_icc_C ((cpu_reg s) PSR)) = 1")
   case True
   then have f1: "eval_icc (fst i) (get_icc_N ((cpu_reg s) PSR)) (get_icc_Z ((cpu_reg s) PSR))
                            (get_icc_V ((cpu_reg s) PSR)) (get_icc_C ((cpu_reg s) PSR)) = 1" 
     by auto
   then show ?thesis
   proof (cases "(fst i) = bicc_type BA \<and> get_operand_flag ((snd i)!0) = 1")
     case True
     then show ?thesis using f1
     apply (simp add: branch_instr_def)
     apply (simp add: Let_def simpler_gets_def bind_def h1_def h2_def)    
     apply (simp add: set_annul_def case_prod_unfold)
     apply (simp add: write_cpu_def simpler_modify_def)
     by (simp add: return_def)   
   next
     case False
     then have f2: "\<not> (fst i = bicc_type BA \<and> get_operand_flag (snd i ! 0) = 1)" by auto
     then show ?thesis using f1
     apply (simp add: branch_instr_def)
     apply (simp add: simpler_gets_def bind_def h1_def h2_def)
     apply (simp add: write_cpu_def simpler_modify_def)
     apply (simp add: branch_instr_sub1_def)
     apply (simp add: Let_def)
     apply auto
     apply (simp add: write_cpu_def simpler_modify_def)    
     by (simp add: write_cpu_def simpler_modify_def)
   qed
 next
   case False
   then show ?thesis
   apply (simp add: branch_instr_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def)
   apply (simp add: write_cpu_def simpler_modify_def)
   apply (simp add: branch_instr_sub1_def)
   apply (simp add: Let_def)
   apply auto
    apply (simp add: Let_def bind_def h1_def h2_def)
    apply (simp add: write_cpu_def simpler_modify_def)
    apply (simp add: cpu_reg_mod_def set_annul_def simpler_modify_def)
   by (simp add: write_cpu_def simpler_modify_def)
 qed
 
 lemma nop_instr_result: "(fst i) = nop_type NOP \<Longrightarrow>
   snd (nop_instr i s) = False"
 apply (simp add: nop_instr_def)
 by (simp add: returnOk_def return_def)
 
 lemma sethi_instr_result: "(fst i) = sethi_type SETHI \<Longrightarrow>
   snd (sethi_instr i s) = False"
 apply (simp add: sethi_instr_def)
 apply (simp add: Let_def)
 apply (simp add: get_curr_win_def get_CWP_def cpu_reg_val_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def)
 apply (simp add: write_reg_def simpler_modify_def)
 by (simp add: return_def)
 
 lemma jmpl_instr_result: "(fst i) = ctrl_type JMPL \<Longrightarrow>
   snd (jmpl_instr i s) = False"
 apply (simp add: jmpl_instr_def)
 apply (simp add: get_curr_win_def get_CWP_def cpu_reg_val_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def)
 apply (simp add: Let_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def)
 apply (simp add: write_reg_def simpler_modify_def)
 apply (simp add: write_cpu_def simpler_modify_def)
 by (simp add: raise_trap_def simpler_modify_def)
 
 lemma save_restore_instr_result: "(fst i) \<in> {ctrl_type SAVE,ctrl_type RESTORE} \<Longrightarrow>
   snd (save_restore_instr i s) = False"
 proof (cases "(fst i) = ctrl_type SAVE")
   case True
   then show ?thesis
   by save_restore_proof
 next
   case False
   then show ?thesis
   by save_restore_proof
 qed
 
 lemma flush_instr_result: "(fst i) = load_store_type FLUSH  \<Longrightarrow>
   snd (flush_instr i s) = False" 
 apply (simp add: flush_instr_def)
 by (simp add: simpler_gets_def bind_def h1_def h2_def simpler_modify_def)
 
 lemma read_state_reg_instr_result: "(fst i) \<in> {sreg_type RDY,sreg_type RDPSR,
   sreg_type RDWIM,sreg_type RDTBR} \<Longrightarrow>
   snd (read_state_reg_instr i s) = False"
 apply (simp add: read_state_reg_instr_def)
 apply (simp add: Let_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 apply (simp add: simpler_gets_def bind_def)
 apply (simp add: write_reg_def simpler_modify_def)
 apply (simp add: raise_trap_def simpler_modify_def return_def)
 apply (simp add: bind_def h1_def h2_def)
 by (simp add: get_curr_win_def simpler_gets_def)
 
 lemma write_state_reg_instr_result: "(fst i) \<in> {sreg_type WRY,sreg_type WRPSR,
   sreg_type WRWIM,sreg_type WRTBR} \<Longrightarrow>
   snd (write_state_reg_instr i s) = False" 
 apply (simp add: write_state_reg_instr_def)
 apply (simp add: Let_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 apply (simp add: simpler_modify_def)
 apply (simp add: raise_trap_def simpler_modify_def return_def)
 apply (simp add: bind_def h1_def h2_def)
 apply (simp add: simpler_gets_def)
 apply (simp add: write_cpu_def simpler_modify_def)
 by (simp add: get_curr_win_def simpler_gets_def)
 
 lemma logical_instr_result: "(fst i) \<in> {logic_type ANDs,logic_type ANDcc,
   logic_type ANDN,logic_type ANDNcc,logic_type ORs,logic_type ORcc,
   logic_type ORN,logic_type XORs,logic_type XNOR} \<Longrightarrow>
   snd (logical_instr i s) = False"
 apply (simp add: logical_instr_def)
 apply (simp add: Let_def simpler_gets_def)
 apply (simp add: write_reg_def simpler_modify_def)
 apply (simp add: bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 apply (simp add: logical_instr_sub1_def)
 apply (simp add: return_def)
 apply (simp add: write_cpu_def simpler_modify_def)
 apply (simp add: bind_def h1_def h2_def)
 apply (simp add: case_prod_unfold)
 apply (simp add: simpler_gets_def)
 by (simp add: get_curr_win_def simpler_gets_def)
 
 lemma shift_instr_result: "(fst i) \<in> {shift_type SLL,shift_type 
   SRL,shift_type SRA} \<Longrightarrow>
   snd (shift_instr i s) = False"
 apply (simp add: shift_instr_def)
 apply (simp add: Let_def)
 apply (simp add: get_curr_win_def simpler_gets_def bind_def h1_def h2_def)
 apply (simp add: return_def)
 apply (simp add: bind_def h1_def h2_def)
 by (simp add: write_reg_def simpler_modify_def)
 
 method add_sub_instr_proof =
 ((simp add: Let_def),
  auto,
  (simp add: write_reg_def simpler_modify_def),
  (simp add: simpler_gets_def bind_def),
  (simp add: get_curr_win_def simpler_gets_def),
  (simp add: write_reg_def write_cpu_def simpler_modify_def),
  (simp add: bind_def),
  (simp add: case_prod_unfold),
  (simp add: simpler_gets_def),
  (simp add: get_curr_win_def simpler_gets_def),
  (simp add: write_reg_def simpler_modify_def),
  (simp add: simpler_gets_def bind_def),
  (simp add: get_curr_win_def simpler_gets_def))
 
 lemma add_instr_result: "(fst i) \<in> {arith_type ADD,arith_type 
   ADDcc,arith_type ADDX} \<Longrightarrow>
   snd (add_instr i s) = False"
 apply (simp add: add_instr_def)
 apply (simp add: Let_def)
 apply auto
   apply (simp add: add_instr_sub1_def)
   apply (simp add: write_reg_def simpler_modify_def)
   apply (simp add: bind_def h1_def h2_def Let_def)
   apply (simp add: case_prod_unfold)
   apply (simp add: simpler_gets_def)
   apply (simp add: get_curr_win_def simpler_gets_def)
  apply (simp add: add_instr_sub1_def)
  apply (simp add: write_reg_def simpler_modify_def)
  apply (simp add: simpler_gets_def bind_def h1_def h2_def)
  apply (simp add: get_curr_win_def simpler_gets_def)
  apply (simp add: write_cpu_def simpler_modify_def)
 apply (simp add: add_instr_sub1_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def)
 apply (simp add: get_curr_win_def simpler_gets_def)
 by (simp add: write_reg_def simpler_modify_def)
 
 lemma sub_instr_result: "(fst i) \<in> {arith_type SUB,arith_type SUBcc,
   arith_type SUBX} \<Longrightarrow>
   snd (sub_instr i s) = False"
 apply (simp add: sub_instr_def)
 apply (simp add: Let_def)
 apply auto
   apply (simp add: sub_instr_sub1_def)
   apply (simp add: write_reg_def simpler_modify_def)
   apply (simp add: bind_def h1_def h2_def Let_def)
   apply (simp add: case_prod_unfold)
   apply (simp add: simpler_gets_def)
   apply (simp add: get_curr_win_def simpler_gets_def)
  apply (simp add: sub_instr_sub1_def)
  apply (simp add: write_reg_def simpler_modify_def)
  apply (simp add: simpler_gets_def bind_def h1_def h2_def)
  apply (simp add: get_curr_win_def simpler_gets_def)
  apply (simp add: write_cpu_def simpler_modify_def)
 apply (simp add: sub_instr_sub1_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def)
 apply (simp add: get_curr_win_def simpler_gets_def)
 by (simp add: write_reg_def simpler_modify_def)
 
 lemma mul_instr_result: "(fst i) \<in> {arith_type UMUL,arith_type SMUL,
   arith_type SMULcc} \<Longrightarrow>
   snd (mul_instr i s) = False"
 apply (simp add: mul_instr_def)
 apply (simp add: Let_def)
 apply auto
   apply (simp add: mul_instr_sub1_def)
   apply (simp add: write_reg_def simpler_modify_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def)
   apply (simp add: get_curr_win_def simpler_gets_def)
   apply (simp add: write_reg_def write_cpu_def simpler_modify_def)
  apply (simp add: mul_instr_sub1_def)
  apply (simp add: simpler_gets_def)
  apply (simp add: write_cpu_def write_reg_def simpler_modify_def)
  apply (simp add: bind_def h1_def h2_def Let_def)
  apply (simp add: get_curr_win_def simpler_gets_def)
 apply (simp add: mul_instr_sub1_def)
 apply (simp add: simpler_gets_def)
 apply (simp add: write_cpu_def write_reg_def simpler_modify_def)
 apply (simp add: bind_def h1_def h2_def)
 by (simp add: get_curr_win_def simpler_gets_def)
 
 lemma div_write_new_val_result: "snd (div_write_new_val i result temp_V s) = False"
 apply (simp add: div_write_new_val_def)
 apply (simp add: return_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def)
 by (simp add: write_cpu_def simpler_modify_def)
 
 lemma div_result: "snd (div_comp instr rs1 rd operand2 s) = False"
 apply (simp add: div_comp_def)
 apply (simp add: simpler_gets_def)
 apply (simp add: bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 apply (simp add: write_reg_def simpler_modify_def)
 apply (simp add: get_curr_win_def simpler_gets_def)
 by (simp add: div_write_new_val_result)
 
 lemma div_instr_result: "(fst i) \<in> {arith_type UDIV,arith_type UDIVcc,
   arith_type SDIV} \<Longrightarrow>
   snd (div_instr i s) = False"
 apply (simp add: div_instr_def)
 apply (simp add: Let_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def)
 apply (simp add: raise_trap_def simpler_modify_def)
 apply (simp add: return_def bind_def)
 by (simp add: div_result)
 
 lemma load_sub2_result: "snd (load_sub2 address asi rd curr_win word0 s) = False"
 apply (simp add: load_sub2_def)
 apply (simp add: write_reg_def simpler_modify_def)
 apply (simp add: bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 apply (simp add: raise_trap_def simpler_modify_def)
 apply (simp add: bind_def h1_def h2_def)
 apply (simp add: write_reg_def simpler_modify_def)
 by (simp add: simpler_gets_def)
 
 lemma load_sub3_result: "snd (load_sub3 instr curr_win rd asi address s) = False"
 apply (simp add: load_sub3_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def)
 apply (simp add: case_prod_unfold)
 apply (simp add: simpler_modify_def bind_def h1_def h2_def Let_def)
 apply (simp add: write_reg_def simpler_modify_def)
 apply (simp add: load_sub2_result)
 by (simp add: raise_trap_def simpler_modify_def)
 
 lemma load_sub1_result: "snd (load_sub1 i rd s_val s) = False"
 apply (simp add: load_sub1_def)
 apply (simp add: bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 apply (simp add: raise_trap_def simpler_modify_def)
 apply (simp add: get_curr_win_def simpler_gets_def)
 by (simp add: load_sub3_result)
 
 lemma load_instr_result: "(fst i) \<in> {load_store_type LDSB,load_store_type LDUB,
   load_store_type LDUBA,load_store_type LDUH,load_store_type LD,
   load_store_type LDA,load_store_type LDD} \<Longrightarrow>
   snd (load_instr i s) = False"
 apply (simp add: load_instr_def)
 apply (simp add: Let_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def)
 apply (simp add: raise_trap_def simpler_modify_def)
 apply (simp add: return_def)
 by (simp add: load_sub1_result)
 
 lemma store_sub2_result: "snd (store_sub2 instr curr_win rd asi address s) = False"
 apply (simp add: store_sub2_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def)
 apply (simp add: raise_trap_def simpler_modify_def)
 apply (simp add: return_def)
 apply (simp add: raise_trap_def simpler_modify_def)
 by (simp add: bind_def h1_def h2_def)
 
 lemma store_sub1_result: "snd (store_sub1 instr rd s_val s) = False"
 apply (simp add: store_sub1_def)
 apply (simp add: bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 apply (simp add: raise_trap_def simpler_modify_def)
 apply (simp add: get_curr_win_def)
 apply (simp add: simpler_gets_def)
 by (simp add: store_sub2_result)
 
 lemma store_instr_result: "(fst i) \<in> {load_store_type STB,load_store_type STH,
   load_store_type ST,load_store_type STA,load_store_type STD} \<Longrightarrow>
   snd (store_instr i s) = False"
 apply (simp add: store_instr_def)
 apply (simp add: Let_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def)
 apply (simp add: raise_trap_def simpler_modify_def)
 apply (simp add: return_def)
 by (simp add: store_sub1_result)
 
 lemma supported_instr_set: "supported_instruction i = True \<Longrightarrow> 
   i \<in> {load_store_type LDSB,load_store_type LDUB,load_store_type LDUBA,
               load_store_type LDUH,load_store_type LD,load_store_type LDA,
               load_store_type LDD,
               load_store_type STB,load_store_type STH,load_store_type ST,
               load_store_type STA,load_store_type STD,
               sethi_type SETHI,
               nop_type NOP,
               logic_type ANDs,logic_type ANDcc,logic_type ANDN,logic_type ANDNcc,
               logic_type ORs,logic_type ORcc,logic_type ORN,logic_type XORs,
               logic_type XNOR,
               shift_type SLL,shift_type SRL,shift_type SRA,
               arith_type ADD,arith_type ADDcc,arith_type ADDX,
               arith_type SUB,arith_type SUBcc,arith_type SUBX,
               arith_type UMUL,arith_type SMUL,arith_type SMULcc,
               arith_type UDIV,arith_type UDIVcc,arith_type SDIV,
               ctrl_type SAVE,ctrl_type RESTORE,
               call_type CALL,
               ctrl_type JMPL,
               ctrl_type RETT,
               sreg_type RDY,sreg_type RDPSR,sreg_type RDWIM,sreg_type RDTBR,
               sreg_type WRY,sreg_type WRPSR,sreg_type WRWIM,sreg_type WRTBR,
               load_store_type FLUSH,
               bicc_type BE,bicc_type BNE,bicc_type BGU,bicc_type BLE,
               bicc_type BL,bicc_type BGE,bicc_type BNEG,bicc_type BG,
               bicc_type BCS,bicc_type BLEU,bicc_type BCC,bicc_type BA,
               bicc_type BN}"
 apply (simp add: supported_instruction_def)
 by presburger
 
 lemma dispatch_instr_result: 
 assumes a1: "supported_instruction (fst i) = True \<and> (fst i) \<noteq> ctrl_type RETT"
 shows "snd (dispatch_instruction i s) = False"
 proof (cases "get_trap_set s = {}")
   case True
   then have f1: "get_trap_set s = {}" by auto
   then show ?thesis 
   proof (cases "(fst i) \<in> {load_store_type LDSB,load_store_type LDUB,
     load_store_type LDUBA,load_store_type LDUH,load_store_type LD,
     load_store_type LDA,load_store_type LDD}")
     case True
     then show ?thesis using f1 
     apply dispatch_instr_proof1
     by (simp add: load_instr_result)
   next
     case False
     then have f2: "(fst i) \<in> {load_store_type STB,load_store_type STH,load_store_type ST,
               load_store_type STA,load_store_type STD,
               sethi_type SETHI,
               nop_type NOP,
               logic_type ANDs,logic_type ANDcc,logic_type ANDN,logic_type ANDNcc,
               logic_type ORs,logic_type ORcc,logic_type ORN,logic_type XORs,
               logic_type XNOR,
               shift_type SLL,shift_type SRL,shift_type SRA,
               arith_type ADD,arith_type ADDcc,arith_type ADDX,
               arith_type SUB,arith_type SUBcc,arith_type SUBX,
               arith_type UMUL,arith_type SMUL,arith_type SMULcc,
               arith_type UDIV,arith_type UDIVcc,arith_type SDIV,
               ctrl_type SAVE,ctrl_type RESTORE,
               call_type CALL,
               ctrl_type JMPL,
               sreg_type RDY,sreg_type RDPSR,sreg_type RDWIM,sreg_type RDTBR,
               sreg_type WRY,sreg_type WRPSR,sreg_type WRWIM,sreg_type WRTBR,
               load_store_type FLUSH,
               bicc_type BE,bicc_type BNE,bicc_type BGU,bicc_type BLE,
               bicc_type BL,bicc_type BGE,bicc_type BNEG,bicc_type BG,
               bicc_type BCS,bicc_type BLEU,bicc_type BCC,bicc_type BA,
               bicc_type BN}"
      using a1 
      apply (simp add: supported_instruction_def)
      by presburger
      then show ?thesis 
      proof (cases "(fst i) \<in> {load_store_type STB,load_store_type STH,
        load_store_type ST,
        load_store_type STA,load_store_type STD}")
       case True
       then show ?thesis using f1
       apply dispatch_instr_proof1      
       by (auto simp add: store_instr_result)
      next
       case False
       then have f3: "(fst i) \<in> {sethi_type SETHI,
               nop_type NOP,
               logic_type ANDs,logic_type ANDcc,logic_type ANDN,logic_type ANDNcc,
               logic_type ORs,logic_type ORcc,logic_type ORN,logic_type XORs,
               logic_type XNOR,
               shift_type SLL,shift_type SRL,shift_type SRA,
               arith_type ADD,arith_type ADDcc,arith_type ADDX,
               arith_type SUB,arith_type SUBcc,arith_type SUBX,
               arith_type UMUL,arith_type SMUL,arith_type SMULcc,
               arith_type UDIV,arith_type UDIVcc,arith_type SDIV,
               ctrl_type SAVE,ctrl_type RESTORE,
               call_type CALL,
               ctrl_type JMPL,
               sreg_type RDY,sreg_type RDPSR,sreg_type RDWIM,sreg_type RDTBR,
               sreg_type WRY,sreg_type WRPSR,sreg_type WRWIM,sreg_type WRTBR,
               load_store_type FLUSH,
               bicc_type BE,bicc_type BNE,bicc_type BGU,bicc_type BLE,
               bicc_type BL,bicc_type BGE,bicc_type BNEG,bicc_type BG,
               bicc_type BCS,bicc_type BLEU,bicc_type BCC,bicc_type BA,
               bicc_type BN}"
       using f2 by auto
       then show ?thesis 
       proof (cases "(fst i) = sethi_type SETHI")
         case True
         then show ?thesis using f1
         apply dispatch_instr_proof1
         by (simp add: sethi_instr_result)
       next
         case False
         then have f4: "(fst i) \<in> {nop_type NOP,
               logic_type ANDs,logic_type ANDcc,logic_type ANDN,logic_type ANDNcc,
               logic_type ORs,logic_type ORcc,logic_type ORN,logic_type XORs,
               logic_type XNOR,
               shift_type SLL,shift_type SRL,shift_type SRA,
               arith_type ADD,arith_type ADDcc,arith_type ADDX,
               arith_type SUB,arith_type SUBcc,arith_type SUBX,
               arith_type UMUL,arith_type SMUL,arith_type SMULcc,
               arith_type UDIV,arith_type UDIVcc,arith_type SDIV,
               ctrl_type SAVE,ctrl_type RESTORE,
               call_type CALL,
               ctrl_type JMPL,
               sreg_type RDY,sreg_type RDPSR,sreg_type RDWIM,sreg_type RDTBR,
               sreg_type WRY,sreg_type WRPSR,sreg_type WRWIM,sreg_type WRTBR,
               load_store_type FLUSH,
               bicc_type BE,bicc_type BNE,bicc_type BGU,bicc_type BLE,
               bicc_type BL,bicc_type BGE,bicc_type BNEG,bicc_type BG,
               bicc_type BCS,bicc_type BLEU,bicc_type BCC,bicc_type BA,
               bicc_type BN}"
         using f3 by auto         
         then show ?thesis 
         proof (cases "fst i = nop_type NOP")
           case True
           then show ?thesis using f1
           apply dispatch_instr_proof1
           by (simp add: nop_instr_result)
         next
           case False
           then have f5: "(fst i) \<in> {logic_type ANDs,logic_type ANDcc,
               logic_type ANDN,logic_type ANDNcc,
               logic_type ORs,logic_type ORcc,logic_type ORN,logic_type XORs,
               logic_type XNOR,
               shift_type SLL,shift_type SRL,shift_type SRA,
               arith_type ADD,arith_type ADDcc,arith_type ADDX,
               arith_type SUB,arith_type SUBcc,arith_type SUBX,
               arith_type UMUL,arith_type SMUL,arith_type SMULcc,
               arith_type UDIV,arith_type UDIVcc,arith_type SDIV,
               ctrl_type SAVE,ctrl_type RESTORE,
               call_type CALL,
               ctrl_type JMPL,
               sreg_type RDY,sreg_type RDPSR,sreg_type RDWIM,sreg_type RDTBR,
               sreg_type WRY,sreg_type WRPSR,sreg_type WRWIM,sreg_type WRTBR,
               load_store_type FLUSH,
               bicc_type BE,bicc_type BNE,bicc_type BGU,bicc_type BLE,
               bicc_type BL,bicc_type BGE,bicc_type BNEG,bicc_type BG,
               bicc_type BCS,bicc_type BLEU,bicc_type BCC,bicc_type BA,
               bicc_type BN}"
           using f4 by auto
           then show ?thesis 
           proof (cases "(fst i) \<in> {logic_type ANDs,logic_type ANDcc,
               logic_type ANDN,logic_type ANDNcc,
               logic_type ORs,logic_type ORcc,logic_type ORN,logic_type XORs,
               logic_type XNOR}")
             case True
             then show ?thesis using f1
             apply dispatch_instr_proof1
             by (auto simp add: logical_instr_result)
           next
             case False
             then have f6: "(fst i) \<in> {shift_type SLL,shift_type SRL,
               shift_type SRA,
               arith_type ADD,arith_type ADDcc,arith_type ADDX,
               arith_type SUB,arith_type SUBcc,arith_type SUBX,
               arith_type UMUL,arith_type SMUL,arith_type SMULcc,
               arith_type UDIV,arith_type UDIVcc,arith_type SDIV,
               ctrl_type SAVE,ctrl_type RESTORE,
               call_type CALL,
               ctrl_type JMPL,
               sreg_type RDY,sreg_type RDPSR,sreg_type RDWIM,sreg_type RDTBR,
               sreg_type WRY,sreg_type WRPSR,sreg_type WRWIM,sreg_type WRTBR,
               load_store_type FLUSH,
               bicc_type BE,bicc_type BNE,bicc_type BGU,bicc_type BLE,
               bicc_type BL,bicc_type BGE,bicc_type BNEG,bicc_type BG,
               bicc_type BCS,bicc_type BLEU,bicc_type BCC,bicc_type BA,
               bicc_type BN}"
             using f5 by auto
             then show ?thesis 
             proof (cases "(fst i) \<in> {shift_type SLL,shift_type SRL,
               shift_type SRA}")
               case True
               then show ?thesis using f1
               apply dispatch_instr_proof1
               by (auto simp add: shift_instr_result)
             next 
               case False
               then have f7: "(fst i) \<in> {arith_type ADD,arith_type ADDcc,
               arith_type ADDX,
               arith_type SUB,arith_type SUBcc,arith_type SUBX,
               arith_type UMUL,arith_type SMUL,arith_type SMULcc,
               arith_type UDIV,arith_type UDIVcc,arith_type SDIV,
               ctrl_type SAVE,ctrl_type RESTORE,
               call_type CALL,
               ctrl_type JMPL,
               sreg_type RDY,sreg_type RDPSR,sreg_type RDWIM,sreg_type RDTBR,
               sreg_type WRY,sreg_type WRPSR,sreg_type WRWIM,sreg_type WRTBR,
               load_store_type FLUSH,
               bicc_type BE,bicc_type BNE,bicc_type BGU,bicc_type BLE,
               bicc_type BL,bicc_type BGE,bicc_type BNEG,bicc_type BG,
               bicc_type BCS,bicc_type BLEU,bicc_type BCC,bicc_type BA,
               bicc_type BN}" 
               using f6 by auto
               then show ?thesis 
               proof (cases "(fst i) \<in> {arith_type ADD,arith_type ADDcc,
               arith_type ADDX}")
                 case True
                 then show ?thesis using f1
                 apply dispatch_instr_proof1
                 by (auto simp add: add_instr_result)
               next
                 case False
                 then have f8: "(fst i) \<in> {arith_type SUB,arith_type SUBcc,
                 arith_type SUBX,
               arith_type UMUL,arith_type SMUL,arith_type SMULcc,
               arith_type UDIV,arith_type UDIVcc,arith_type SDIV,
               ctrl_type SAVE,ctrl_type RESTORE,
               call_type CALL,
               ctrl_type JMPL,
               sreg_type RDY,sreg_type RDPSR,sreg_type RDWIM,sreg_type RDTBR,
               sreg_type WRY,sreg_type WRPSR,sreg_type WRWIM,sreg_type WRTBR,
               load_store_type FLUSH,
               bicc_type BE,bicc_type BNE,bicc_type BGU,bicc_type BLE,
               bicc_type BL,bicc_type BGE,bicc_type BNEG,bicc_type BG,
               bicc_type BCS,bicc_type BLEU,bicc_type BCC,bicc_type BA,
               bicc_type BN}"
                 using f7 by auto
                 then show ?thesis 
                 proof (cases "(fst i) \<in> {arith_type SUB,arith_type SUBcc,
                 arith_type SUBX}")
                   case True
                   then show ?thesis using f1
                   apply dispatch_instr_proof1
                   by (auto simp add: sub_instr_result)
                 next
                   case False
                   then have f9: "(fst i) \<in> {arith_type UMUL,arith_type SMUL,
                   arith_type SMULcc,
               arith_type UDIV,arith_type UDIVcc,arith_type SDIV,
               ctrl_type SAVE,ctrl_type RESTORE,
               call_type CALL,
               ctrl_type JMPL,
               sreg_type RDY,sreg_type RDPSR,sreg_type RDWIM,sreg_type RDTBR,
               sreg_type WRY,sreg_type WRPSR,sreg_type WRWIM,sreg_type WRTBR,
               load_store_type FLUSH,
               bicc_type BE,bicc_type BNE,bicc_type BGU,bicc_type BLE,
               bicc_type BL,bicc_type BGE,bicc_type BNEG,bicc_type BG,
               bicc_type BCS,bicc_type BLEU,bicc_type BCC,bicc_type BA,
               bicc_type BN}"
                   using f8 by auto
                   then show ?thesis 
                   proof (cases "(fst i) \<in> {arith_type UMUL,arith_type SMUL,
                   arith_type SMULcc}")
                     case True
                     then show ?thesis using f1
                     apply dispatch_instr_proof1
                     by (auto simp add: mul_instr_result)
                   next
                     case False
                     then have f10: "(fst i) \<in> {arith_type UDIV,arith_type UDIVcc,
                     arith_type SDIV,
               ctrl_type SAVE,ctrl_type RESTORE,
               call_type CALL,
               ctrl_type JMPL,
               sreg_type RDY,sreg_type RDPSR,sreg_type RDWIM,sreg_type RDTBR,
               sreg_type WRY,sreg_type WRPSR,sreg_type WRWIM,sreg_type WRTBR,
               load_store_type FLUSH,
               bicc_type BE,bicc_type BNE,bicc_type BGU,bicc_type BLE,
               bicc_type BL,bicc_type BGE,bicc_type BNEG,bicc_type BG,
               bicc_type BCS,bicc_type BLEU,bicc_type BCC,bicc_type BA,
               bicc_type BN}"
                     using f9 by auto
                     then show ?thesis 
                     proof (cases "(fst i) \<in> {arith_type UDIV,arith_type UDIVcc,
                     arith_type SDIV}")
                       case True
                       then show ?thesis 
                       apply dispatch_instr_proof1 using f1
                       by (auto simp add: div_instr_result)
                     next
                       case False
                       then have f11: "(fst i) \<in> {ctrl_type SAVE,ctrl_type RESTORE,
               call_type CALL,
               ctrl_type JMPL,
               sreg_type RDY,sreg_type RDPSR,sreg_type RDWIM,sreg_type RDTBR,
               sreg_type WRY,sreg_type WRPSR,sreg_type WRWIM,sreg_type WRTBR,
               load_store_type FLUSH,
               bicc_type BE,bicc_type BNE,bicc_type BGU,bicc_type BLE,
               bicc_type BL,bicc_type BGE,bicc_type BNEG,bicc_type BG,
               bicc_type BCS,bicc_type BLEU,bicc_type BCC,bicc_type BA,
               bicc_type BN}"
                       using f10 by auto
                       then show ?thesis 
                       proof (cases "(fst i) \<in> {ctrl_type SAVE,ctrl_type RESTORE}")
                         case True
                         then show ?thesis using f1
                         apply dispatch_instr_proof1 
                         by (auto simp add: save_restore_instr_result)
                       next
                         case False
                         then have f12: "(fst i) \<in> {call_type CALL,
               ctrl_type JMPL,
               sreg_type RDY,sreg_type RDPSR,sreg_type RDWIM,sreg_type RDTBR,
               sreg_type WRY,sreg_type WRPSR,sreg_type WRWIM,sreg_type WRTBR,
               load_store_type FLUSH,
               bicc_type BE,bicc_type BNE,bicc_type BGU,bicc_type BLE,
               bicc_type BL,bicc_type BGE,bicc_type BNEG,bicc_type BG,
               bicc_type BCS,bicc_type BLEU,bicc_type BCC,bicc_type BA,
               bicc_type BN}"
                         using f11 by auto
                         then show ?thesis 
                         proof (cases "(fst i) = call_type CALL")
                           case True
                           then show ?thesis using f1
                           apply dispatch_instr_proof1
                           by (auto simp add: call_instr_result)
                         next
                           case False
                           then have f13: "(fst i) \<in> {ctrl_type JMPL,
               sreg_type RDY,sreg_type RDPSR,sreg_type RDWIM,sreg_type RDTBR,
               sreg_type WRY,sreg_type WRPSR,sreg_type WRWIM,sreg_type WRTBR,
               load_store_type FLUSH,
               bicc_type BE,bicc_type BNE,bicc_type BGU,bicc_type BLE,
               bicc_type BL,bicc_type BGE,bicc_type BNEG,bicc_type BG,
               bicc_type BCS,bicc_type BLEU,bicc_type BCC,bicc_type BA,
               bicc_type BN}"
                           using f12 by auto
                           then show ?thesis 
                           proof (cases "(fst i) = ctrl_type JMPL")
                             case True
                             then show ?thesis using f1
                             apply dispatch_instr_proof1
                             by (auto simp add: jmpl_instr_result)
                           next
                             case False
                             then have f14: "(fst i) \<in> {
                             sreg_type RDY,
                             sreg_type RDPSR,sreg_type RDWIM,sreg_type RDTBR,
               sreg_type WRY,sreg_type WRPSR,sreg_type WRWIM,sreg_type WRTBR,
               load_store_type FLUSH,
               bicc_type BE,bicc_type BNE,bicc_type BGU,bicc_type BLE,
               bicc_type BL,bicc_type BGE,bicc_type BNEG,bicc_type BG,
               bicc_type BCS,bicc_type BLEU,bicc_type BCC,bicc_type BA,
               bicc_type BN}"
                             using f13 by auto
                             then show ?thesis 
                             proof (cases "(fst i) \<in> {sreg_type RDY,
                             sreg_type RDPSR,sreg_type RDWIM,sreg_type RDTBR}")
                               case True
                               then show ?thesis using f1
                               apply dispatch_instr_proof1
                               by (auto simp add: read_state_reg_instr_result)
                             next
                               case False
                               then have f15: "(fst i) \<in> {
                               sreg_type WRY,
                               sreg_type WRPSR,sreg_type WRWIM,sreg_type WRTBR,
               load_store_type FLUSH,
               bicc_type BE,bicc_type BNE,bicc_type BGU,bicc_type BLE,
               bicc_type BL,bicc_type BGE,bicc_type BNEG,bicc_type BG,
               bicc_type BCS,bicc_type BLEU,bicc_type BCC,bicc_type BA,
               bicc_type BN}"
                               using f14 by auto
                               then show ?thesis 
                               proof (cases "(fst i) \<in> {sreg_type WRY,
                               sreg_type WRPSR,sreg_type WRWIM,sreg_type WRTBR}")
                                 case True
                                 then show ?thesis using f1
                                 apply dispatch_instr_proof1
                                 by (auto simp add: write_state_reg_instr_result)
                               next
                                 case False
                                 then have f16: "(fst i) \<in> {
                                 load_store_type FLUSH,
               bicc_type BE,bicc_type BNE,bicc_type BGU,bicc_type BLE,
               bicc_type BL,bicc_type BGE,bicc_type BNEG,bicc_type BG,
               bicc_type BCS,bicc_type BLEU,bicc_type BCC,bicc_type BA,
               bicc_type BN}"
                                 using f15 by auto
                                 then show ?thesis 
                                 proof (cases "(fst i) = load_store_type FLUSH")
                                   case True
                                   then show ?thesis using f1
                                   apply dispatch_instr_proof1
                                   by (auto simp add: flush_instr_result)
                                 next
                                   case False
                                   then have f17: "(fst i) \<in>
                                   {
                                   bicc_type BE,bicc_type BNE,bicc_type BGU,
                                   bicc_type BLE,
               bicc_type BL,bicc_type BGE,bicc_type BNEG,bicc_type BG,
               bicc_type BCS,bicc_type BLEU,bicc_type BCC,bicc_type BA,
               bicc_type BN}"
                                   using f16 by auto
                                   then show ?thesis using f1
                                   proof (cases "(fst i) \<in> {bicc_type BE,
                                     bicc_type BNE,bicc_type BGU,
                                   bicc_type BLE,
               bicc_type BL,bicc_type BGE,bicc_type BNEG,bicc_type BG,
               bicc_type BCS,bicc_type BLEU,bicc_type BCC,bicc_type BA
               }")
                                     case True
                                     then show ?thesis using f1
                                     apply dispatch_instr_proof1
                                     apply auto
                                                by (auto simp add: branch_instr_result)
                                   next
                                     case False
                                     then have f18: "(fst i) \<in> {bicc_type BN}" 
                                     using f17 by auto
                                     then show ?thesis using f1
                                     apply dispatch_instr_proof1
                                     apply auto
                                     by (auto simp add: branch_instr_result)
                                   qed
                                 qed
                               qed
                             qed
                           qed
                         qed
                       qed
                     qed
                   qed
                 qed
               qed
             qed
           qed
         qed
       qed
      qed
   qed
 next
   case False
   then show ?thesis
   apply (simp add: dispatch_instruction_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def)
   apply (simp add: Let_def)
   by (simp add: returnOk_def return_def)
 qed
 
 lemma dispatch_instr_result_rett: 
 assumes a1: "(fst i) = ctrl_type RETT \<and> (get_ET (cpu_reg_val PSR s) \<noteq> 1 \<and>
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) \<noteq> 0 \<and>
   (get_WIM_bit (nat (((uint (get_CWP (cpu_reg_val PSR s))) + 1) mod NWINDOWS)) 
     (cpu_reg_val WIM s)) = 0 \<and>
-  (bitAND (get_addr (snd i) s) (0b00000000000000000000000000000011::word32)) = 0)"
+  ((AND) (get_addr (snd i) s) (0b00000000000000000000000000000011::word32)) = 0)"
 shows "snd (dispatch_instruction i s) = False"
 proof (cases "get_trap_set s = {}")
   case True
   then show ?thesis using a1
   apply (simp add: dispatch_instruction_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   by (simp add: rett_instr_result)
 next
   case False
   then show ?thesis using a1
   apply (simp add: dispatch_instruction_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   by (simp add: return_def)
 qed
 
 lemma execute_instr_sub1_result: "snd (execute_instr_sub1 i s) = False"
 proof (cases "get_trap_set s = {} \<and> (fst i) \<in> {call_type CALL,ctrl_type RETT,
   ctrl_type JMPL}")
   case True
   then show ?thesis 
   apply (simp add: execute_instr_sub1_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def)
   apply (simp add: write_cpu_def simpler_modify_def)
   apply auto
      by (auto simp add: return_def)
 next
   case False
   then show ?thesis
   apply (simp add: execute_instr_sub1_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def)
   apply (simp add: write_cpu_def simpler_modify_def)
   by (auto simp add: return_def)
 qed
 
 lemma next_match : "snd (execute_instruction () s) = False \<Longrightarrow>
   NEXT s = Some (snd (fst (execute_instruction () s)))"
 apply (simp add: NEXT_def)
 by (simp add: case_prod_unfold)
 
 lemma exec_ss1 : "\<exists>s'. (execute_instruction () s = (s', False)) \<Longrightarrow> 
   \<exists>s''. (execute_instruction() s = (s'', False))"
 proof -
   assume "\<exists>s'. (execute_instruction () s = (s', False))"
   hence "(snd (execute_instruction() s)) = False" 
          by (auto simp add: execute_instruction_def case_prod_unfold)         
   hence "(execute_instruction() s) = 
         ((fst (execute_instruction() s)),False)"
          by (metis (full_types) prod.collapse) 
   hence "\<exists>s''. (execute_instruction() s = (s'', False))" 
         by blast
   thus ?thesis by assumption
 qed
 
 lemma exec_ss2 : "snd (execute_instruction() s) = False \<Longrightarrow>
   snd (execute_instruction () s) = False"
 proof -
   assume "snd (execute_instruction() s) = False"
   hence "snd (execute_instruction () s) = False" 
     by (auto simp add:execute_instruction_def)
   thus ?thesis by assumption
 qed
 
 lemma good_context_1 : "good_context s \<and> s' = s \<and>
   (get_trap_set s') \<noteq> {} \<and> (reset_trap_val s') = False \<and> get_ET (cpu_reg_val PSR s') = 0 
   \<Longrightarrow> False"
 proof -
   assume asm: "good_context s \<and> s' = s \<and>
     (get_trap_set s') \<noteq> {} \<and> (reset_trap_val s') = False \<and> get_ET (cpu_reg_val PSR s') = 0"
   then have  "(get_trap_set s') \<noteq> {} \<and> (reset_trap_val s') = False \<and> 
   get_ET (cpu_reg_val PSR s') = 0 \<Longrightarrow> False" 
     by (simp add: good_context_def get_ET_def cpu_reg_val_def) 
   then show ?thesis using asm by auto 
 qed
 
 lemma fetch_instr_result_1 : "\<not> (\<exists>e. fetch_instruction s' = Inl e) \<Longrightarrow>
   (\<exists>v. fetch_instruction s' = Inr v)"
 by (meson sumE)
 
 lemma fetch_instr_result_2 : "(\<exists>v. fetch_instruction s' = Inr v) \<Longrightarrow>
   \<not> (\<exists>e. fetch_instruction s' = Inl e)"
 by force
 
 lemma fetch_instr_result_3 : "(\<exists>e. fetch_instruction s' = Inl e) \<Longrightarrow>
   \<not> (\<exists>v. fetch_instruction s' = Inr v)"
 by auto
 
 lemma decode_instr_result_1 : 
 "\<not>(\<exists>v2. ((decode_instruction v1)::(Exception list + instruction)) = Inr v2) \<Longrightarrow>
   (\<exists>e. ((decode_instruction v1)::(Exception list + instruction)) = Inl e)"
 by (meson sumE)
 
 lemma decode_instr_result_2 : 
 "(\<exists>e. ((decode_instruction v1)::(Exception list + instruction)) = Inl e) \<Longrightarrow>
   \<not>(\<exists>v2. ((decode_instruction v1)::(Exception list + instruction)) = Inr v2)"
 by force
 
 lemma decode_instr_result_3 : "x = decode_instruction v1 \<and> y = decode_instruction v2 
   \<and> v1 = v2 \<Longrightarrow> x = y"
 by auto
 
 lemma decode_instr_result_4 : 
 "\<not> (\<exists>e. ((decode_instruction v1)::(Exception list + instruction)) = Inl e) \<Longrightarrow>
   (\<exists>v2. ((decode_instruction v1)::(Exception list + instruction)) = Inr v2)"
 by (meson sumE)
 
 lemma good_context_2 : 
 "good_context (s::(('a::len0) sparc_state)) \<and> 
  fetch_instruction (delayed_pool_write s) = Inr v1  \<and> 
  \<not>(\<exists>v2. (decode_instruction v1::(Exception list + instruction)) = Inr v2) 
  \<Longrightarrow> False"
 proof -
   assume "good_context s \<and> 
     fetch_instruction (delayed_pool_write s) = Inr v1 \<and> 
     \<not>(\<exists>v2. ((decode_instruction v1)::(Exception list + instruction)) = Inr v2)"
   hence fact1: "good_context s \<and> 
     fetch_instruction (delayed_pool_write s) = Inr v1 \<and> 
     (\<exists>e. ((decode_instruction v1)::(Exception list + instruction)) = Inl e)" 
     using decode_instr_result_1 by auto
   hence fact2: "\<not>(\<exists>e. fetch_instruction (delayed_pool_write s) = Inl e)" 
     using fetch_instr_result_2 by auto
   then have "fetch_instruction (delayed_pool_write s) = Inr v1 \<and> 
             (\<exists>e. ((decode_instruction v1)::(Exception list + instruction)) = Inl e) 
             \<Longrightarrow> False"
     proof (cases "(get_trap_set s) \<noteq> {} \<and> (reset_trap_val s) = False \<and> 
       get_ET (cpu_reg_val PSR s) = 0") 
       case True 
       from this fact1 show ?thesis using good_context_1 by blast
     next
       case False
         then have fact3: "(get_trap_set s) = {} \<or> (reset_trap_val s) \<noteq> False 
         \<or> get_ET (cpu_reg_val PSR s) \<noteq> 0"
           by auto
         then show ?thesis 
           using fact1 decode_instr_result_3
           by (metis (no_types, lifting) good_context_def sum.case(1) sum.case(2))        
     qed
   thus ?thesis using fact1 by auto
 qed
 
 lemma good_context_3 : 
 "good_context (s::(('a::len0) sparc_state)) \<and> 
  s'' = delayed_pool_write s \<and>
  fetch_instruction s'' = Inr v1  \<and> 
  (decode_instruction v1::(Exception list + instruction)) = Inr v2 \<and>
  annul_val s'' = False \<and> supported_instruction (fst v2) = False
  \<Longrightarrow> False"
 proof -
   assume asm: "good_context (s::(('a::len0) sparc_state)) \<and> 
   s'' = delayed_pool_write s \<and>
   fetch_instruction s'' = Inr v1  \<and> 
   (decode_instruction v1::(Exception list + instruction)) = Inr v2 \<and>
   annul_val s'' = False \<and> supported_instruction (fst v2) = False"
   then have "annul_val s'' = False \<and> supported_instruction (fst v2) = False
     \<Longrightarrow> False"
     proof (cases "(get_trap_set s) \<noteq> {} \<and> (reset_trap_val s) = False \<and> 
       get_ET (cpu_reg_val PSR s) = 0")
       case True
       from this asm show ?thesis using good_context_1 by blast
     next 
       case False
       then have fact3: "(get_trap_set s) = {} \<or> (reset_trap_val s) \<noteq> False \<or> 
       get_ET (cpu_reg_val PSR s) \<noteq> 0"
         by auto
       thus ?thesis using asm by (auto simp add: good_context_def)
     qed
   thus ?thesis using asm by auto
 qed
 
 lemma good_context_4 : 
 "good_context (s::(('a::len0) sparc_state)) \<and> 
  s'' = delayed_pool_write s \<and>
  fetch_instruction s'' = Inr v1 \<and> 
  ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and>
  annul_val s'' = False \<and> 
  supported_instruction (fst v2) = True \<and> \<comment> \<open>This line is redundant\<close>
  (fst v2) = ctrl_type RETT \<and> get_ET (cpu_reg_val PSR s'') \<noteq> 1 \<and>
  ((ucast (get_S (cpu_reg_val PSR s'')))::word1) = 0
  \<Longrightarrow> False"
 proof -
   assume asm: "good_context (s::(('a::len0) sparc_state)) \<and> 
   s'' = delayed_pool_write s \<and>
   fetch_instruction s'' = Inr v1 \<and> 
   ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and>
   annul_val s'' = False \<and> 
   supported_instruction (fst v2) = True \<and> \<comment> \<open>This line is redundant\<close>
   (fst v2) = ctrl_type RETT \<and> get_ET (cpu_reg_val PSR s'') \<noteq> 1 \<and>
   ((ucast (get_S (cpu_reg_val PSR s'')))::word1) = 0"
   then have "(fst v2) = ctrl_type RETT \<and> get_ET (cpu_reg_val PSR s'') \<noteq> 1 \<and>
   ((ucast (get_S (cpu_reg_val PSR s'')))::word1) = 0 \<Longrightarrow> False"
     proof (cases "(get_trap_set s) \<noteq> {} \<and> (reset_trap_val s) = False \<and> 
       get_ET (cpu_reg_val PSR s) = 0")
       case True
       from this asm show ?thesis using good_context_1 by blast
     next 
       case False
       then have fact3: "(get_trap_set s) = {} \<or> (reset_trap_val s) \<noteq> False \<or> 
       get_ET (cpu_reg_val PSR s) \<noteq> 0"
         by auto
       thus ?thesis using asm by (auto simp add: good_context_def)
     qed
   thus ?thesis using asm by auto
 qed
 
 lemma good_context_5 : 
 "good_context (s::(('a::len0) sparc_state)) \<and> 
  s'' = delayed_pool_write s \<and>
  fetch_instruction s'' = Inr v1 \<and> 
  ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and>
  annul_val s'' = False \<and> 
  supported_instruction (fst v2) = True \<and> \<comment> \<open>This line is redundant\<close>
  (fst v2) = ctrl_type RETT \<and> get_ET (cpu_reg_val PSR s'') \<noteq> 1 \<and>
  ((ucast (get_S (cpu_reg_val PSR s'')))::word1) \<noteq> 0 \<and>
  (get_WIM_bit (nat (((uint (get_CWP (cpu_reg_val PSR s''))) + 1) mod NWINDOWS)) 
   (cpu_reg_val WIM s'')) \<noteq> 0
  \<Longrightarrow> False"
 proof -
   assume asm: "good_context (s::(('a::len0) sparc_state)) \<and> 
   s'' = delayed_pool_write s \<and>
   fetch_instruction s'' = Inr v1 \<and> 
   ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and>
   annul_val s'' = False \<and> 
   supported_instruction (fst v2) = True \<and> \<comment> \<open>This line is redundant\<close>
   (fst v2) = ctrl_type RETT \<and> get_ET (cpu_reg_val PSR s'') \<noteq> 1 \<and>
   ((ucast (get_S (cpu_reg_val PSR s'')))::word1) \<noteq> 0 \<and>
   (get_WIM_bit (nat (((uint (get_CWP (cpu_reg_val PSR s''))) + 1) mod NWINDOWS)) 
     (cpu_reg_val WIM s'')) \<noteq> 0"
   then have "(fst v2) = ctrl_type RETT \<and> get_ET (cpu_reg_val PSR s'') \<noteq> 1 \<and>
   ((ucast (get_S (cpu_reg_val PSR s'')))::word1) \<noteq> 0 \<and>
   (get_WIM_bit (nat (((uint (get_CWP (cpu_reg_val PSR s''))) + 1) mod NWINDOWS)) 
     (cpu_reg_val WIM s'')) \<noteq> 0
   \<Longrightarrow> False"
     proof (cases "(get_trap_set s) \<noteq> {} \<and> (reset_trap_val s) = False \<and> 
       get_ET (cpu_reg_val PSR s) = 0")
       case True
       from this asm show ?thesis using good_context_1 by blast
     next 
       case False
       then have fact3: "(get_trap_set s) = {} \<or> (reset_trap_val s) \<noteq> False \<or>
       get_ET (cpu_reg_val PSR s) \<noteq> 0"
         by auto
       thus ?thesis using asm by (auto simp add: good_context_def)
     qed
   thus ?thesis using asm by auto
 qed
 
 lemma good_context_6 : 
 "good_context (s::(('a::len0) sparc_state)) \<and> 
  s'' = delayed_pool_write s \<and>
  fetch_instruction s'' = Inr v1 \<and> 
  ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and>
  annul_val s'' = False \<and> 
  supported_instruction (fst v2) = True \<and> \<comment> \<open>This line is redundant\<close>
  (fst v2) = ctrl_type RETT \<and> get_ET (cpu_reg_val PSR s'') \<noteq> 1 \<and>
  ((ucast (get_S (cpu_reg_val PSR s'')))::word1) \<noteq> 0 \<and>
  (get_WIM_bit (nat (((uint (get_CWP (cpu_reg_val PSR s''))) + 1) mod NWINDOWS)) 
   (cpu_reg_val WIM s'')) = 0 \<and>
- (bitAND (get_addr (snd v2) s'') (0b00000000000000000000000000000011::word32)) \<noteq> 0
+ ((AND) (get_addr (snd v2) s'') (0b00000000000000000000000000000011::word32)) \<noteq> 0
  \<Longrightarrow> False"
 proof -
   assume asm: "good_context (s::(('a::len0) sparc_state)) \<and> 
   s'' = delayed_pool_write s \<and>
   fetch_instruction s'' = Inr v1 \<and> 
   ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and>
   annul_val s'' = False \<and> 
   supported_instruction (fst v2) = True \<and> \<comment> \<open>This line is redundant\<close>
   (fst v2) = ctrl_type RETT \<and> get_ET (cpu_reg_val PSR s'') \<noteq> 1 \<and>
   ((ucast (get_S (cpu_reg_val PSR s'')))::word1) \<noteq> 0 \<and>
   (get_WIM_bit (nat (((uint (get_CWP (cpu_reg_val PSR s''))) + 1) mod NWINDOWS)) 
     (cpu_reg_val WIM s'')) = 0 \<and>
-  (bitAND (get_addr (snd v2) s'') (0b00000000000000000000000000000011::word32)) \<noteq> 0"
+  ((AND) (get_addr (snd v2) s'') (0b00000000000000000000000000000011::word32)) \<noteq> 0"
   then have "(fst v2) = ctrl_type RETT \<and> get_ET (cpu_reg_val PSR s'') \<noteq> 1 \<and>
   ((ucast (get_S (cpu_reg_val PSR s'')))::word1) \<noteq> 0 \<and>
   (get_WIM_bit (nat (((uint (get_CWP (cpu_reg_val PSR s''))) + 1) mod NWINDOWS)) 
     (cpu_reg_val WIM s'')) = 0 \<and>
-  (bitAND (get_addr (snd v2) s'') (0b00000000000000000000000000000011::word32)) \<noteq> 0
+  ((AND) (get_addr (snd v2) s'') (0b00000000000000000000000000000011::word32)) \<noteq> 0
   \<Longrightarrow> False"
     proof (cases "(get_trap_set s) \<noteq> {} \<and> (reset_trap_val s) = False \<and> 
       get_ET (cpu_reg_val PSR s) = 0")
       case True
       from this asm show ?thesis using good_context_1 by blast
     next 
       case False
       then have fact3: "(get_trap_set s) = {} \<or> (reset_trap_val s) \<noteq> False \<or>
       get_ET (cpu_reg_val PSR s) \<noteq> 0"
         by auto
       thus ?thesis using asm by (auto simp add: good_context_def)
     qed
   thus ?thesis using asm by auto
 qed
 
 lemma good_context_all : 
 "good_context (s::(('a::len0) sparc_state)) \<and> 
  s'' = delayed_pool_write s \<Longrightarrow>
  (get_trap_set s = {} \<or> (reset_trap_val s) \<noteq> False \<or> get_ET (cpu_reg_val PSR s) \<noteq> 0) \<and>
  ((\<exists>e. fetch_instruction s'' = Inl e) \<or> 
   (\<exists>v1 v2. fetch_instruction s'' = Inr v1 \<and> 
    ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and>
    (annul_val s'' = True \<or>
     (annul_val s'' = False \<and> 
      (\<forall>v1' v2'. fetch_instruction s'' = Inr v1' \<and> 
       ((decode_instruction v1')::(Exception list + instruction)) = Inr v2' \<longrightarrow>
       supported_instruction (fst v2') = True) \<and>
      ((fst v2) \<noteq> ctrl_type RETT \<or>
       ((fst v2) = ctrl_type RETT \<and> 
        (get_ET (cpu_reg_val PSR s'') = 1 \<or>
         (get_ET (cpu_reg_val PSR s'') \<noteq> 1 \<and>
         ((ucast (get_S (cpu_reg_val PSR s'')))::word1) \<noteq> 0 \<and>
         (get_WIM_bit (nat (((uint (get_CWP (cpu_reg_val PSR s''))) + 1) mod NWINDOWS)) 
           (cpu_reg_val WIM s'')) = 0 \<and>
-        (bitAND (get_addr (snd v2) s'') (0b00000000000000000000000000000011::word32)) = 0))))))))"
+        ((AND) (get_addr (snd v2) s'') (0b00000000000000000000000000000011::word32)) = 0))))))))"
 proof -
  assume asm: "good_context s \<and> s'' = delayed_pool_write s"
  from asm have "(get_trap_set s) \<noteq> {} \<and> (reset_trap_val s) = False \<and> 
  get_ET (cpu_reg_val PSR s) = 0 \<Longrightarrow> False"
   using good_context_1 by blast  
  hence fact1: "(get_trap_set s = {} \<or> (reset_trap_val s) \<noteq> False \<or> 
  get_ET (cpu_reg_val PSR s) \<noteq> 0)" by auto
  have fact2: "\<not>(\<exists>e. fetch_instruction s'' = Inl e) \<and> \<not> (\<exists>v1. fetch_instruction s'' = Inr v1) 
   \<Longrightarrow> False" using fetch_instr_result_1 by blast
  from asm have fact3: "\<exists>v1. fetch_instruction s'' = Inr v1 \<and>
   \<not>(\<exists>v2.((decode_instruction v1)::(Exception list + instruction)) = Inr v2)
   \<Longrightarrow> False"
   using good_context_2 by blast
  from asm have fact4: "\<exists>v1 v2. fetch_instruction s'' = Inr v1 \<and> 
   ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and>
   annul_val s'' = False \<and> supported_instruction (fst v2) = False
   \<Longrightarrow> False"
   using good_context_3 by blast
  from asm have fact5: "\<exists>v1 v2. fetch_instruction s'' = Inr v1 \<and> 
   ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and>
   annul_val s'' = False \<and> supported_instruction (fst v2) = True \<and>
   (fst v2) = ctrl_type RETT \<and> get_ET (cpu_reg_val PSR s'') \<noteq> 1 \<and>
   ((ucast (get_S (cpu_reg_val PSR s'')))::word1) = 0
   \<Longrightarrow> False"
   using good_context_4 by blast
  from asm have fact6: "\<exists>v1 v2. fetch_instruction s'' = Inr v1 \<and> 
   ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and>
   annul_val s'' = False \<and> supported_instruction (fst v2) = True \<and>
   (fst v2) = ctrl_type RETT \<and> get_ET (cpu_reg_val PSR s'') \<noteq> 1 \<and>
   ((ucast (get_S (cpu_reg_val PSR s'')))::word1) \<noteq> 0 \<and>
   (get_WIM_bit (nat (((uint (get_CWP (cpu_reg_val PSR s''))) + 1) mod NWINDOWS)) 
     (cpu_reg_val WIM s'')) \<noteq> 0
   \<Longrightarrow> False" 
   using good_context_5 by blast
  from asm have fact7: "\<exists>v1 v2. fetch_instruction s'' = Inr v1 \<and> 
   ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and>
   annul_val s'' = False \<and> supported_instruction (fst v2) = True \<and>
   (fst v2) = ctrl_type RETT \<and> get_ET (cpu_reg_val PSR s'') \<noteq> 1 \<and>
   ((ucast (get_S (cpu_reg_val PSR s'')))::word1) \<noteq> 0 \<and>
   (get_WIM_bit (nat (((uint (get_CWP (cpu_reg_val PSR s''))) + 1) mod NWINDOWS)) 
     (cpu_reg_val WIM s'')) = 0 \<and>
-  (bitAND (get_addr (snd v2) s'') (0b00000000000000000000000000000011::word32)) \<noteq> 0
+  ((AND) (get_addr (snd v2) s'') (0b00000000000000000000000000000011::word32)) \<noteq> 0
   \<Longrightarrow> False"
     using good_context_6 by blast
  from asm show ?thesis 
   proof (cases "(\<exists>e. fetch_instruction s'' = Inl e)")
     case True
     then show ?thesis using fact1 by auto
   next 
     case False
     then have fact8: "\<exists>v1. fetch_instruction s'' = Inr v1 \<and> 
     (\<exists>v2.((decode_instruction v1)::(Exception list + instruction)) = Inr v2)"
       using fact2 fact3 by auto
     then show ?thesis 
       proof (cases "annul_val s'' = True")
         case True
         then show ?thesis using fact1 fact8 by auto
       next 
         case False
         then have fact9: "\<exists>v1 v2. fetch_instruction s'' = Inr v1 \<and> 
         ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and>
         annul_val s'' = False \<and> supported_instruction (fst v2) = True"
           using fact4 fact8 by blast
         then show ?thesis 
           proof (cases "\<exists>v1 v2. fetch_instruction s'' = Inr v1 \<and> 
             ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and>
             (fst v2) \<noteq> ctrl_type RETT")
             case True
             then show ?thesis using fact1 fact9 by auto  
           next
             case False
             then have fact10: "\<exists>v1 v2. fetch_instruction s'' = Inr v1 \<and> 
             ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and>
             annul_val s'' = False \<and> supported_instruction (fst v2) = True \<and> 
               (fst v2) = ctrl_type RETT"
               using fact9 by auto
             then show ?thesis 
               proof (cases "get_ET (cpu_reg_val PSR s'') = 1")
                 case True
                 then show ?thesis using fact1 fact9 by auto
               next
                 case False
                 then have fact11: "get_ET (cpu_reg_val PSR s'') \<noteq> 1 \<and> 
                 ((ucast (get_S (cpu_reg_val PSR s'')))::word1) \<noteq> 0"
                   using fact10 fact5 by auto
                 then have fact12: "(get_WIM_bit (nat (((uint (get_CWP (cpu_reg_val PSR s''))) + 1) 
                   mod NWINDOWS)) (cpu_reg_val WIM s'')) = 0" 
                   using fact10 fact6 by auto
                 then have fact13: "\<exists>v1 v2. fetch_instruction s'' = Inr v1 \<and> 
                 ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and>
-                (bitAND (get_addr (snd v2) s'') (0b00000000000000000000000000000011::word32)) = 0"
+                ((AND) (get_addr (snd v2) s'') (0b00000000000000000000000000000011::word32)) = 0"
                   using fact10 fact11 fact7 by blast
                 thus ?thesis using fact1 fact10 fact11 fact12 by auto
               qed
           qed
       qed
   qed
 qed
 
 lemma select_trap_result1 : "(reset_trap_val s) = True \<Longrightarrow>
   snd (select_trap() s) = False"   
 apply (simp add: select_trap_def exec_gets return_def)
 by (simp add: bind_def  h1_def h2_def simpler_modify_def)
 
 lemma select_trap_result2 : 
 assumes a1: "\<not>(reset_trap_val s = False \<and> get_ET (cpu_reg_val PSR s) = 0)"
 shows  "snd (select_trap() s) = False"
 proof (cases "reset_trap_val s = True") 
   case True
   then show ?thesis using select_trap_result1 
   by blast
 next
   case False
   then have f1: "reset_trap_val s = False \<and> get_ET (cpu_reg_val PSR s) \<noteq> 0"
     using a1 by auto
     then show ?thesis
     proof (cases "data_store_error \<in> get_trap_set s")
       case True
       then show ?thesis using f1
       by select_trap_proof0
     next
       case False
       then have f2: "data_store_error \<notin> get_trap_set s" by auto
       then show ?thesis 
       proof (cases "instruction_access_error \<in> get_trap_set s")
         case True
         then show ?thesis using f1 f2
         by select_trap_proof0
       next
         case False
         then have f3: "instruction_access_error \<notin> get_trap_set s" by auto
         then show ?thesis 
         proof (cases "r_register_access_error \<in> get_trap_set s")
           case True
           then show ?thesis using f1 f2 f3
           by select_trap_proof0
         next
           case False
           then have f4: "r_register_access_error \<notin> get_trap_set s" by auto
           then show ?thesis 
           proof (cases "instruction_access_exception \<in> get_trap_set s")
             case True
             then show ?thesis using f1 f2 f3 f4
             by select_trap_proof0
           next
             case False
             then have f5: "instruction_access_exception \<notin> get_trap_set s" by auto
             then show ?thesis 
             proof (cases "privileged_instruction \<in> get_trap_set s")
               case True
               then show ?thesis using f1 f2 f3 f4 f5
               by select_trap_proof0
             next  
               case False
               then have f6: "privileged_instruction \<notin> get_trap_set s" by auto
               then show ?thesis 
               proof (cases "illegal_instruction \<in> get_trap_set s")
                 case True
                 then show ?thesis using f1 f2 f3 f4 f5 f6
                 by select_trap_proof0
               next
                 case False
                 then have f7: "illegal_instruction \<notin> get_trap_set s" by auto
                 then show ?thesis
                 proof (cases "fp_disabled \<in> get_trap_set s")
                   case True
                   then show ?thesis using f1 f2 f3 f4 f5 f6 f7
                   by select_trap_proof0
                 next
                   case False
                   then have f8: "fp_disabled \<notin> get_trap_set s" by auto
                   then show ?thesis 
                   proof (cases "cp_disabled \<in> get_trap_set s")
                     case True
                     then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8
                     by select_trap_proof0
                   next
                     case False
                     then have f9: "cp_disabled \<notin> get_trap_set s" by auto
                     then show ?thesis 
                     proof (cases "unimplemented_FLUSH \<in> get_trap_set s")
                       case True
                       then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8 f9
                       by select_trap_proof0
                     next
                       case False
                       then have f10: "unimplemented_FLUSH \<notin> get_trap_set s" by auto
                       then show ?thesis 
                       proof (cases "window_overflow \<in> get_trap_set s")
                         case True
                         then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8 f9 f10
                         by select_trap_proof0
                       next 
                         case False
                         then have f11: "window_overflow \<notin> get_trap_set s" by auto
                         then show ?thesis 
                         proof (cases "window_underflow \<in> get_trap_set s")
                           case True
                           then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11
                           by select_trap_proof0
                         next
                           case False
                           then have f12: "window_underflow \<notin> get_trap_set s" by auto
                           then show ?thesis 
                           proof (cases "mem_address_not_aligned \<in> get_trap_set s")
                             case True
                             then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12
                             by select_trap_proof0
                           next
                             case False
                             then have f13: "mem_address_not_aligned \<notin> get_trap_set s" by auto
                             then show ?thesis 
                             proof (cases "fp_exception \<in> get_trap_set s")
                               case True
                               then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13
                               by select_trap_proof0
                             next
                               case False
                               then have f14: "fp_exception \<notin> get_trap_set s" by auto
                               then show ?thesis 
                               proof (cases "cp_exception \<in> get_trap_set s")
                                 case True
                                 then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13
                                 f14 
                                 by select_trap_proof0
                               next
                                 case False
                                 then have f15: "cp_exception \<notin> get_trap_set s" by auto
                                 then show ?thesis 
                                 proof (cases "data_access_error \<in> get_trap_set s")
                                   case True
                                   then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13
                                 f14 f15 
                                 by select_trap_proof0
                                 next
                                   case False
                                   then have f16: "data_access_error \<notin> get_trap_set s" by auto
                                   then show ?thesis 
                                   proof (cases "data_access_exception \<in> get_trap_set s")
                                     case True
                                     then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 
                                     f13 f14 f15 f16
                                     by select_trap_proof0
                                   next
                                     case False
                                     then have f17: "data_access_exception \<notin> get_trap_set s" by auto
                                     then show ?thesis 
                                     proof (cases "tag_overflow \<in> get_trap_set s")
                                       case True
                                       then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 
                                       f13 f14 f15 f16 f17
                                       by select_trap_proof0
                                     next
                                       case False
                                       then have f18: "tag_overflow \<notin> get_trap_set s" by auto
                                       then show ?thesis 
                                       proof (cases "division_by_zero \<in> get_trap_set s")
                                         case True
                                         then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 
                                         f12 f13 f14 f15 f16 f17 f18 
                                         by select_trap_proof0
                                       next
                                         case False
                                         then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 
                                         f12 f13 f14 f15 f16 f17 f18
                                         apply (simp add: select_trap_def exec_gets return_def)
                                         apply (simp add: DetMonad.bind_def h1_def h2_def simpler_modify_def)
                                         apply (simp add: return_def simpler_gets_def)
                                         apply (simp add: case_prod_unfold)
                                         apply (simp add: return_def)
                                         apply (simp add: write_cpu_tt_def write_cpu_def)
                                         by (simp add: simpler_gets_def bind_def h1_def h2_def simpler_modify_def)
                                       qed
                                     qed
                                   qed
                                 qed
                               qed
                             qed
                           qed
                         qed
                       qed
                     qed
                   qed
                 qed
               qed
             qed
           qed
         qed
       qed
     qed
 qed
 
 lemma emp_trap_set_err_mode : "err_mode_val s = err_mode_val (emp_trap_set s)"
 by (auto simp add: emp_trap_set_def err_mode_val_def)
 
 lemma write_cpu_tt_err_mode : "err_mode_val s = err_mode_val (snd (fst (write_cpu_tt w s)))"
 apply (simp add: write_cpu_tt_def err_mode_val_def write_cpu_def)  
 apply (simp add: exec_gets return_def)
 apply (simp add: bind_def simpler_modify_def)
 by (simp add: cpu_reg_mod_def)
 
 lemma select_trap_monad : "snd (select_trap() s) = False \<Longrightarrow> 
   err_mode_val s = err_mode_val (snd (fst (select_trap () s)))"
 proof -
   assume a1: "snd (select_trap() s) = False"
   then have f0: "reset_trap_val s = False \<and> get_ET (cpu_reg_val PSR s) = 0 \<Longrightarrow> False" 
     apply (simp add: select_trap_def exec_gets return_def)
     apply (simp add: bind_def h1_def h2_def simpler_modify_def)
     by (simp add: fail_def split_def)  
   then show ?thesis
     proof (cases "reset_trap_val s = True")
       case True
       from a1 f0 this show ?thesis 
       apply (simp add: select_trap_def exec_gets return_def)
       apply (simp add: bind_def h1_def h2_def simpler_modify_def)
       by (simp add: emp_trap_set_def err_mode_val_def)
     next
       case False
       then have f1: "reset_trap_val s = False \<and> get_ET (cpu_reg_val PSR s) \<noteq> 0" using f0 by auto
       then show ?thesis using f1 a1
       proof (cases "data_store_error \<in> get_trap_set s")
         case True
         then show ?thesis using f1 a1
         by select_trap_proof1
       next 
         case False
         then have f2: "data_store_error \<notin> get_trap_set s" by auto
         then show ?thesis 
         proof (cases "instruction_access_error \<in> get_trap_set s")
           case True
           then show ?thesis using f1 f2 a1
           by select_trap_proof1
         next
           case False
           then have f3: "instruction_access_error \<notin> get_trap_set s" by auto
           then show ?thesis 
           proof (cases "r_register_access_error \<in> get_trap_set s")
             case True
             then show ?thesis using f1 f2 f3 a1
             by select_trap_proof1
           next
             case False
             then have f4: "r_register_access_error \<notin> get_trap_set s" by auto
             then show ?thesis 
             proof (cases "instruction_access_exception \<in> get_trap_set s")
               case True
               then show ?thesis using f1 f2 f3 f4 a1
               by select_trap_proof1
             next
               case False
               then have f5: "instruction_access_exception \<notin> get_trap_set s" by auto
               then show ?thesis 
               proof (cases "privileged_instruction \<in> get_trap_set s")
                 case True
                 then show ?thesis using f1 f2 f3 f4 f5 a1
                 by select_trap_proof1
               next  
                 case False
                 then have f6: "privileged_instruction \<notin> get_trap_set s" by auto
                 then show ?thesis 
                 proof (cases "illegal_instruction \<in> get_trap_set s")
                   case True
                   then show ?thesis using f1 f2 f3 f4 f5 f6 a1
                   by select_trap_proof1
                 next
                   case False
                   then have f7: "illegal_instruction \<notin> get_trap_set s" by auto
                   then show ?thesis
                   proof (cases "fp_disabled \<in> get_trap_set s")
                     case True
                     then show ?thesis using f1 f2 f3 f4 f5 f6 f7 a1
                     by select_trap_proof1
                   next
                     case False
                     then have f8: "fp_disabled \<notin> get_trap_set s" by auto
                     then show ?thesis 
                     proof (cases "cp_disabled \<in> get_trap_set s")
                       case True
                       then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8 a1
                       by select_trap_proof1
                     next
                       case False
                       then have f9: "cp_disabled \<notin> get_trap_set s" by auto
                       then show ?thesis 
                       proof (cases "unimplemented_FLUSH \<in> get_trap_set s")
                         case True
                         then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8 f9 a1
                         by select_trap_proof1
                       next
                         case False
                         then have f10: "unimplemented_FLUSH \<notin> get_trap_set s" by auto
                         then show ?thesis 
                         proof (cases "window_overflow \<in> get_trap_set s")
                           case True
                           then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 a1
                           by select_trap_proof1
                         next 
                           case False
                           then have f11: "window_overflow \<notin> get_trap_set s" by auto
                           then show ?thesis 
                           proof (cases "window_underflow \<in> get_trap_set s")
                             case True
                             then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 a1
                             by select_trap_proof1
                           next
                             case False
                             then have f12: "window_underflow \<notin> get_trap_set s" by auto
                             then show ?thesis 
                             proof (cases "mem_address_not_aligned \<in> get_trap_set s")
                               case True
                               then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 a1
                               by select_trap_proof1
                             next
                               case False
                               then have f13: "mem_address_not_aligned \<notin> get_trap_set s" by auto
                               then show ?thesis 
                               proof (cases "fp_exception \<in> get_trap_set s")
                                 case True
                                 then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13
                                 a1
                                 by select_trap_proof1
                               next
                                 case False
                                 then have f14: "fp_exception \<notin> get_trap_set s" by auto
                                 then show ?thesis 
                                 proof (cases "cp_exception \<in> get_trap_set s")
                                   case True
                                   then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13
                                   f14 a1
                                   by select_trap_proof1
                                 next
                                   case False
                                   then have f15: "cp_exception \<notin> get_trap_set s" by auto
                                   then show ?thesis 
                                   proof (cases "data_access_error \<in> get_trap_set s")
                                     case True
                                     then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13
                                     f14 f15 a1
                                     by select_trap_proof1
                                   next
                                     case False
                                     then have f16: "data_access_error \<notin> get_trap_set s" by auto
                                     then show ?thesis 
                                     proof (cases "data_access_exception \<in> get_trap_set s")
                                       case True
                                       then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 
                                       f13 f14 f15 f16 a1
                                       by select_trap_proof1
                                     next
                                       case False
                                       then have f17: "data_access_exception \<notin> get_trap_set s" by auto
                                       then show ?thesis 
                                       proof (cases "tag_overflow \<in> get_trap_set s")
                                         case True
                                         then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 
                                         f13 f14 f15 f16 f17 a1
                                         by select_trap_proof1
                                       next
                                         case False
                                         then have f18: "tag_overflow \<notin> get_trap_set s" by auto
                                         then show ?thesis 
                                         proof (cases "division_by_zero \<in> get_trap_set s")
                                           case True
                                           then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 
                                           f12 f13 f14 f15 f16 f17 f18 a1
                                           by select_trap_proof1
                                         next
                                           case False
                                           then show ?thesis using f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 
                                           f12 f13 f14 f15 f16 f17 f18 a1
                                           apply (simp add: select_trap_def exec_gets return_def)
                                           apply (simp add: bind_def h1_def h2_def simpler_modify_def)
                                           apply (simp add: return_def simpler_gets_def)
                                           apply (simp add: emp_trap_set_def err_mode_val_def
                                             cpu_reg_mod_def)
                                           apply (simp add: case_prod_unfold)
                                           apply (simp add: return_def)
                                           apply clarsimp                                          
                                           apply (simp add: write_cpu_tt_def write_cpu_def write_tt_def)
                                           apply (simp add: simpler_gets_def bind_def h1_def h2_def)
                                           apply (simp add: simpler_modify_def)
                                           by (simp add: cpu_reg_val_def cpu_reg_mod_def)
                                         qed
                                       qed
                                     qed
                                   qed
                                 qed
                               qed
                             qed
                           qed
                         qed
                       qed
                     qed
                   qed
                 qed
               qed
             qed
           qed
         qed
       qed
     qed
 qed
 
 lemma exe_trap_st_pc_result : "snd (exe_trap_st_pc() s) = False"
 proof (cases "annul_val s = True")
   case True
   then show ?thesis 
   apply (simp add: exe_trap_st_pc_def get_curr_win_def)
   apply (simp add: exec_gets return_def)
   apply (simp add: DetMonad.bind_def h1_def h2_def)
   by (simp add: set_annul_def write_reg_def simpler_modify_def)
 next
   case False
   then show ?thesis
   apply (simp add: exe_trap_st_pc_def get_curr_win_def)
   apply (simp add: exec_gets return_def)
   apply (simp add: DetMonad.bind_def h1_def h2_def)
   by (simp add: write_reg_def simpler_modify_def)
 qed
 
 lemma exe_trap_wr_pc_result : "snd (exe_trap_wr_pc() s) = False"
 proof (cases "reset_trap_val s = True")
   case True
   then show ?thesis 
   apply (simp add: exe_trap_wr_pc_def get_curr_win_def)
   apply (simp add: exec_gets return_def)
   apply (simp add: DetMonad.bind_def h1_def h2_def)
   apply (simp add: write_cpu_def simpler_modify_def)
   apply (simp add: simpler_gets_def)
   apply (simp add: cpu_reg_val_def update_S_def cpu_reg_mod_def reset_trap_val_def)
   apply (simp add: write_cpu_def simpler_modify_def DetMonad.bind_def h1_def h2_def)
   apply (simp add: return_def)
   by (simp add: set_reset_trap_def simpler_modify_def DetMonad.bind_def h1_def h2_def return_def)
 next
   case False
   then show ?thesis
   apply (simp add: exe_trap_wr_pc_def get_curr_win_def)
   apply (simp add: exec_gets return_def)
   apply (simp add: DetMonad.bind_def h1_def h2_def)
   apply (simp add: write_cpu_def simpler_modify_def)
   apply (simp add: simpler_gets_def)
   apply (simp add: cpu_reg_val_def update_S_def cpu_reg_mod_def reset_trap_val_def)
   apply (simp add: write_cpu_def simpler_modify_def DetMonad.bind_def h1_def h2_def)
   by (simp add: return_def)
 qed
 
 lemma execute_trap_result : "\<not>(reset_trap_val s = False \<and> get_ET (cpu_reg_val PSR s) = 0) \<Longrightarrow>
   snd (execute_trap() s) = False"
 proof -
   assume "\<not>(reset_trap_val s = False \<and> get_ET (cpu_reg_val PSR s) = 0)"
   then have fact1: "snd (select_trap() s) = False" using select_trap_result2 by blast
   then show ?thesis 
     proof (cases "err_mode_val s = True")
       case True
       then show ?thesis using fact1 
         apply (simp add: execute_trap_def exec_gets return_def)
         apply (simp add: DetMonad.bind_def h1_def h2_def Let_def)
         apply (simp add: case_prod_unfold)
         by (simp add: in_gets return_def select_trap_monad simpler_gets_def)
     next 
       case False
       then show ?thesis using fact1 select_trap_monad
       apply (simp add: execute_trap_def exec_gets return_def)
       apply (simp add: DetMonad.bind_def h1_def h2_def)
       apply (simp add: case_prod_unfold)
       apply (simp add: simpler_gets_def)
       apply (auto simp add: select_trap_monad)
       apply (simp add: DetMonad.bind_def h1_def h2_def get_curr_win_def)
       apply (simp add: get_CWP_def cpu_reg_val_def)
       apply (simp add: simpler_gets_def return_def write_cpu_def)
       apply (simp add: simpler_modify_def DetMonad.bind_def h1_def h2_def)
       apply (simp add: exe_trap_st_pc_result)
       by (simp add: case_prod_unfold exe_trap_wr_pc_result)
     qed
 qed
 
 lemma execute_trap_result2 : "\<not>(reset_trap_val s = False \<and> get_ET (cpu_reg_val PSR s) = 0) \<Longrightarrow>
   snd (execute_trap() s) = False"
 using execute_trap_result
 by blast
 
 lemma exe_instr_all : 
 "good_context (s::(('a::len0) sparc_state)) \<Longrightarrow> 
   snd (execute_instruction() s) = False"
 proof -
   assume asm1: "good_context s"
   let ?s' = "delayed_pool_write s"
   from asm1 have f1 : "(get_trap_set s = {} \<or> (reset_trap_val s) \<noteq> False \<or> 
   get_ET (cpu_reg_val PSR s) \<noteq> 0) \<and>
   ((\<exists>e. fetch_instruction ?s' = Inl e) \<or> 
   (\<exists>v1 v2. fetch_instruction ?s' = Inr v1 \<and> 
    ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and>
    (annul_val ?s' = True \<or>
     (annul_val ?s' = False \<and> 
      (\<forall>v1' v2'. fetch_instruction ?s' = Inr v1' \<and> 
       ((decode_instruction v1')::(Exception list + instruction)) = Inr v2' \<longrightarrow>
       supported_instruction (fst v2') = True) \<and>
      ((fst v2) \<noteq> ctrl_type RETT \<or>
       ((fst v2) = ctrl_type RETT \<and> 
        (get_ET (cpu_reg_val PSR ?s') = 1 \<or>
         (get_ET (cpu_reg_val PSR ?s') \<noteq> 1 \<and>
         ((ucast (get_S (cpu_reg_val PSR ?s')))::word1) \<noteq> 0 \<and>
         (get_WIM_bit (nat (((uint (get_CWP (cpu_reg_val PSR ?s'))) + 1) mod NWINDOWS)) 
           (cpu_reg_val WIM ?s')) = 0 \<and>
-        (bitAND (get_addr (snd v2) ?s') (0b00000000000000000000000000000011::word32)) = 0))))))))"
+        ((AND) (get_addr (snd v2) ?s') (0b00000000000000000000000000000011::word32)) = 0))))))))"
        using good_context_all by blast
    from f1 have f2: "get_trap_set s \<noteq> {} \<Longrightarrow> 
    (reset_trap_val s) \<noteq> False \<or> get_ET (cpu_reg_val PSR s) \<noteq> 0" 
     by auto
    show ?thesis 
    proof (cases "get_trap_set s = {}")
     case True
     then have f3: "get_trap_set s = {}" by auto
     then show ?thesis
     proof (cases "exe_mode_val s = True")
       case True
       then have f4: "exe_mode_val s = True" by auto
       then show ?thesis 
       proof (cases "\<exists>e1. fetch_instruction ?s' = Inl e1")
         case True
         then show ?thesis using f3
         apply exe_proof_to_decode
         apply (simp add: raise_trap_def simpler_modify_def)
         by (simp add: bind_def h1_def h2_def return_def)
       next
         case False
         then have f5: "\<exists> v1. fetch_instruction ?s' = Inr v1" using fetch_instr_result_1 by blast
         then have f6: "\<exists>v1 v2. fetch_instruction ?s' = Inr v1 \<and> 
           ((decode_instruction v1)::(Exception list + instruction)) = Inr v2"
         using f1 fetch_instr_result_2 by blast
         then show ?thesis 
         proof (cases "annul_val ?s' = True")
           case True
           then show ?thesis using f3 f4 f6
           apply exe_proof_to_decode
           apply (simp add: set_annul_def annul_mod_def simpler_modify_def bind_def h1_def h2_def)
           apply (simp add: return_def simpler_gets_def)
           by (simp add: write_cpu_def simpler_modify_def)
         next
           case False
           then have f7: "\<exists>v1 v2. fetch_instruction ?s' = Inr v1 \<and> 
           ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and> 
           (\<forall>v1' v2'. fetch_instruction ?s' = Inr v1' \<and> 
           ((decode_instruction v1')::(Exception list +  instruction)) = Inr v2' \<longrightarrow>
           supported_instruction (fst v2') = True) \<and> annul_val ?s' = False"
           using f1 f6 fetch_instr_result_2 by auto
           then have f7': "\<exists>v1 v2. fetch_instruction ?s' = Inr v1 \<and> 
           ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and> 
           supported_instruction (fst v2) = True \<and> annul_val ?s' = False"
           by auto
           then show ?thesis 
           proof (cases "\<exists>v1 v2. fetch_instruction ?s' = Inr v1 \<and> 
           ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and> 
           (fst v2) = ctrl_type RETT")
             case True
             then have f8: "\<exists>v1 v2. fetch_instruction ?s' = Inr v1 \<and> 
             ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and> 
             (fst v2) = ctrl_type RETT" by auto
             then show ?thesis 
             proof (cases "get_trap_set ?s' = {}")
               case True
               then have f9: "get_trap_set ?s' = {}" by auto
               then show ?thesis 
               proof (cases "get_ET (cpu_reg_val PSR ?s') = 1")
                 case True
                 then have f10: "get_ET (cpu_reg_val PSR ?s') = 1" by auto
                 then show ?thesis 
                 proof (cases "((ucast (get_S (cpu_reg_val PSR ?s')))::word1) = 0")
                   case True
                   then show ?thesis using f3 f4 f7 f8 f9 f10
                   apply exe_proof_to_decode              
                   apply exe_proof_dispatch_rett
                   apply (simp add: raise_trap_def simpler_modify_def)
                   apply (auto simp add: execute_instr_sub1_result return_def)
                   by (simp add: case_prod_unfold)
                 next
                   case False
                   then show ?thesis using f3 f4 f7 f8 f9 f10
                   apply exe_proof_to_decode
                   apply exe_proof_dispatch_rett
                   apply (simp add: raise_trap_def simpler_modify_def)
                   apply (auto simp add: execute_instr_sub1_result return_def)
                   by (simp add: case_prod_unfold)
                 qed
               next
                 case False
                 then have f11: "\<exists>v1 v2. fetch_instruction ?s' = Inr v1 \<and> 
                 ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and>
                 annul_val ?s' = False \<and>
                 (fst v2) = ctrl_type RETT \<and>
                 (get_ET (cpu_reg_val PSR ?s') \<noteq> 1 \<and>
                 ((ucast (get_S (cpu_reg_val PSR ?s')))::word1) \<noteq> 0 \<and>
                 (get_WIM_bit (nat (((uint (get_CWP (cpu_reg_val PSR ?s'))) + 1) mod NWINDOWS)) 
                   (cpu_reg_val WIM ?s')) = 0 \<and>
-                (bitAND (get_addr (snd v2) ?s') (0b00000000000000000000000000000011::word32)) = 0)"
+                ((AND) (get_addr (snd v2) ?s') (0b00000000000000000000000000000011::word32)) = 0)"
                 using f1 fetch_instr_result_2 f7' f8 by auto
                 then show ?thesis using f3 f4
                 proof (cases "get_trap_set ?s' = {}")
                   case True
                   then show ?thesis using f3 f4 f11
                   apply (simp add: execute_instruction_def)
                   apply (simp add: simpler_gets_def bind_def h1_def h2_def simpler_modify_def)
                   apply clarsimp
                   apply (simp add: return_def)
                   apply (simp add: bind_def h1_def h2_def Let_def)
                   apply (simp add: case_prod_unfold)   
                   apply auto
                    apply (simp add: execute_instr_sub1_result)                
                   apply (simp add: dispatch_instruction_def)
                   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)  
                   by (simp add: rett_instr_result)
                 next
                   case False
                   then show ?thesis using f3 f4 f11
                   apply (simp add: execute_instruction_def)
                   apply (simp add: simpler_gets_def bind_def h1_def h2_def simpler_modify_def)
                   apply clarsimp
                   apply (simp add: return_def)
                   apply (simp add: bind_def h1_def h2_def)
                   apply (simp add: case_prod_unfold)   
                   apply (simp add: execute_instr_sub1_result)
                   apply (simp add: dispatch_instruction_def)
                   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
                   by (simp add: return_def)
                 qed             
               qed
             next
               case False
               then show ?thesis using f3 f4 f7 f8
               apply exe_proof_to_decode
               apply (simp add: dispatch_instruction_def)
               apply (simp add: simpler_gets_def bind_def h1_def h2_def)
               apply (simp add: case_prod_unfold)
               by (auto simp add: execute_instr_sub1_result return_def Let_def)
             qed
           next
             case False \<comment> \<open>Instruction is not \<open>RETT\<close>.\<close>
             then have "\<exists>v1 v2. fetch_instruction ?s' = Inr v1 \<and> 
             ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and> 
             (fst v2) \<noteq> ctrl_type RETT" using f7 by auto
             then have "\<exists>v1 v2. fetch_instruction ?s' = Inr v1 \<and> 
             ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and>
             (fst v2) \<noteq> ctrl_type RETT \<and>
             supported_instruction (fst v2) = True \<and> annul_val ?s' = False"
             using f7 by auto            
             then have "\<exists>v1 v2. fetch_instruction ?s' = Inr v1 \<and> 
             ((decode_instruction v1)::(Exception list + instruction)) = Inr v2 \<and>
             (fst v2) \<noteq> ctrl_type RETT \<and>
             supported_instruction (fst v2) = True \<and> annul_val ?s' = False \<and>
             snd (dispatch_instruction v2 ?s') = False"
             by (auto simp add: dispatch_instr_result)                   
             then show ?thesis using f3 f4
               apply exe_proof_to_decode
               apply (simp add: bind_def h1_def h2_def)
               apply (simp add: case_prod_unfold)
               by (simp add: execute_instr_sub1_result)            
           qed
         qed
       qed
     next
       case False
       then show ?thesis using f3
       apply (simp add: execute_instruction_def)
       by (simp add: exec_gets return_def)
     qed
    next
     case False
     then have "get_trap_set s \<noteq> {} \<and> 
     ((reset_trap_val s) \<noteq> False \<or> get_ET (cpu_reg_val PSR s) \<noteq> 0)" 
       using f2 by auto
     then show ?thesis
     apply (simp add: execute_instruction_def exec_gets)
     by (simp add: execute_trap_result2)
    qed
 qed
 
 lemma dispatch_fail: 
 "snd (execute_instruction() (s::(('a::len0) sparc_state))) = False \<and>
   get_trap_set s = {} \<and>
   exe_mode_val s \<and>
   fetch_instruction (delayed_pool_write s) = Inr v  \<and> 
   ((decode_instruction v)::(Exception list + instruction)) = Inl e
  \<Longrightarrow> False"
 using decode_instr_result_2
 apply (simp add: execute_instruction_def)
 apply (simp add: exec_gets bind_def)
 apply clarsimp
 apply (simp add: simpler_gets_def bind_def h1_def h2_def)
 apply (simp add: simpler_modify_def return_def)
 by (simp add: fail_def)
 
 lemma no_error : "good_context s \<Longrightarrow> snd (execute_instruction () s) = False"
 proof -
   assume "good_context s"
   hence "snd (execute_instruction() s) = False" 
     using exe_instr_all by auto
   hence "snd (execute_instruction () s) = False" by (simp add: exec_ss2)
   thus ?thesis by assumption
 qed
 
 theorem single_step : "good_context s \<Longrightarrow> NEXT s = Some (snd (fst (execute_instruction () s)))"
 by (simp add: no_error next_match)
 
 (*********************************************************************)
 
 section \<open>Privilege safty\<close>
 
 (*********************************************************************)
 
 text \<open>The following shows that, if the pre-state is under user mode,
   then after a singel step execution, the post-state is aslo under user mode.\<close>
 
 lemma write_cpu_pc_privilege: "s' = snd (fst (write_cpu w PC s)) \<and>
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0 \<Longrightarrow>
   ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 apply (simp add: write_cpu_def simpler_modify_def)
 apply (simp add: cpu_reg_mod_def)
 by (simp add: cpu_reg_val_def)
 
 lemma write_cpu_npc_privilege: "s' = snd (fst (write_cpu w nPC s)) \<and>
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0 \<Longrightarrow>
   ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 apply (simp add: write_cpu_def simpler_modify_def)
 apply (simp add: cpu_reg_mod_def)
 by (simp add: cpu_reg_val_def)
 
 lemma write_cpu_y_privilege: "s' = snd (fst (write_cpu w Y s)) \<and>
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0
   \<Longrightarrow> ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 apply (simp add: write_cpu_def simpler_modify_def)
 apply (simp add: cpu_reg_mod_def)
 by (simp add: cpu_reg_val_def)
 
 lemma cpu_reg_mod_y_privilege: "s' = cpu_reg_mod w Y s \<and>
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0
   \<Longrightarrow> ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 by (simp add: cpu_reg_mod_def cpu_reg_val_def)
 
 lemma cpu_reg_mod_asr_privilege: "s' = cpu_reg_mod w (ASR r) s \<and>
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0
   \<Longrightarrow> ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 by (simp add: cpu_reg_mod_def cpu_reg_val_def)
 
 lemma global_reg_mod_privilege: "s' = global_reg_mod w1 n w2 s \<and>
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0 \<Longrightarrow>
   ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 apply (induction n arbitrary:s)
  apply (clarsimp)
 apply (auto)
 apply (simp add: Let_def)
 by (simp add: cpu_reg_val_def)
 
 lemma out_reg_mod_privilege: "s' = out_reg_mod a w r s \<and>
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0 \<Longrightarrow>
   ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 apply (simp add: out_reg_mod_def Let_def)
 by (simp add: cpu_reg_val_def)
 
 lemma in_reg_mod_privilege: "s' = in_reg_mod a w r s \<and>
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0 \<Longrightarrow>
   ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 apply (simp add: in_reg_mod_def Let_def)
 by (simp add: cpu_reg_val_def)
 
 lemma user_reg_mod_privilege: 
 assumes a1: " s' = user_reg_mod d (w::(('a::len0) window_size)) r 
   (s::(('a::len0) sparc_state)) \<and> 
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 proof (cases "r = 0")
   case True
   then show ?thesis using a1
   by (simp add: user_reg_mod_def)  
 next
   case False
   then have f1: "r \<noteq> 0" by auto
   then show ?thesis
   proof (cases "0 < r \<and> r < 8")
     case True
     then show ?thesis using a1 f1
     apply (simp add: user_reg_mod_def)
     by (auto intro: global_reg_mod_privilege)
   next
     case False
     then have f2: "\<not>(0 < r \<and> r < 8)" by auto
     then show ?thesis 
     proof (cases "7 < r \<and> r < 16")
       case True
       then show ?thesis using a1 f1 f2
       apply (simp add: user_reg_mod_def)
       by (auto intro: out_reg_mod_privilege)
     next
       case False
       then have f3: "\<not> (7 < r \<and> r < 16)" by auto
       then show ?thesis
       proof (cases "15 < r \<and> r < 24")
         case True
         then show ?thesis using a1 f1 f2 f3
         apply (simp add: user_reg_mod_def)
         by (simp add: cpu_reg_val_def)
       next
         case False
         then show ?thesis using a1 f1 f2 f3
         apply (simp add: user_reg_mod_def)
         by (auto intro: in_reg_mod_privilege)
       qed
     qed
   qed
 qed
 
 lemma write_reg_privilege: "s' = snd (fst (write_reg w1 w2 w3 
   (s::(('a::len0) sparc_state)))) \<and>
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0 \<Longrightarrow>
   ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 apply (simp add: write_reg_def simpler_modify_def)
 by (auto intro: user_reg_mod_privilege)
 
 lemma set_annul_privilege: "s' = snd (fst (set_annul b s)) \<and>
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0 \<Longrightarrow>
   ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 apply (simp add: set_annul_def simpler_modify_def)
 apply (simp add: annul_mod_def write_annul_def)
 by (simp add: cpu_reg_val_def)
 
 lemma set_reset_trap_privilege: "s' = snd (fst (set_reset_trap b s)) \<and>
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0 \<Longrightarrow>
   ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 apply (simp add: set_reset_trap_def simpler_modify_def)
 apply (simp add: reset_trap_mod_def write_annul_def)
 by (simp add: cpu_reg_val_def)
 
 lemma empty_delayed_pool_write_privilege: "get_delayed_pool s = [] \<and>
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0 \<and>
   s' = delayed_pool_write s \<Longrightarrow> 
   ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 apply (simp add: delayed_pool_write_def)
 by (simp add: get_delayed_write_def delayed_write_all_def delayed_pool_rm_list_def)
 
 lemma raise_trap_privilege: 
 "((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0 \<and>
   s' = snd (fst (raise_trap t s)) \<Longrightarrow> 
   ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 apply (simp add: raise_trap_def)
 apply (simp add: simpler_modify_def add_trap_set_def)
 by (simp add: cpu_reg_val_def)
 
 lemma write_cpu_tt_privilege: "s' = snd (fst (write_cpu_tt w s)) \<and>
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0
   \<Longrightarrow> ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 apply (simp add: write_cpu_tt_def)
 apply (simp add: exec_gets)
 apply (simp add: write_cpu_def cpu_reg_mod_def write_tt_def)
 apply (simp add: simpler_modify_def)
 by (simp add: cpu_reg_val_def)
 
 lemma emp_trap_set_privilege: "s' = emp_trap_set s \<and>
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0
   \<Longrightarrow> ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 apply (simp add: emp_trap_set_def)
 by (simp add: cpu_reg_val_def)
 
 lemma sys_reg_mod_privilege: "s' = sys_reg_mod w r s 
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0
   \<Longrightarrow> ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 apply (simp add: sys_reg_mod_def)
 by (simp add: cpu_reg_val_def)
 
 lemma mem_mod_privilege: 
 assumes a1: "s' = mem_mod a1 a2 v s \<and>
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 proof (cases "(uint a1) = 8 \<or> (uint a1) = 10")
   case True
   then show ?thesis using a1
   apply (simp add: mem_mod_def)
   apply (simp add: Let_def)
   by (simp add: cpu_reg_val_def)
 next
   case False
   then have f1: "\<not>((uint a1) = 8 \<or> (uint a1) = 10)" by auto
   then show ?thesis 
   proof (cases "(uint a1) = 9 \<or> (uint a1) = 11")
     case True
     then show ?thesis using a1 f1
     apply (simp add: mem_mod_def)
     apply (simp add: Let_def)
     by (simp add: cpu_reg_val_def)
   next
     case False
     then show ?thesis using a1 f1
     apply (simp add: mem_mod_def)
     by (simp add: cpu_reg_val_def)
   qed
 qed
 
 lemma mem_mod_w32_privilege: "s' = mem_mod_w32 a1 a2 b d s \<and>
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0
   \<Longrightarrow> ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 apply (simp add: mem_mod_w32_def)
 apply (simp add: Let_def)
 by (auto intro: mem_mod_privilege)
 
 lemma add_instr_cache_privilege: "s' = add_instr_cache s addr y m \<Longrightarrow>
 ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0 \<Longrightarrow>
 ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 apply (simp add: add_instr_cache_def)
 apply (simp add: Let_def)
 by (simp add: icache_mod_def cpu_reg_val_def)
 
 lemma add_data_cache_privilege: "s' = add_data_cache s addr y m \<Longrightarrow>
 ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0 \<Longrightarrow>
 ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 apply (simp add: add_data_cache_def)
 apply (simp add: Let_def)
 by (simp add: dcache_mod_def cpu_reg_val_def)
 
 lemma memory_read_privilege: 
 assumes a1: "s' = snd (memory_read asi addr s) \<and>
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 proof (cases "uint asi = 1")
   case True
   then show ?thesis using a1 
   apply (simp add: memory_read_def)
   by (simp add: Let_def)
 next
   case False
   then have f1: "uint asi \<noteq> 1" by auto
   then show ?thesis  
   proof (cases "uint asi = 2")
     case True 
     then show ?thesis using a1 f1
     by (simp add: memory_read_def)    
   next
     case False
     then have f2: "uint asi \<noteq> 2" by auto
     then show ?thesis 
     proof (cases "uint asi \<in> {8,9}")
       case True
       then have f3: "uint asi \<in> {8,9}" by auto
       then show ?thesis
       proof (cases "load_word_mem s addr asi = None")
         case True
         then have f4: "load_word_mem s addr asi = None" by auto
         then show ?thesis 
         using a1 f1 f2 f3 f4
         by (simp add: memory_read_def)
       next
         case False
         then show ?thesis using a1 f1 f2 f3
         apply (simp add: memory_read_def)      
         apply auto
          apply (simp add: add_instr_cache_privilege)
         by (simp add: add_instr_cache_privilege)
       qed
     next
       case False
       then have f5: "uint asi \<notin> {8, 9}" by auto
       then show ?thesis 
         proof (cases "uint asi \<in> {10,11}")
           case True
           then have f6: "uint asi \<in> {10,11}" by auto
           then show ?thesis
           proof (cases "load_word_mem s addr asi = None")
             case True
             then have f7: "load_word_mem s addr asi = None" by auto
             then show ?thesis 
             using a1 f1 f2 f5 f6 f7
             by (simp add: memory_read_def)
           next
             case False
             then show ?thesis using a1 f1 f2 f5 f6
             apply (simp add: memory_read_def)      
             apply auto
              apply (simp add: add_data_cache_privilege)
             by (simp add: add_data_cache_privilege)
           qed
       next
         case False
         then have f8: "uint asi \<notin> {10,11}" by auto
         then show ?thesis
         proof (cases "uint asi = 13")
           case True
           then have f9: "uint asi = 13" by auto
           then show ?thesis 
           proof (cases "read_instr_cache s addr = None")
             case True
             then show ?thesis using a1 f1 f2 f5 f8 f9
             by (simp add: memory_read_def) 
           next
             case False
             then show ?thesis using a1 f1 f2 f5 f8 f9
             apply (simp add: memory_read_def)
             by auto
           qed
         next
           case False
           then have f10: "uint asi \<noteq> 13" by auto
           then show ?thesis 
           proof (cases "uint asi = 15")
             case True
             then show ?thesis using a1 f1 f2 f5 f8 f10
             apply (simp add: memory_read_def)
             apply (cases "read_data_cache s addr = None")
              by auto
           next
             case False
             then show ?thesis using a1 f1 f2 f5 f8 f10
             apply (simp add: memory_read_def) \<comment> \<open>The rest cases are easy.\<close>
             by (simp add: Let_def)
           qed
         qed
       qed      
     qed
   qed
 qed
 
 lemma get_curr_win_privilege: "s' = snd (fst (get_curr_win() s)) \<and>
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0
   \<Longrightarrow> ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 apply (simp add: get_curr_win_def)
 by (simp add: simpler_gets_def)
 
 lemma load_sub2_privilege: 
 assumes a1: "s' = snd (fst (load_sub2 addr asi r win w s))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 proof (cases "fst (memory_read asi (addr + 4)
                         (snd (fst (write_reg w win (r AND 30) s)))) =
                   None")
   case True
   then show ?thesis using a1
   apply (simp add: load_sub2_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   apply (simp add: case_prod_unfold)
   by (auto intro: raise_trap_privilege write_reg_privilege)
 next
   case False
   then show ?thesis using a1
   apply (simp add: load_sub2_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def)
   apply (simp add: case_prod_unfold)
   apply clarsimp
   apply (simp add: simpler_modify_def bind_def h1_def h2_def Let_def)
   by (auto intro: write_reg_privilege memory_read_privilege)
 qed
 
 lemma load_sub3_privilege: 
 assumes a1: "s' = snd (fst (load_sub3 instr curr_win rd asi address s))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 proof (cases "fst (memory_read asi address s) = None")
   case True
   then show ?thesis using a1
   apply (simp add: load_sub3_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def)
   apply (simp add: case_prod_unfold)
   by (auto intro: raise_trap_privilege)
 next
   case False
   then have f1: "fst (memory_read asi address s) \<noteq> None " by auto
   then show ?thesis 
   proof (cases "rd \<noteq> 0 \<and>
                           (fst instr = load_store_type LD \<or>
                            fst instr = load_store_type LDA \<or>
                            fst instr = load_store_type LDUH \<or>
                            fst instr = load_store_type LDSB \<or>
                            fst instr = load_store_type LDUB \<or>
                            fst instr = load_store_type LDUBA \<or>
                            fst instr = load_store_type LDSH \<or>
                            fst instr = load_store_type LDSHA \<or>
                            fst instr = load_store_type LDUHA \<or>
                            fst instr = load_store_type LDSBA)")
     case True
     then show ?thesis using a1 f1
     apply (simp add: load_sub3_def)
     apply (simp add: simpler_gets_def bind_def h1_def h2_def)
     apply (simp add: case_prod_unfold)
     apply clarsimp
     apply (simp add: simpler_modify_def bind_def h1_def h2_def Let_def)
     by (auto intro: write_reg_privilege memory_read_privilege)
   next 
     case False
     then show ?thesis using a1 f1
     apply (simp add: load_sub3_def)
     apply (simp add: simpler_gets_def bind_def h1_def h2_def)
     apply (simp add: case_prod_unfold)
     apply auto
      apply (simp add: simpler_modify_def bind_def h1_def h2_def)
      apply (auto intro: load_sub2_privilege memory_read_privilege)
     apply (simp add: simpler_modify_def bind_def h1_def h2_def)
     by (auto intro: load_sub2_privilege memory_read_privilege)
   qed
 qed
 
 lemma load_sub1_privilege: 
 assumes a1: "s' = snd (fst (load_sub1 instr rd s_val s))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 using a1
 apply (simp add: load_sub1_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 apply auto
                by (auto intro: get_curr_win_privilege raise_trap_privilege load_sub3_privilege)
 
 lemma load_instr_privilege: "s' = snd (fst (load_instr i s))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0
   \<Longrightarrow> ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 apply (simp add: load_instr_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def)
 apply (simp add: Let_def)
 apply clarsimp
 by (auto intro: get_curr_win_privilege raise_trap_privilege load_sub1_privilege)
 
 lemma store_barrier_pending_mod_privilege: "s' = store_barrier_pending_mod b s
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0
   \<Longrightarrow> ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 apply (simp add: store_barrier_pending_mod_def)
 apply (simp add: write_store_barrier_pending_def)
 by (simp add: cpu_reg_val_def)
 
 lemma store_word_mem_privilege: 
 assumes a1: "store_word_mem s addr data byte_mask asi = Some s' \<and> 
 ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 using a1 apply (simp add: store_word_mem_def)
 apply (case_tac "virt_to_phys addr (mmu s) (mem s) = None")
 apply auto
 apply (case_tac "mmu_writable (get_acc_flag b) asi")
 apply auto
 by (simp add: mem_mod_w32_privilege)
 
 lemma flush_instr_cache_privilege: "((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0 \<Longrightarrow>
 s' = flush_instr_cache s \<Longrightarrow>
 ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 apply (simp add: flush_instr_cache_def)
 by (simp add: cpu_reg_val_def)
 
 lemma flush_data_cache_privilege: "((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0 \<Longrightarrow>
 s' = flush_data_cache s \<Longrightarrow>
 ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 apply (simp add: flush_data_cache_def)
 by (simp add: cpu_reg_val_def)
 
 lemma flush_cache_all_privilege: "((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0 \<Longrightarrow>
 s' = flush_cache_all s \<Longrightarrow>
 ((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 apply (simp add: flush_cache_all_def)
 by (simp add: cpu_reg_val_def)
 
 lemma memory_write_asi_privilege: 
 assumes a1: "r = memory_write_asi asi addr byte_mask data s \<and>
   r = Some s' \<and>
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 proof (cases "uint asi = 1")
   case True
   then show ?thesis using a1
   apply (simp add: memory_write_asi_def)
   by (auto intro: store_word_mem_privilege)
 next
   case False
   then have f1: "uint asi \<noteq> 1" by auto
   then show ?thesis
   proof (cases "uint asi = 2")
     case True
     then have f01: "uint asi = 2" by auto 
     then show ?thesis 
     proof (cases "uint addr = 0")
       case True
       then show ?thesis using a1 f1 f01      
       apply (simp add: memory_write_asi_def)
       apply (simp add: ccr_flush_def)
       apply (simp add: Let_def)
       apply auto
          apply (metis flush_data_cache_privilege flush_instr_cache_privilege sys_reg_mod_privilege)
         apply (metis flush_instr_cache_privilege sys_reg_mod_privilege)
        apply (metis flush_data_cache_privilege sys_reg_mod_privilege)
       by (simp add: sys_reg_mod_privilege)
     next
       case False
       then show ?thesis using a1 f1 f01
       apply (simp add: memory_write_asi_def)
       apply clarsimp
       by (metis option.distinct(1) option.sel sys_reg_mod_privilege)      
     qed      
   next
     case False
     then have f2: "uint asi \<noteq> 2" by auto
     then show ?thesis
     proof (cases "uint asi \<in> {8,9}")
       case True
       then show ?thesis using a1 f1 f2
       apply (simp add: memory_write_asi_def)
       using store_word_mem_privilege add_instr_cache_privilege
       by blast    
     next
       case False
       then have f3: "uint asi \<notin> {8,9}" by auto
       then show ?thesis 
       proof (cases "uint asi \<in> {10,11}")
         case True
         then show ?thesis using a1 f1 f2 f3
         apply (simp add: memory_write_asi_def)
         using store_word_mem_privilege add_data_cache_privilege
         by blast 
       next
         case False
         then have f4: "uint asi \<notin> {10,11}" by auto
         then show ?thesis 
         proof (cases "uint asi = 13")
           case True
           then show ?thesis using a1 f1 f2 f3 f4
           apply (simp add: memory_write_asi_def)
           by (auto simp add: add_instr_cache_privilege)
         next
           case False
           then have f5: "uint asi \<noteq> 13" by auto
           then show ?thesis
           proof (cases "uint asi = 15")
             case True
             then show ?thesis using a1 f1 f2 f3 f4 f5
             apply (simp add: memory_write_asi_def)
             by (auto simp add: add_data_cache_privilege)
           next
             case False
             then have f6: "uint asi \<noteq> 15" by auto
             then show ?thesis
             proof (cases "uint asi = 16")
               case True
               then show ?thesis using a1
               apply (simp add: memory_write_asi_def)
               by (auto simp add: flush_instr_cache_privilege)
             next
               case False
               then have f7: "uint asi \<noteq> 16" by auto
               then show ?thesis
               proof (cases "uint asi = 17")
                 case True
                 then show ?thesis using a1
                 apply (simp add: memory_write_asi_def)
                 by (auto simp add: flush_data_cache_privilege)
               next
                 case False
                 then have f8: "uint asi \<noteq> 17" by auto
                 then show ?thesis
                 proof (cases "uint asi = 24")
                   case True
                   then show ?thesis using a1
                   apply (simp add: memory_write_asi_def)
                   by (auto simp add: flush_cache_all_privilege)
                 next
                   case False
                   then have f9: "uint asi \<noteq> 24" by auto
                   then show ?thesis
                   proof (cases "uint asi = 25")
                     case True
                     then show ?thesis using a1
                     apply (simp add: memory_write_asi_def)
                     apply (case_tac "mmu_reg_mod (mmu s) addr data = None")
                      apply auto
                     by (simp add: cpu_reg_val_def)
                   next
                     case False
                     then have f10: "uint asi \<noteq> 25" by auto
                     then show ?thesis
                     proof (cases "uint asi = 28")
                       case True
                       then show ?thesis using a1
                       apply (simp add: memory_write_asi_def)
                       by (auto simp add: mem_mod_w32_privilege)
                     next
                       case False \<comment> \<open>The remaining cases are easy.\<close>
                       then show ?thesis using a1 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10
                       apply (simp add: memory_write_asi_def)
                       apply (auto simp add: Let_def)
                       apply (case_tac "uint asi = 20 \<or> uint asi = 21")
                        by auto                  
                     qed
                   qed
                 qed
               qed
             qed
           qed
         qed
       qed
     qed
   qed
 qed
 
 lemma memory_write_privilege: 
 assumes a1: "r = memory_write asi addr byte_mask data 
   (s::(('a::len0) sparc_state)) \<and>
   r = Some s' \<and>
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR 
   (s'::(('a::len0) sparc_state)))))::word1) = 0"
 proof -
   have "\<forall>x. Some x \<noteq> None" by auto
   then have "r \<noteq> None" using a1
     by (simp add: \<open>r = memory_write asi addr byte_mask data s \<and> 
         r = Some s' \<and> ucast (get_S (cpu_reg_val PSR s)) = 0\<close>)  
   then have "\<exists>s''. r = Some (store_barrier_pending_mod False s'')" using a1
     by (metis (no_types, lifting) memory_write_def option.case_eq_if) 
   then have "\<exists>s''. s' = store_barrier_pending_mod False s''" using a1
     by blast    
   then have "\<exists>s''. memory_write_asi asi addr byte_mask data s = Some s'' \<and> 
              s' = store_barrier_pending_mod False s''"
     by (metis (no_types, lifting) assms memory_write_def not_None_eq option.case_eq_if option.sel)
   then show ?thesis using a1
     using memory_write_asi_privilege store_barrier_pending_mod_privilege by blast   
 qed
 
 lemma store_sub2_privilege: 
 assumes a1: "s' = snd (fst (store_sub2 instr curr_win rd asi address s))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 proof (cases "memory_write asi address (st_byte_mask instr address)
                         (st_data0 instr curr_win rd address s) s =
                        None")
   case True
   then show ?thesis using a1
   apply (simp add: store_sub2_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   apply (simp add: case_prod_unfold)
   by (metis fst_conv raise_trap_privilege return_def snd_conv)
 next
   case False
   then have f1: "\<not>(memory_write asi address (st_byte_mask instr address)
                         (st_data0 instr curr_win rd address s) s =
                        None)" 
     by auto
   then show ?thesis  
   proof (cases "(fst instr) \<in> {load_store_type STD,load_store_type STDA}")
     case True
     then have f2: "(fst instr) \<in> {load_store_type STD,load_store_type STDA}" by auto
     then show ?thesis using a1 f1
     apply (simp add: store_sub2_def)
     apply (simp add: simpler_gets_def bind_def h1_def h2_def)
     apply (simp add: simpler_modify_def bind_def h1_def h2_def Let_def)
     apply (simp add: return_def)
     apply (simp add: bind_def case_prod_unfold)
     apply (simp add: simpler_modify_def)
     apply clarsimp
     apply (simp add: case_prod_unfold bind_def h1_def h2_def Let_def simpler_modify_def)
     apply (simp add: simpler_gets_def)
     apply auto
        using memory_write_privilege raise_trap_privilege apply blast
       apply (simp add: simpler_modify_def simpler_gets_def bind_def)
       apply (meson memory_write_privilege)
      using memory_write_privilege raise_trap_privilege apply blast
     by (meson memory_write_privilege)    
   next
     case False
     then show ?thesis using a1 f1
     apply (simp add: store_sub2_def)
     apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
     apply clarsimp
     apply (simp add: simpler_modify_def return_def)
     by (auto intro: memory_write_privilege)
   qed
 qed
 
 lemma store_sub1_privilege: 
 assumes a1: "s' = snd (fst (store_sub1 instr rd s_val 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR 
   (s'::(('a::len0) sparc_state)))))::word1) = 0"
 proof (cases "(fst instr = load_store_type STH \<or> fst instr = load_store_type STHA) \<and>
               ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s)))))::word1) \<noteq> 0")
   case True
   then show ?thesis using a1
   apply (simp add: store_sub1_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   apply (simp add: case_prod_unfold)
   using get_curr_win_privilege raise_trap_privilege by blast                
 next
   case False
   then have f1: "\<not>((fst instr = load_store_type STH \<or> fst instr = load_store_type STHA) \<and>
               ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s)))))::word1) \<noteq> 0)"
     by auto
   then show ?thesis 
   proof (cases "(fst instr \<in> {load_store_type ST,load_store_type STA}) \<and>
               ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s)))))::word2) \<noteq> 0")
     case True
     then show ?thesis using a1 f1
     apply (simp add: store_sub1_def)
     apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
     apply (simp add: case_prod_unfold)    
     using get_curr_win_privilege raise_trap_privilege by blast
   next
     case False
     then have f2: "\<not>((fst instr \<in> {load_store_type ST,load_store_type STA}) \<and>
               ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s)))))::word2) \<noteq> 0)"
       by auto
     then show ?thesis
     proof (cases "(fst instr \<in> {load_store_type STD,load_store_type STDA}) \<and>
               ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s)))))::word3) \<noteq> 0")
       case True
       then show ?thesis using a1 f1 f2
       apply (simp add: store_sub1_def)
       apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
       apply (simp add: case_prod_unfold) 
       using get_curr_win_privilege raise_trap_privilege by blast
     next
       case False
       then show ?thesis using a1 f1 f2
       apply (simp add: store_sub1_def)
       apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
       apply (simp add: case_prod_unfold)
       by (meson get_curr_win_privilege store_sub2_privilege)       
     qed
   qed
 qed
 
 lemma store_instr_privilege: 
 assumes a1: "s' = snd (fst (store_instr instr 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR 
   (s'::(('a::len0) sparc_state)))))::word1) = 0"
 using a1
 apply (simp add: store_instr_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def)
 apply (simp add: Let_def)
 using raise_trap_privilege store_sub1_privilege by blast
 
 lemma sethi_instr_privilege: 
 assumes a1: "s' = snd (fst (sethi_instr instr 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 using a1
 apply (simp add: sethi_instr_def)
 apply (simp add: Let_def)
 apply auto
  apply (simp add: bind_def h1_def h2_def Let_def)
  apply (simp add: case_prod_unfold)
  using get_curr_win_privilege write_reg_privilege apply blast
 by (simp add: return_def)
 
 lemma nop_instr_privilege: 
 assumes a1: "s' = snd (fst (nop_instr instr 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 using a1
 apply (simp add: nop_instr_def)
 by (simp add: return_def)
 
 lemma ucast_0: "((ucast (get_S w))::word1) = 0 \<Longrightarrow> get_S w = 0"
 by (simp add: ucast_id)
 
 lemma ucast_02: "get_S w = 0 \<Longrightarrow> ((ucast (get_S w))::word1) = 0"
 by simp
 
 lemma ucast_s: "((ucast (get_S w))::word1) = 0 \<Longrightarrow> 
-  bitAND w (0b00000000000000000000000010000000::word32) = 0"
+  (AND) w (0b00000000000000000000000010000000::word32) = 0"
 apply (simp add: get_S_def)
 by (metis (mono_tags) ucast_id zero_neq_one)
 
-lemma ucast_s2: "bitAND w 0b00000000000000000000000010000000 = 0
+lemma ucast_s2: "(AND) w 0b00000000000000000000000010000000 = 0
   \<Longrightarrow> ((ucast (get_S w))::word1) = 0"
 by (simp add: get_S_def)
 
-lemma update_PSR_icc_1: "w' = bitAND w (0b11111111000011111111111111111111::word32)
+lemma update_PSR_icc_1: "w' = (AND) w (0b11111111000011111111111111111111::word32)
   \<and> ((ucast (get_S w))::word1) = 0
   \<Longrightarrow> ((ucast (get_S w'))::word1) = 0"
 by (simp add: get_S_def word_bw_assocs(1))
 
-lemma and_num_1048576_128: "bitAND (0b00000000000100000000000000000000::word32)
-  (0b00000000000000000000000010000000::word32) = 0"
-by simp
-
-lemma and_num_2097152_128: "bitAND (0b00000000001000000000000000000000::word32)
+lemma and_num_1048576_128: "(AND) (0b00000000000100000000000000000000::word32)
   (0b00000000000000000000000010000000::word32) = 0"
 by simp
 
-lemma and_num_4194304_128: "bitAND (0b00000000010000000000000000000000::word32)
+lemma and_num_2097152_128: "(AND) (0b00000000001000000000000000000000::word32)
   (0b00000000000000000000000010000000::word32) = 0"
 by simp
 
-lemma and_num_8388608_128: "bitAND (0b00000000100000000000000000000000::word32)
+lemma and_num_4194304_128: "(AND) (0b00000000010000000000000000000000::word32)
   (0b00000000000000000000000010000000::word32) = 0"
 by simp
 
-lemma or_and_s: "bitAND w1 (0b00000000000000000000000010000000::word32) = 0
-  \<and> bitAND w2 (0b00000000000000000000000010000000::word32) = 0
-  \<Longrightarrow> bitAND (bitOR w1 w2) (0b00000000000000000000000010000000::word32) = 0"
+lemma and_num_8388608_128: "(AND) (0b00000000100000000000000000000000::word32)
+  (0b00000000000000000000000010000000::word32) = 0"
+by simp
+
+lemma or_and_s: "(AND) w1 (0b00000000000000000000000010000000::word32) = 0
+  \<and> (AND) w2 (0b00000000000000000000000010000000::word32) = 0
+  \<Longrightarrow> (AND) ((OR) w1 w2) (0b00000000000000000000000010000000::word32) = 0"
 by (simp add: word_ao_dist)
 
 lemma and_or_s: 
 assumes a1: "((ucast (get_S w1))::word1) = 0 \<and> 
-  bitAND w2 (0b00000000000000000000000010000000::word32) = 0"
-shows "((ucast (get_S (bitOR (bitAND w1 
+  (AND) w2 (0b00000000000000000000000010000000::word32) = 0"
+shows "((ucast (get_S ((OR) ((AND) w1 
   (0b11111111000011111111111111111111::word32)) w2)))::word1) = 0"
 by (metis (full_types) assms ucast_s ucast_s2 word_ao_absorbs(8) word_bool_alg.conj_disj_distrib2)
 
 lemma and_or_or_s:
 assumes a1: "((ucast (get_S w1))::word1) = 0 \<and> 
-  bitAND w2 (0b00000000000000000000000010000000::word32) = 0 \<and>  
-  bitAND w3 (0b00000000000000000000000010000000::word32) = 0"
-shows "((ucast (get_S (bitOR (bitOR (bitAND w1 
+  (AND) w2 (0b00000000000000000000000010000000::word32) = 0 \<and>  
+  (AND) w3 (0b00000000000000000000000010000000::word32) = 0"
+shows "((ucast (get_S ((OR) ((OR) ((AND) w1 
   (0b11111111000011111111111111111111::word32)) w2) w3)))::word1) = 0"
 using and_or_s assms or_and_s ucast_s ucast_s2 by blast 
 
 lemma and_or_or_or_s:
 assumes a1: "((ucast (get_S w1))::word1) = 0 \<and> 
-  bitAND w2 (0b00000000000000000000000010000000::word32) = 0 \<and>  
-  bitAND w3 (0b00000000000000000000000010000000::word32) = 0 \<and>
-  bitAND w4 (0b00000000000000000000000010000000::word32) = 0"
-shows "((ucast (get_S (bitOR (bitOR (bitOR (bitAND w1 
+  (AND) w2 (0b00000000000000000000000010000000::word32) = 0 \<and>  
+  (AND) w3 (0b00000000000000000000000010000000::word32) = 0 \<and>
+  (AND) w4 (0b00000000000000000000000010000000::word32) = 0"
+shows "((ucast (get_S ((OR) ((OR) ((OR) ((AND) w1 
   (0b11111111000011111111111111111111::word32)) w2) w3) w4)))::word1) = 0"
 using and_or_or_s assms or_and_s ucast_s ucast_s2 
 by (meson word_bool_alg.conj.commute word_bool_alg.conj_zero_left word_bw_assocs(1))
 
 lemma and_or_or_or_or_s:
 assumes a1: "((ucast (get_S w1))::word1) = 0 \<and> 
-  bitAND w2 (0b00000000000000000000000010000000::word32) = 0 \<and>  
-  bitAND w3 (0b00000000000000000000000010000000::word32) = 0 \<and>
-  bitAND w4 (0b00000000000000000000000010000000::word32) = 0 \<and> 
-  bitAND w5 (0b00000000000000000000000010000000::word32) = 0"
-shows "((ucast (get_S (bitOR (bitOR (bitOR (bitOR (bitAND w1 
+  (AND) w2 (0b00000000000000000000000010000000::word32) = 0 \<and>  
+  (AND) w3 (0b00000000000000000000000010000000::word32) = 0 \<and>
+  (AND) w4 (0b00000000000000000000000010000000::word32) = 0 \<and> 
+  (AND) w5 (0b00000000000000000000000010000000::word32) = 0"
+shows "((ucast (get_S ((OR) ((OR) ((OR) ((OR) ((AND) w1 
   (0b11111111000011111111111111111111::word32)) w2) w3) w4) w5)))::word1) = 0"
 using and_or_or_or_s assms or_and_s ucast_s ucast_s2
 by (meson word_ao_absorbs(8) word_bool_alg.conj_disj_distrib2) 
 
 lemma write_cpu_PSR_icc_privilege: 
 assumes a1: "s' = snd (fst (write_cpu (update_PSR_icc n_val z_val v_val c_val 
                                         (cpu_reg_val PSR s)) 
                                       PSR 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 using a1
 apply (simp add: write_cpu_def)
 apply (simp add: simpler_modify_def)
 apply (simp add: cpu_reg_mod_def update_PSR_icc_def)
 apply (simp add: cpu_reg_val_def)
 apply auto
                using update_PSR_icc_1 apply blast
               using update_PSR_icc_1 and_num_1048576_128 and_or_s apply blast
              using update_PSR_icc_1 and_num_2097152_128 and_or_s apply blast
             using update_PSR_icc_1 and_num_1048576_128 and_num_2097152_128 
             and_or_or_s apply blast
            using update_PSR_icc_1 and_num_4194304_128 and_or_s apply blast
           using update_PSR_icc_1 and_num_1048576_128 and_num_4194304_128 
           and_or_or_s apply blast
          using update_PSR_icc_1 and_num_2097152_128 and_num_4194304_128 
          and_or_or_s apply blast
         using update_PSR_icc_1 and_num_1048576_128 and_num_2097152_128 and_num_4194304_128
         and_or_or_or_s apply blast 
        using update_PSR_icc_1 and_num_8388608_128 and_or_s apply blast
       using update_PSR_icc_1 and_num_1048576_128 and_num_8388608_128 
       and_or_or_s apply blast
      using update_PSR_icc_1 and_num_2097152_128 and_num_8388608_128 
      and_or_or_s apply blast
     using update_PSR_icc_1 and_num_1048576_128 and_num_2097152_128 and_num_8388608_128
     and_or_or_or_s apply blast 
    using update_PSR_icc_1 and_num_4194304_128 and_num_8388608_128 
    and_or_or_s apply blast
   using update_PSR_icc_1 and_num_1048576_128 and_num_4194304_128 and_num_8388608_128
   and_or_or_or_s apply blast 
  using update_PSR_icc_1 and_num_2097152_128 and_num_4194304_128 and_num_8388608_128
  and_or_or_or_s apply blast 
 using update_PSR_icc_1 and_num_1048576_128 and_num_2097152_128 and_num_4194304_128 
 and_num_8388608_128 and_or_or_or_or_s by blast 
 
-lemma and_num_4294967167_128: "bitAND (0b11111111111111111111111101111111::word32)
+lemma and_num_4294967167_128: "(AND) (0b11111111111111111111111101111111::word32)
   (0b00000000000000000000000010000000::word32) = 0"
 by simp
 
-lemma s_0_word: "((ucast (get_S (bitAND w 
+lemma s_0_word: "((ucast (get_S ((AND) w 
   (0b11111111111111111111111101111111::word32))))::word1) = 0"
 apply (simp add: get_S_def)
 using and_num_4294967167_128
 by (simp add: word_bool_alg.conj.commute word_bw_lcs(1)) 
 
-lemma update_PSR_CWP_1: "w' = bitAND w (0b11111111111111111111111111100000::word32)
+lemma update_PSR_CWP_1: "w' = (AND) w (0b11111111111111111111111111100000::word32)
   \<and> ((ucast (get_S w))::word1) = 0
   \<Longrightarrow> ((ucast (get_S w'))::word1) = 0"
 by (simp add: get_S_def word_bw_assocs(1))
 
 lemma write_cpu_PSR_CWP_privilege: 
 assumes a1: "s' = snd (fst (write_cpu (update_CWP cwp_val 
                                         (cpu_reg_val PSR s)) 
                                       PSR 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 using a1
 apply (simp add: write_cpu_def)
 apply (simp add: simpler_modify_def)
 apply (simp add: cpu_reg_mod_def)
 apply (simp add: update_CWP_def)
 apply (simp add: Let_def)
 apply auto
 apply (simp add: cpu_reg_val_def)
 using s_0_word by blast
 
 lemma logical_instr_sub1_privilege: 
 assumes a1: "s' = snd (fst (logical_instr_sub1 instr_name result 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 proof (cases "instr_name = logic_type ANDcc \<or>
               instr_name = logic_type ANDNcc \<or>
               instr_name = logic_type ORcc \<or>
               instr_name = logic_type ORNcc \<or>
               instr_name = logic_type XORcc \<or> instr_name = logic_type XNORcc")
   case True
   then show ?thesis using a1
   apply (simp add: logical_instr_sub1_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   apply (simp add: logical_new_psr_val_def)
   using write_cpu_PSR_icc_privilege by blast
 next
   case False
   then show ?thesis using a1
   apply (simp add: logical_instr_sub1_def)
   by (simp add: return_def)
 qed
 
 lemma logical_instr_privilege: 
 assumes a1: "s' = snd (fst (logical_instr instr 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 using a1
 apply (simp add: logical_instr_def)
 apply (simp add: Let_def simpler_gets_def bind_def h1_def h2_def)
 apply (simp add: case_prod_unfold)
 apply auto
  apply (meson get_curr_win_privilege logical_instr_sub1_privilege write_reg_privilege)
 by (meson get_curr_win_privilege logical_instr_sub1_privilege write_reg_privilege)
 
 method shift_instr_privilege_proof = (
 (simp add: shift_instr_def),
 (simp add: Let_def), 
 (simp add: simpler_gets_def),
 (simp add: bind_def h1_def h2_def Let_def case_prod_unfold),
 auto,
 (blast intro: get_curr_win_privilege write_reg_privilege),
 (blast intro: get_curr_win_privilege write_reg_privilege)
 )
 
 lemma shift_instr_privilege: 
 assumes a1: "s' = snd (fst (shift_instr instr 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 proof (cases "(fst instr = shift_type SLL) \<and> (get_operand_w5 ((snd instr)!3) \<noteq> 0)")
   case True
   then show ?thesis using a1
   by shift_instr_privilege_proof
 next
   case False
   then have f1: "\<not>((fst instr = shift_type SLL) \<and> (get_operand_w5 ((snd instr)!3) \<noteq> 0))"
     by auto
   then show ?thesis
   proof (cases "(fst instr = shift_type SRL) \<and> (get_operand_w5 ((snd instr)!3) \<noteq> 0)")
     case True
     then show ?thesis using a1 f1
     by shift_instr_privilege_proof
   next
     case False
     then have f2: "\<not>((fst instr = shift_type SRL) \<and> (get_operand_w5 ((snd instr)!3) \<noteq> 0))"
       by auto
     then show ?thesis 
     proof (cases "(fst instr = shift_type SRA) \<and> (get_operand_w5 ((snd instr)!3) \<noteq> 0)")
       case True
       then show ?thesis using a1 f1 f2
       by shift_instr_privilege_proof
     next
       case False
       then show ?thesis using a1 f1 f2
       apply (simp add: shift_instr_def)
       apply (simp add: Let_def) 
       apply (simp add: simpler_gets_def)
       apply (simp add: bind_def h1_def h2_def Let_def case_prod_unfold)
       apply (simp add: return_def)
       using get_curr_win_privilege by blast
     qed
   qed
 qed
 
 lemma add_instr_sub1_privilege: 
 assumes a1: "s' = snd (fst (add_instr_sub1 instr_name result rs1_val operand2 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 proof (cases "instr_name = arith_type ADDcc \<or> instr_name = arith_type ADDXcc")
   case True
   then show ?thesis using a1
   apply (simp add: add_instr_sub1_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   by (blast intro: write_cpu_PSR_icc_privilege)
 next
   case False
   then show ?thesis using a1
   apply (simp add: add_instr_sub1_def)
   by (simp add: return_def)
 qed
 
 lemma add_instr_privilege: 
 assumes a1: "s' = snd (fst (add_instr instr 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 using a1
 apply (simp add: add_instr_def)
 apply (simp add: Let_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 by (meson add_instr_sub1_privilege get_curr_win_privilege write_reg_privilege)
 
 lemma sub_instr_sub1_privilege: 
 assumes a1: "s' = snd (fst (sub_instr_sub1 instr_name result rs1_val operand2 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 proof (cases "instr_name = arith_type SUBcc \<or> instr_name = arith_type SUBXcc")
   case True
   then show ?thesis using a1
   apply (simp add: sub_instr_sub1_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   by (blast intro: write_cpu_PSR_icc_privilege)
 next
   case False
   then show ?thesis using a1
   apply (simp add: sub_instr_sub1_def)
   by (simp add: return_def)
 qed
 
 lemma sub_instr_privilege: 
 assumes a1: "s' = snd (fst (sub_instr instr 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 using a1
 apply (simp add: sub_instr_def)
 apply (simp add: Let_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 by (meson sub_instr_sub1_privilege get_curr_win_privilege write_reg_privilege)
 
 lemma mul_instr_sub1_privilege: 
 assumes a1: "s' = snd (fst (mul_instr_sub1 instr_name result  
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 proof (cases "instr_name \<in> {arith_type SMULcc,arith_type UMULcc}")
   case True
   then show ?thesis using a1
   apply (simp add: mul_instr_sub1_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   by (blast intro: write_cpu_PSR_icc_privilege)
 next
   case False
   then show ?thesis using a1
   apply (simp add: mul_instr_sub1_def)
   by (simp add: return_def)
 qed
 
 lemma mul_instr_privilege: 
 assumes a1: "s' = snd (fst (mul_instr instr 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 using a1
 apply (simp add: mul_instr_def)
 apply (simp add: Let_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 by (meson get_curr_win_privilege mul_instr_sub1_privilege write_cpu_y_privilege write_reg_privilege)
 
 lemma div_write_new_val_privilege: 
 assumes a1: "s' = snd (fst (div_write_new_val i result temp_V  
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 proof (cases "(fst i) \<in> {arith_type UDIVcc,arith_type SDIVcc}")
   case True
   then show ?thesis using a1
   apply (simp add: div_write_new_val_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   by (blast intro: write_cpu_PSR_icc_privilege)
 next
   case False
   then show ?thesis using a1
   apply (simp add: div_write_new_val_def)
   by (simp add: return_def)
 qed
 
 lemma div_comp_privilege: 
 assumes a1: "s' = snd (fst (div_comp instr rs1 rd operand2  
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 using a1
 apply (simp add: div_comp_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 by (meson get_curr_win_privilege div_write_new_val_privilege write_reg_privilege)
 
 lemma div_instr_privilege: 
 assumes a1: "s' = snd (fst (div_instr instr 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 using a1
 apply (simp add: div_instr_def)
 apply (simp add: Let_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 apply (simp add: return_def)
 apply auto
  using raise_trap_privilege apply blast
 using div_comp_privilege by blast
 
 lemma save_retore_sub1_privilege: 
 assumes a1: "s' = snd (fst (save_retore_sub1 result new_cwp rd 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 using a1
 apply (simp add: save_retore_sub1_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 using write_cpu_PSR_CWP_privilege write_reg_privilege by blast
 
 method save_restore_instr_privilege_proof = (
 (simp add: save_restore_instr_def),
 (simp add: Let_def),
 (simp add: simpler_gets_def bind_def h1_def h2_def Let_def),
 (simp add: case_prod_unfold),
 auto,
 (blast intro: get_curr_win_privilege raise_trap_privilege),
 (simp add: simpler_gets_def bind_def h1_def h2_def Let_def case_prod_unfold),
 (blast intro: get_curr_win_privilege save_retore_sub1_privilege)
 )
 
 lemma save_restore_instr_privilege: 
 assumes a1: "s' = snd (fst (save_restore_instr instr 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 proof (cases "fst instr = ctrl_type SAVE")
   case True
   then have f1: "fst instr = ctrl_type SAVE" by auto
   then show ?thesis using a1
   by save_restore_instr_privilege_proof
 next
   case False
   then show ?thesis using a1
   by save_restore_instr_privilege_proof
 qed
 
 lemma call_instr_privilege: 
 assumes a1: "s' = snd (fst (call_instr instr 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 using a1
 apply (simp add: call_instr_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 by (meson get_curr_win_privilege write_cpu_npc_privilege write_cpu_pc_privilege write_reg_privilege)
 
 lemma jmpl_instr_privilege: 
 assumes a1: "s' = snd (fst (jmpl_instr instr 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 using a1
 apply (simp add: jmpl_instr_def)
 apply (simp add: Let_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 apply auto
  using get_curr_win_privilege raise_trap_privilege apply blast
 apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 by (meson get_curr_win_privilege write_cpu_npc_privilege write_cpu_pc_privilege write_reg_privilege)
 
 lemma rett_instr_privilege: 
 assumes a1: "snd (rett_instr i s) = False \<and>
   s' = snd (fst (rett_instr instr 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 using a1
 apply (simp add: rett_instr_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
 apply auto
  apply (simp add: case_prod_unfold)
  apply (simp add: return_def)
  apply (blast intro: raise_trap_privilege)
 apply (simp add: bind_def h1_def h2_def Let_def)
 by (simp add: case_prod_unfold fail_def)
 
 method read_state_reg_instr_privilege_proof = (
 (simp add: read_state_reg_instr_def),
 (simp add: Let_def),
 (simp add: simpler_gets_def bind_def h1_def h2_def Let_def),
 (simp add: case_prod_unfold)
 )
 
 lemma read_state_reg_instr_privilege: 
 assumes a1: "s' = snd (fst (read_state_reg_instr instr 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 proof (cases "(fst instr \<in> {sreg_type RDPSR,sreg_type RDWIM,sreg_type RDTBR} \<or> 
         (fst instr = sreg_type RDASR \<and> privileged_ASR (get_operand_w5 ((snd instr)!0))))")
   case True
   then have "(fst instr \<in> {sreg_type RDPSR,sreg_type RDWIM,sreg_type RDTBR} \<or> 
         (fst instr = sreg_type RDASR \<and> privileged_ASR (get_operand_w5 ((snd instr)!0))))
         \<and> ((ucast (get_S (cpu_reg_val PSR (snd (fst (get_curr_win () s))))))::word1) = 0"
     by (metis assms get_curr_win_privilege)    
   then show ?thesis using a1
   apply read_state_reg_instr_privilege_proof
   by (blast intro: raise_trap_privilege get_curr_win_privilege)
 next
   case False
   then have f1: "\<not>((fst instr = sreg_type RDPSR \<or>
                     fst instr = sreg_type RDWIM \<or>
                     fst instr = sreg_type RDTBR \<or>
                     fst instr = sreg_type RDASR \<and> privileged_ASR (get_operand_w5 (snd instr ! 0))) \<and>
                    ucast (get_S (cpu_reg_val PSR (snd (fst (get_curr_win () s))))) = 0)"
     by blast 
   then show ?thesis 
   proof (cases "illegal_instruction_ASR (get_operand_w5 ((snd instr)!0))")
     case True
     then show ?thesis using a1 f1
     apply read_state_reg_instr_privilege_proof
     by (simp add: illegal_instruction_ASR_def)    
   next
     case False
     then have f2: "\<not>(illegal_instruction_ASR (get_operand_w5 ((snd instr)!0)))" 
       by auto
     then show ?thesis 
     proof (cases "(get_operand_w5 ((snd instr)!1)) \<noteq> 0")
       case True
       then have f3: "(get_operand_w5 ((snd instr)!1)) \<noteq> 0" 
         by auto
       then show ?thesis 
       proof (cases "fst instr = sreg_type RDY")
         case True
         then show ?thesis using a1 f1 f2 f3
         apply (simp add: read_state_reg_instr_def)
         apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
         apply (simp add: case_prod_unfold)
         by (blast intro: get_curr_win_privilege write_reg_privilege)        
       next
         case False
         then have f4: "\<not>(fst instr = sreg_type RDY)" by auto
         then show ?thesis 
         proof (cases "fst instr = sreg_type RDASR")
           case True
           then show ?thesis using a1 f1 f2 f3 f4
           apply read_state_reg_instr_privilege_proof
           apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
           by (blast intro: get_curr_win_privilege write_reg_privilege) 
         next
           case False
           then have f5: "\<not>(fst instr = sreg_type RDASR)" by auto
           then show ?thesis 
           proof (cases "fst instr = sreg_type RDPSR")
             case True
             then show ?thesis using a1 f1 f2 f3 f4 f5
             apply read_state_reg_instr_privilege_proof
             by (blast intro: get_curr_win_privilege write_reg_privilege) 
           next
             case False
             then show ?thesis using a1 f1 f2 f3 f4 f5
             apply read_state_reg_instr_privilege_proof
             apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
             by (blast intro: get_curr_win_privilege write_reg_privilege) 
           qed
         qed
       qed
     next
       case False
       then show ?thesis using a1 
       apply read_state_reg_instr_privilege_proof
       apply (simp add: return_def) 
       using f1 f2 get_curr_win_privilege by blast     
     qed
   qed
 qed
 
 method write_state_reg_instr_privilege_proof = (
 (simp add: write_state_reg_instr_def),
 (simp add: Let_def),
 (simp add: simpler_gets_def bind_def h1_def h2_def Let_def),
 (simp add: case_prod_unfold)
 )
 
 lemma write_state_reg_instr_privilege: 
 assumes a1: "s' = snd (fst (write_state_reg_instr instr 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 proof (cases "fst instr = sreg_type WRY")
   case True
   then show ?thesis using a1
   apply write_state_reg_instr_privilege_proof
   apply (simp add: simpler_modify_def)
   apply (simp add: delayed_pool_add_def DELAYNUM_def)
   by (blast intro: cpu_reg_mod_y_privilege get_curr_win_privilege)
 next
   case False
   then have f1: "\<not>(fst instr = sreg_type WRY)" by auto
   then show ?thesis
   proof (cases "fst instr = sreg_type WRASR")
     case True
     then show ?thesis
      using a1 f1
     apply write_state_reg_instr_privilege_proof
     apply (simp add: simpler_modify_def)
     apply auto
          using illegal_instruction_ASR_def apply blast
         using illegal_instruction_ASR_def apply blast
        using illegal_instruction_ASR_def apply blast
       using raise_trap_privilege get_curr_win_privilege apply blast
      apply (simp add: simpler_modify_def delayed_pool_add_def DELAYNUM_def)
      using cpu_reg_mod_asr_privilege get_curr_win_privilege apply blast
     apply (simp add: simpler_modify_def delayed_pool_add_def DELAYNUM_def)
     using cpu_reg_mod_asr_privilege get_curr_win_privilege by blast
   next
     case False
     then have f2: "\<not>(fst instr = sreg_type WRASR)" by auto
     have f3: "get_S (cpu_reg_val PSR (snd (fst (get_curr_win () s)))) = 0"
       using get_curr_win_privilege a1 by (metis ucast_id)
     then show ?thesis 
     proof (cases "fst instr = sreg_type WRPSR")
       case True
       then show ?thesis using a1 f1 f2 f3
       apply write_state_reg_instr_privilege_proof
       by (metis raise_trap_privilege ucast_0)      
     next
       case False
       then have f4: "\<not>(fst instr = sreg_type WRPSR)" by auto
       then show ?thesis 
       proof (cases "fst instr = sreg_type WRWIM")  
         case True
         then show ?thesis using a1 f1 f2 f3 f4
         apply write_state_reg_instr_privilege_proof
         by (metis raise_trap_privilege ucast_0)  
       next
         case False
         then have f5: "\<not>(fst instr = sreg_type WRWIM)" by auto
         then show ?thesis using a1 f1 f2 f3 f4 f5
         apply write_state_reg_instr_privilege_proof
         by (metis raise_trap_privilege ucast_0)        
       qed
     qed
   qed
 qed
 
 lemma flush_instr_privilege: 
 assumes a1: "s' = snd (fst (flush_instr instr 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 using a1
 apply (simp add: flush_instr_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def simpler_modify_def)
 by (auto simp add: flush_cache_all_privilege)
 
 lemma branch_instr_privilege: 
 assumes a1: "s' = snd (fst (branch_instr instr 
   (s::(('a::len0) sparc_state))))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 using a1
 apply (simp add: branch_instr_def)
 apply (simp add: Let_def simpler_gets_def bind_def h1_def h2_def)
 apply (simp add: case_prod_unfold return_def)
 by (meson set_annul_privilege write_cpu_npc_privilege write_cpu_pc_privilege)
 
 method dispath_instr_privilege_proof = (
 (simp add: dispatch_instruction_def),
 (simp add: simpler_gets_def bind_def h1_def h2_def Let_def),
 (simp add: Let_def)
 )
 
 lemma dispath_instr_privilege: 
 assumes a1: "snd (dispatch_instruction instr s) = False \<and>
   s' = snd (fst (dispatch_instruction instr s))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 proof (cases "get_trap_set s = {}")
   case True
   then have f1: "get_trap_set s = {}" by auto
   show ?thesis
   proof (cases "fst instr \<in> {load_store_type LDSB,load_store_type LDUB,
         load_store_type LDUBA,load_store_type LDUH,load_store_type LD,
         load_store_type LDA,load_store_type LDD}")
     case True
     then show ?thesis using a1 f1
     apply dispath_instr_privilege_proof
     by (blast intro: load_instr_privilege)    
   next
     case False
     then have f2: "\<not>(fst instr \<in> {load_store_type LDSB,load_store_type LDUB,
         load_store_type LDUBA,load_store_type LDUH,load_store_type LD,
         load_store_type LDA,load_store_type LDD})"
       by auto
     then show ?thesis 
     proof (cases "fst instr \<in> {load_store_type STB,load_store_type STH,
         load_store_type ST,load_store_type STA,load_store_type STD}")
       case True
       then show ?thesis using a1 f1 f2
       apply dispath_instr_privilege_proof
       by (blast intro: store_instr_privilege) 
     next
       case False
       then have f3: "\<not>(fst instr \<in> {load_store_type STB,load_store_type STH,
         load_store_type ST,load_store_type STA,load_store_type STD})"
         by auto
       then show ?thesis 
       proof (cases "fst instr \<in> {sethi_type SETHI}")
         case True
         then show ?thesis using a1 f1 f2 f3
         apply dispath_instr_privilege_proof
         by (blast intro: sethi_instr_privilege) 
       next
         case False
         then have f4: "\<not>(fst instr \<in> {sethi_type SETHI})"
           by auto
         then show ?thesis
         proof (cases "fst instr \<in> {nop_type NOP}")
           case True
           then show ?thesis using a1 f1 f2 f3 f4
           apply dispath_instr_privilege_proof
           by (blast intro: nop_instr_privilege)
         next
           case False
           then have f5: "\<not>(fst instr \<in> {nop_type NOP})" 
             by auto
           then show ?thesis
           proof (cases "fst instr \<in> {logic_type ANDs,logic_type ANDcc,logic_type ANDN,
             logic_type ANDNcc,logic_type ORs,logic_type ORcc,logic_type ORN,
             logic_type XORs,logic_type XNOR}")
             case True
             then show ?thesis using a1 f1 f2 f3 f4 f5
             apply dispath_instr_privilege_proof
             by (blast intro: logical_instr_privilege)
           next
             case False
             then have f6: "\<not>(fst instr \<in> {logic_type ANDs,logic_type ANDcc,logic_type ANDN,
             logic_type ANDNcc,logic_type ORs,logic_type ORcc,logic_type ORN,
             logic_type XORs,logic_type XNOR})"
               by auto
             show ?thesis
             proof (cases "fst instr \<in> {shift_type SLL,shift_type SRL,shift_type SRA}")
               case True
               then show ?thesis using a1 f1 f2 f3 f4 f5 f6
               apply dispath_instr_privilege_proof
               by (blast intro: shift_instr_privilege)
             next
               case False
               then have f7: "\<not>(fst instr \<in> {shift_type SLL,shift_type SRL,shift_type SRA})"
                 by auto
               then show ?thesis 
               proof (cases "fst instr \<in> {arith_type ADD,arith_type ADDcc,arith_type ADDX}")
                 case True
                 then show ?thesis using a1 f1 f2 f3 f4 f5 f6 f7
                 apply dispath_instr_privilege_proof
                 by (blast intro: add_instr_privilege)
               next
                 case False
                 then have f8: "\<not>(fst instr \<in> {arith_type ADD,arith_type ADDcc,arith_type ADDX})"
                   by auto
                 then show ?thesis
                 proof (cases "fst instr \<in> {arith_type SUB,arith_type SUBcc,arith_type SUBX}")
                   case True
                   then show ?thesis using a1 f1 f2 f3 f4 f5 f6 f7 f8
                   apply dispath_instr_privilege_proof
                   by (blast intro: sub_instr_privilege)
                 next
                   case False
                   then have f9: "\<not>(fst instr \<in> {arith_type SUB,arith_type SUBcc,arith_type SUBX})"
                     by auto
                   then show ?thesis
                   proof (cases "fst instr \<in> {arith_type UMUL,arith_type SMUL,arith_type SMULcc}")
                     case True
                     then show ?thesis using a1 f1 f2 f3 f4 f5 f6 f7 f8 f9
                     apply dispath_instr_privilege_proof
                     by (blast intro: mul_instr_privilege)
                   next
                     case False
                     then have f10: "\<not>(fst instr \<in> {arith_type UMUL,arith_type SMUL,
                       arith_type SMULcc})"
                       by auto
                     then show ?thesis 
                     proof (cases "fst instr \<in> {arith_type UDIV,arith_type UDIVcc,arith_type SDIV}")
                       case True
                       then show ?thesis using a1 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10
                       apply dispath_instr_privilege_proof
                       by (blast intro: div_instr_privilege)
                     next
                       case False
                       then have f11: "\<not>(fst instr \<in> {arith_type UDIV,
                         arith_type UDIVcc,arith_type SDIV})"
                         by auto
                       then show ?thesis 
                       proof (cases "fst instr \<in> {ctrl_type SAVE,ctrl_type RESTORE}")
                         case True
                         then show ?thesis using a1 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11
                         apply dispath_instr_privilege_proof
                         by (blast intro: save_restore_instr_privilege)
                       next
                         case False
                         then have f12: "\<not>(fst instr \<in> {ctrl_type SAVE,ctrl_type RESTORE})"
                           by auto
                         then show ?thesis 
                         proof (cases "fst instr \<in> {call_type CALL}")
                           case True
                           then show ?thesis using a1 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12
                           apply dispath_instr_privilege_proof
                           by (blast intro: call_instr_privilege)
                         next
                           case False
                           then have f13: "\<not>(fst instr \<in> {call_type CALL})" by auto
                           then show ?thesis
                           proof (cases "fst instr \<in> {ctrl_type JMPL}")
                             case True
                             then show ?thesis using a1 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13
                             apply dispath_instr_privilege_proof
                             by (blast intro: jmpl_instr_privilege)
                           next
                             case False
                             then have f14: "\<not>(fst instr \<in> {ctrl_type JMPL})" by auto
                             then show ?thesis 
                             proof (cases "fst instr \<in> {ctrl_type RETT}")
                               case True
                               then show ?thesis using a1 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13
                                 f14
                               apply dispath_instr_privilege_proof
                               by (blast intro: rett_instr_privilege)
                             next
                               case False
                               then have f15: "\<not>(fst instr \<in> {ctrl_type RETT})" by auto
                               then show ?thesis 
                               proof (cases "fst instr \<in> {sreg_type RDY,sreg_type RDPSR,
                                 sreg_type RDWIM, sreg_type RDTBR}")
                                 case True
                                 then show ?thesis using a1 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 
                                 f13 f14 f15
                                 apply dispath_instr_privilege_proof
                                 by (blast intro: read_state_reg_instr_privilege)
                               next
                                 case False
                                 then have f16: "\<not>(fst instr \<in> {sreg_type RDY,sreg_type RDPSR,
                                 sreg_type RDWIM, sreg_type RDTBR})" by auto
                                 then show ?thesis
                                 proof (cases "fst instr \<in> {sreg_type WRY,sreg_type WRPSR,
                                   sreg_type WRWIM, sreg_type WRTBR}")
                                   case True
                                   then show ?thesis using a1 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 
                                   f13 f14 f15 f16
                                   apply dispath_instr_privilege_proof
                                   by (blast intro: write_state_reg_instr_privilege)
                                 next
                                   case False
                                   then have f17: "\<not>(fst instr \<in> {sreg_type WRY,sreg_type WRPSR,
                                   sreg_type WRWIM, sreg_type WRTBR})" by auto
                                   then show ?thesis
                                   proof (cases "fst instr \<in> {load_store_type FLUSH}")
                                     case True
                                     then show ?thesis using a1 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 
                                     f12 f13 f14 f15 f16 f17
                                     apply dispath_instr_privilege_proof
                                     by (blast intro: flush_instr_privilege)
                                   next
                                     case False
                                     then have f18: "\<not>(fst instr \<in> {load_store_type FLUSH})" by auto
                                     then show ?thesis 
                                     proof (cases "fst instr \<in> {bicc_type BE,bicc_type BNE,
                                       bicc_type BGU,bicc_type BLE,bicc_type BL,bicc_type BGE,
                                       bicc_type BNEG,bicc_type BG,bicc_type BCS,bicc_type BLEU,
                                       bicc_type BCC,bicc_type BA,bicc_type BN}")
                                       case True
                                       then show ?thesis using a1 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 
                                       f12 f13 f14 f15 f16 f17 f18
                                       apply dispath_instr_privilege_proof
                                       by (blast intro: branch_instr_privilege)
                                     next
                                       case False
                                       then show ?thesis using a1 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 
                                       f12 f13 f14 f15 f16 f17 f18
                                       apply dispath_instr_privilege_proof
                                       by (simp add: fail_def)
                                     qed
                                   qed
                                 qed
                               qed
                             qed
                           qed
                         qed
                       qed
                     qed
                   qed
                 qed
               qed
             qed
           qed
         qed
       qed
     qed
   qed
 next
   case False
   then show ?thesis using a1
   apply (simp add: dispatch_instruction_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def)
   apply (simp add: Let_def)
   by (simp add: return_def)
 qed
 
 lemma execute_instr_sub1_privilege: 
 assumes a1: "snd (execute_instr_sub1 i s) = False \<and>
   s' = snd (fst (execute_instr_sub1 i s))
   \<and> ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 proof (cases "get_trap_set s = {} \<and> fst i \<notin> {call_type CALL,ctrl_type RETT,ctrl_type JMPL,
                                    bicc_type BE,bicc_type BNE,bicc_type BGU,
                                    bicc_type BLE,bicc_type BL,bicc_type BGE,
                                    bicc_type BNEG,bicc_type BG,
                                    bicc_type BCS,bicc_type BLEU,bicc_type BCC,
                                    bicc_type BA,bicc_type BN}")
   case True
   then show ?thesis using a1
   apply (simp add: execute_instr_sub1_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   apply (simp add: case_prod_unfold return_def)
   by (auto intro: write_cpu_pc_privilege write_cpu_npc_privilege)
 next
   case False
   then show ?thesis using a1
   apply (simp add: execute_instr_sub1_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   apply (simp add: case_prod_unfold return_def)
   by auto
 qed
 
 text \<open>
   Assume that there is no \<open>delayed_write\<close> and 
   there is no traps to be executed.
   If an instruction is executed as a user,
   the privilege will not be changed to supervisor after 
   the execution.\<close>
 theorem safe_privilege : 
 assumes a1: "get_delayed_pool s = [] \<and> get_trap_set s = {} \<and>
   snd (execute_instruction() s) = False \<and>
   s' = snd (fst (execute_instruction() s)) \<and> 
   ((ucast (get_S (cpu_reg_val PSR s)))::word1) = 0"
 shows "((ucast (get_S (cpu_reg_val PSR s')))::word1) = 0"
 proof (cases "exe_mode_val s")
   case True   
   then have f2: "exe_mode_val s = True" by auto
   then show ?thesis
   proof (cases "\<exists>e. fetch_instruction (delayed_pool_write s) = Inl e")
     case True
     then have f3: "\<exists>e. fetch_instruction (delayed_pool_write s) = Inl e"
       by auto
     then have f4: "\<not> (\<exists>v. fetch_instruction (delayed_pool_write s) = Inr v)" 
       using fetch_instr_result_3 by auto
     then show ?thesis using a1 f2 f3 raise_trap_result empty_delayed_pool_write_privilege raise_trap_privilege        
     apply (simp add: execute_instruction_def)
     apply (simp add: exec_gets return_def)
     apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
     apply (simp add: simpler_modify_def)
     apply clarsimp
     apply (simp add: case_prod_unfold)
     by (blast intro: empty_delayed_pool_write_privilege raise_trap_privilege)      
   next
     case False
     then have f5: "\<exists>v. fetch_instruction (delayed_pool_write s) = Inr v"
       using fetch_instr_result_1 by blast
     then have f6: "\<exists>v. fetch_instruction (delayed_pool_write s) = Inr v \<and>
     \<not> (\<exists>e. ((decode_instruction v)::(Exception list + instruction)) = Inl e)"
       using a1 f2 dispatch_fail by blast 
     then have f7: "\<exists>v. fetch_instruction (delayed_pool_write s) = Inr v \<and>
     (\<exists>v1. ((decode_instruction v)::(Exception list + instruction)) = Inr v1)"
       using decode_instr_result_4 by auto 
     then show ?thesis
     proof (cases "annul_val (delayed_pool_write s)")
       case True
       then show ?thesis using  a1 f2 f7           
       apply (simp add: execute_instruction_def)
       apply (simp add: exec_gets return_def)
       apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
       apply (simp add: simpler_modify_def)
       apply clarsimp
       apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
       apply (simp add: case_prod_unfold)
       by (auto intro: empty_delayed_pool_write_privilege 
       set_annul_privilege write_cpu_npc_privilege write_cpu_pc_privilege)
     next 
       case False
       then show ?thesis using  a1 f2 f7 
       apply (simp add: execute_instruction_def)
       apply (simp add: exec_gets return_def)
       apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
       apply (simp add: simpler_modify_def)
       apply clarsimp
       apply (simp add: bind_def h1_def h2_def Let_def)
       apply (simp add: case_prod_unfold)
       apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
       apply (simp add: simpler_modify_def return_def)
       apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
       apply (simp add: case_prod_unfold)
       by (auto intro: empty_delayed_pool_write_privilege dispath_instr_privilege 
          execute_instr_sub1_privilege)        
     qed
   qed    
 next
   case False
   then show ?thesis using a1 
   apply (simp add: execute_instruction_def)
   by (simp add: simpler_gets_def bind_def h1_def h2_def Let_def return_def) 
 qed
 
 (*********************************************************************)
 
 section \<open>Single step non-interference property.\<close>
 
 (*********************************************************************)
 
 definition user_accessible:: "('a::len0) sparc_state \<Rightarrow> phys_address \<Rightarrow> bool" where
 "user_accessible s pa \<equiv> \<exists>va p. (virt_to_phys va (mmu s) (mem s)) = Some p \<and>
   mmu_readable (get_acc_flag (snd p)) 10 \<and>
   (fst p) = pa" \<comment> \<open>Passing \<open>asi = 8\<close> is the same.\<close>
 
 lemma user_accessible_8: 
 assumes a1: "mmu_readable (get_acc_flag (snd p)) 8"
 shows "mmu_readable (get_acc_flag (snd p)) 10"
 using a1 by (simp add: mmu_readable_def)
 
 definition mem_equal:: "('a) sparc_state \<Rightarrow> ('a) sparc_state \<Rightarrow> 
   phys_address \<Rightarrow> bool" where
 "mem_equal s1 s2 pa \<equiv>
   (mem s1) 8 (pa AND 68719476732) = (mem s2) 8 (pa AND 68719476732) \<and>
   (mem s1) 8 ((pa AND 68719476732) + 1) = (mem s2) 8 ((pa AND 68719476732) + 1) \<and>
   (mem s1) 8 ((pa AND 68719476732) + 2) = (mem s2) 8 ((pa AND 68719476732) + 2) \<and>
   (mem s1) 8 ((pa AND 68719476732) + 3) = (mem s2) 8 ((pa AND 68719476732) + 3) \<and>
   (mem s1) 9 (pa AND 68719476732) = (mem s2) 9 (pa AND 68719476732) \<and>
   (mem s1) 9 ((pa AND 68719476732) + 1) = (mem s2) 9 ((pa AND 68719476732) + 1) \<and>
   (mem s1) 9 ((pa AND 68719476732) + 2) = (mem s2) 9 ((pa AND 68719476732) + 2) \<and>
   (mem s1) 9 ((pa AND 68719476732) + 3) = (mem s2) 9 ((pa AND 68719476732) + 3) \<and>
   (mem s1) 10 (pa AND 68719476732) = (mem s2) 10 (pa AND 68719476732) \<and>
   (mem s1) 10 ((pa AND 68719476732) + 1) = (mem s2) 10 ((pa AND 68719476732) + 1) \<and>
   (mem s1) 10 ((pa AND 68719476732) + 2) = (mem s2) 10 ((pa AND 68719476732) + 2) \<and>
   (mem s1) 10 ((pa AND 68719476732) + 3) = (mem s2) 10 ((pa AND 68719476732) + 3) \<and>
   (mem s1) 11 (pa AND 68719476732) = (mem s2) 11 (pa AND 68719476732) \<and>
   (mem s1) 11 ((pa AND 68719476732) + 1) = (mem s2) 11 ((pa AND 68719476732) + 1) \<and>
   (mem s1) 11 ((pa AND 68719476732) + 2) = (mem s2) 11 ((pa AND 68719476732) + 2) \<and>
   (mem s1) 11 ((pa AND 68719476732) + 3) = (mem s2) 11 ((pa AND 68719476732) + 3)"
 
 text \<open>\<open>low_equal\<close> defines the equivalence relation over two sparc
 states that is an analogy to the \<open>=\<^sub>L\<close> relation over memory contexts
 in the traditional non-interference theorem.\<close>
 
 definition low_equal:: "('a::len0) sparc_state \<Rightarrow> ('a) sparc_state \<Rightarrow> bool" where
 "low_equal s1 s2 \<equiv> 
   (cpu_reg s1) = (cpu_reg s2) \<and>
   (user_reg s1) = (user_reg s2) \<and>
   (sys_reg s1) = (sys_reg s2) \<and>  
   (\<forall>va. (virt_to_phys va (mmu s1) (mem s1)) = (virt_to_phys va (mmu s2) (mem s2))) \<and>
   (\<forall>pa. (user_accessible s1 pa) \<longrightarrow> mem_equal s1 s2 pa) \<and>  
   (mmu s1) = (mmu s2) \<and> 
   (state_var s1) = (state_var s2) \<and>
   (traps s1) = (traps s2) \<and>
   (undef s1) = (undef s2)
 " 
 
 lemma low_equal_com: "low_equal s1 s2 \<Longrightarrow> low_equal s2 s1"
 apply (simp add: low_equal_def)
 apply (simp add: mem_equal_def user_accessible_def)
 by metis
 
 lemma non_exe_mode_equal: "exe_mode_val s = False \<and>
 get_trap_set s = {} \<and>
 Some t = NEXT s \<Longrightarrow> 
 t = s"
 apply (simp add: NEXT_def execute_instruction_def)
 apply auto
 by (simp add: simpler_gets_def bind_def h1_def h2_def Let_def return_def)
 
 lemma exe_mode_low_equal:
 assumes a1: "low_equal s1 s2"
 shows " exe_mode_val s1 =  exe_mode_val s2"
 using a1 apply (simp add: low_equal_def)
 by (simp add: exe_mode_val_def)
 
 lemma mem_val_mod_state: "mem_val_alt asi a s = mem_val_alt asi a 
 (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>)"
 apply (simp add: mem_val_alt_def)
 by (simp add: Let_def)
 
 lemma mem_val_w32_mod_state: "mem_val_w32 asi a s = mem_val_w32 asi a 
 (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>)"
 apply (simp add: mem_val_w32_def)
 apply (simp add: Let_def)
 by (metis mem_val_mod_state)
 
 lemma load_word_mem_mod_state: "load_word_mem s addr asi = load_word_mem 
 (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>) addr asi"
 apply (simp add: load_word_mem_def)
 apply (case_tac "virt_to_phys addr (mmu s) (mem s) = None")
  apply auto
 by (auto simp add: mem_val_w32_mod_state)
 
 lemma load_word_mem2_mod_state: 
 "fst (case load_word_mem s addr asi of None \<Rightarrow> (None, s)
       | Some w \<Rightarrow> (Some w, add_data_cache s addr w 15)) =
  fst (case load_word_mem (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>) addr asi of
          None \<Rightarrow> (None, (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>))
       | Some w \<Rightarrow> (Some w, add_data_cache (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>) addr w 15))"
 proof (cases "load_word_mem s addr asi = None")
   case True
   then have "load_word_mem s addr asi = None \<and>
     load_word_mem (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>) addr asi = None"
     using load_word_mem_mod_state by metis
   then show ?thesis by auto
 next
   case False
   then have "\<exists>w. load_word_mem s addr asi = Some w" by auto
   then have "\<exists>w. load_word_mem s addr asi = Some w \<and> 
     load_word_mem (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>) addr asi = Some w"
   using load_word_mem_mod_state by metis
   then show ?thesis by auto
 qed
 
 lemma load_word_mem3_mod_state: 
 "fst (case load_word_mem s addr asi of None \<Rightarrow> (None, s)
       | Some w \<Rightarrow> (Some w, add_instr_cache s addr w 15)) =
  fst (case load_word_mem (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>) addr asi of
          None \<Rightarrow> (None, (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>))
       | Some w \<Rightarrow> (Some w, add_instr_cache (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>) addr w 15))"
 proof (cases "load_word_mem s addr asi = None")
   case True
   then have "load_word_mem s addr asi = None \<and>
     load_word_mem (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>) addr asi = None"
     using load_word_mem_mod_state by metis
   then show ?thesis by auto
 next
   case False
   then have "\<exists>w. load_word_mem s addr asi = Some w" by auto
   then have "\<exists>w. load_word_mem s addr asi = Some w \<and> 
     load_word_mem (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>) addr asi = Some w"
   using load_word_mem_mod_state by metis
   then show ?thesis by auto
 qed
 
 lemma read_dcache_mod_state: "read_data_cache s addr = read_data_cache 
 (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>) addr"
 apply (simp add: read_data_cache_def)
 by (simp add: dcache_val_def)
 
 lemma read_dcache2_mod_state: 
 "fst (case read_data_cache s addr of None \<Rightarrow> (None, s)
       | Some w \<Rightarrow> (Some w, s)) =
  fst (case read_data_cache (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>) addr of
          None \<Rightarrow> (None, (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>))
       | Some w \<Rightarrow> (Some w, (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>)))"
 proof (cases "read_data_cache s addr = None")
   case True
   then have "read_data_cache s addr = None \<and>
     read_data_cache (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>) addr = None"
     using read_dcache_mod_state by metis
   then show ?thesis by auto    
 next
   case False
   then have "\<exists>w. read_data_cache s addr = Some w" by auto
   then have "\<exists>w. read_data_cache s addr = Some w \<and> 
     read_data_cache (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>) addr = Some w"
     using read_dcache_mod_state by metis
   then show ?thesis by auto
 qed
 
 lemma read_icache_mod_state: "read_instr_cache s addr = read_instr_cache 
 (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>) addr"
 apply (simp add: read_instr_cache_def)
 by (simp add: icache_val_def)
 
 lemma read_icache2_mod_state: 
 "fst (case read_instr_cache s addr of None \<Rightarrow> (None, s)
       | Some w \<Rightarrow> (Some w, s)) =
  fst (case read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>) addr of
          None \<Rightarrow> (None, (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>))
       | Some w \<Rightarrow> (Some w, (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>)))"
 proof (cases "read_instr_cache s addr = None")
   case True
   then have "read_instr_cache s addr = None \<and>
     read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>) addr = None"
     using read_icache_mod_state by metis
   then show ?thesis by auto    
 next
   case False
   then have "\<exists>w. read_instr_cache s addr = Some w" by auto
   then have "\<exists>w. read_instr_cache s addr = Some w \<and> 
     read_instr_cache (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>) addr = Some w"
     using read_icache_mod_state by metis
   then show ?thesis by auto
 qed
 
 lemma mem_read_mod_state: "fst (memory_read asi addr s) =
 fst (memory_read asi addr 
 (s\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>))"
 apply (simp add: memory_read_def)
 apply (case_tac "uint asi = 1")
  apply (simp add: Let_def)
  apply (metis load_word_mem_mod_state option.distinct(1))
 apply (case_tac "uint asi = 2")
  apply (simp add: Let_def)
  apply (simp add: sys_reg_val_def)
 apply (case_tac "uint asi \<in> {8,9}")
  apply (simp add: Let_def)
  apply (simp add: load_word_mem3_mod_state)
  apply (simp add: load_word_mem_mod_state)
 apply (case_tac "uint asi \<in> {10,11}")
  apply (simp add: Let_def)
  apply (simp add: load_word_mem2_mod_state)
  apply (simp add: load_word_mem_mod_state)
 apply (case_tac "uint asi = 13")
  apply (simp add: Let_def)
  apply (simp add: read_icache2_mod_state)
 apply (case_tac "uint asi = 15")
  apply (simp add: Let_def)
  apply (simp add: read_dcache2_mod_state)
 apply (case_tac "uint asi = 25")
  apply (simp add: Let_def)
 apply (case_tac "uint asi = 28")
  apply (simp add: Let_def)
  apply (simp add: mem_val_w32_mod_state)
 by (simp add: Let_def)
 
 lemma insert_trap_mem: "fst (memory_read asi addr s) =
 fst (memory_read asi addr (s\<lparr>traps := new_traps\<rparr>))"
 proof -
   have "fst (memory_read asi addr s) =
     fst (memory_read asi addr 
       (s\<lparr>cpu_reg := (cpu_reg s),
          user_reg := (user_reg s),
          dwrite := (dwrite s),
          state_var := (state_var s),
          traps := new_traps,
          undef := (undef s)\<rparr>))"
     using mem_read_mod_state by blast
     then show ?thesis by auto
 qed
 
 lemma cpu_reg_mod_mem: "fst (memory_read asi addr s) =
 fst (memory_read asi addr (s\<lparr>cpu_reg := new_cpu_reg\<rparr>))"
 proof -
   have "fst (memory_read asi addr s) =
     fst (memory_read asi addr 
       (s\<lparr>cpu_reg := new_cpu_reg,
          user_reg := (user_reg s),
          dwrite := (dwrite s),
          state_var := (state_var s),
          traps := (traps s),
          undef := (undef s)\<rparr>))"
     using mem_read_mod_state by blast
     then show ?thesis by auto
 qed
 
 lemma user_reg_mod_mem: "fst (memory_read asi addr s) =
 fst (memory_read asi addr (s\<lparr>user_reg := new_user_reg\<rparr>))"
 proof -
   have "fst (memory_read asi addr s) =
     fst (memory_read asi addr 
       (s\<lparr>cpu_reg := (cpu_reg s),
          user_reg := new_user_reg,
          dwrite := (dwrite s),
          state_var := (state_var s),
          traps := (traps s),
          undef := (undef s)\<rparr>))"
     using mem_read_mod_state by blast
     then show ?thesis by auto
 qed
 
 lemma annul_mem: "fst (memory_read asi addr s) =
 fst (memory_read asi addr 
 (s\<lparr>state_var := new_state_var,
    cpu_reg := new_cpu_reg\<rparr>))"
 proof -
   have "fst (memory_read asi addr s) =
     fst (memory_read asi addr 
       (s\<lparr>cpu_reg := new_cpu_reg,
          user_reg := (user_reg s),
          dwrite := (dwrite s),
          state_var := new_state_var,
          traps := (traps s),
          undef := (undef s)\<rparr>))"
     using mem_read_mod_state by blast
   then have "fst (memory_read asi addr s) =
     fst (memory_read asi addr 
       (s\<lparr>cpu_reg := new_cpu_reg,
          state_var := new_state_var\<rparr>))"
     by auto        
   then show ?thesis 
     by (metis Sparc_State.sparc_state.surjective Sparc_State.sparc_state.update_convs(1) Sparc_State.sparc_state.update_convs(8))
 qed
 
 lemma state_var_mod_mem: "fst (memory_read asi addr s) =
 fst (memory_read asi addr (s\<lparr>state_var := new_state_var\<rparr>))"
 proof -
   have "fst (memory_read asi addr s) =
     fst (memory_read asi addr 
       (s\<lparr>cpu_reg := (cpu_reg s),
          user_reg := (user_reg s),
          dwrite := (dwrite s),
          state_var := new_state_var,
          traps := (traps s),
          undef := (undef s)\<rparr>))"
     using mem_read_mod_state by blast
     then show ?thesis by auto
 qed
 
 lemma mod_state_low_equal: "low_equal s1 s2 \<and>
 t1 = (s1\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>) \<and>
 t2 = (s2\<lparr>cpu_reg := new_cpu_reg,
    user_reg := new_user_reg,
    dwrite := new_dwrite,
    state_var := new_state_var,
    traps := new_traps,
    undef := new_undef\<rparr>) \<Longrightarrow>
 low_equal t1 t2"
 apply (simp add: low_equal_def)
 apply clarsimp
 apply (simp add: mem_equal_def)
 by (simp add: user_accessible_def)
 
 lemma user_reg_state_mod_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>           
 t1 = (s1\<lparr>user_reg := new_user_reg\<rparr>) \<and>
 t2 = (s2\<lparr>user_reg := new_user_reg\<rparr>)"
 shows "low_equal t1 t2"
 proof -
   have "low_equal s1 s2 \<and>
 t1 = (s1\<lparr>cpu_reg := (cpu_reg s1),
    user_reg := new_user_reg,
    dwrite := (dwrite s1),
    state_var := (state_var s1),
    traps := (traps s1),
    undef := (undef s1)\<rparr>) \<and>
 t2 = (s2\<lparr>cpu_reg := (cpu_reg s2),
    user_reg := new_user_reg,
    dwrite := (dwrite s2),
    state_var := (state_var s2),
    traps := (traps s2),
    undef := (undef s2)\<rparr>) \<Longrightarrow>
 low_equal t1 t2"
     using mod_state_low_equal apply (simp add: low_equal_def)    
     apply (simp add: user_accessible_def mem_equal_def)
     by clarsimp
   then show ?thesis using a1
   by clarsimp
 qed
 
 lemma mod_trap_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>           
 t1 = (s1\<lparr>traps := new_traps\<rparr>) \<and>
 t2 = (s2\<lparr>traps := new_traps\<rparr>)"
 shows "low_equal t1 t2"
 proof -
   have "low_equal s1 s2 \<and>
 t1 = (s1\<lparr>cpu_reg := (cpu_reg s1),
    user_reg := (user_reg s1),
    dwrite := (dwrite s1),
    state_var := (state_var s1),
    traps := new_traps,
    undef := (undef s1)\<rparr>) \<and>
 t2 = (s2\<lparr>cpu_reg := (cpu_reg s2),
    user_reg := (user_reg s2),
    dwrite := (dwrite s2),
    state_var := (state_var s2),
    traps := new_traps,
    undef := (undef s2)\<rparr>) \<Longrightarrow>
 low_equal t1 t2"
     using mod_state_low_equal apply (simp add: low_equal_def)
     apply (simp add: user_accessible_def mem_equal_def)
     by clarsimp
   then show ?thesis using a1
   by clarsimp
 qed
 
 lemma state_var_low_equal: "low_equal s1 s2 \<Longrightarrow>
 state_var s1 = state_var s2"
 by (simp add: low_equal_def)
 
 lemma state_var2_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>           
 t1 = (s1\<lparr>state_var := new_state_var\<rparr>) \<and>
 t2 = (s2\<lparr>state_var := new_state_var\<rparr>)"
 shows "low_equal t1 t2"
 proof -
   have "low_equal s1 s2 \<and>
 t1 = (s1\<lparr>cpu_reg := (cpu_reg s1),
    user_reg := (user_reg s1),
    dwrite := (dwrite s1),
    state_var := new_state_var,
    traps := (traps s1),
    undef := (undef s1)\<rparr>) \<and>
 t2 = (s2\<lparr>cpu_reg := (cpu_reg s2),
    user_reg := (user_reg s2),
    dwrite := (dwrite s2),
    state_var := new_state_var,
    traps := (traps s2),
    undef := (undef s2)\<rparr>) \<Longrightarrow>
 low_equal t1 t2"
     using mod_state_low_equal apply (simp add: low_equal_def)
     apply (simp add: user_accessible_def mem_equal_def)
     by clarsimp   
   then show ?thesis using a1
   by clarsimp
 qed
 
 lemma traps_low_equal: "low_equal s1 s2 \<Longrightarrow> traps s1 = traps s2"
 by (simp add: low_equal_def)
 
 lemma s_low_equal: "low_equal s1 s2 \<Longrightarrow>
 (get_S (cpu_reg_val PSR s1)) = (get_S (cpu_reg_val PSR s2))"
 by (simp add: low_equal_def cpu_reg_val_def)
 
 lemma cpu_reg_val_low_equal: "low_equal s1 s2 \<Longrightarrow>
 (cpu_reg_val cr s1) = (cpu_reg_val cr s2)"
 by (simp add: cpu_reg_val_def low_equal_def)
 
 lemma get_curr_win_low_equal: "low_equal s1 s2 \<Longrightarrow>
 (fst (fst (get_curr_win () s1))) = (fst (fst (get_curr_win () s2)))"
 apply (simp add: low_equal_def)
 apply (simp add: get_curr_win_def cpu_reg_val_def get_CWP_def)
 by (simp add: simpler_gets_def)
 
 lemma get_curr_win2_low_equal: "low_equal s1 s2 \<Longrightarrow>
 t1 = (snd (fst (get_curr_win () s1))) \<Longrightarrow>
 t2 = (snd (fst (get_curr_win () s2))) \<Longrightarrow>
 low_equal t1 t2"
 apply (simp add: low_equal_def)
 apply (simp add: get_curr_win_def cpu_reg_val_def get_CWP_def)
 by (auto simp add: simpler_gets_def)
 
 lemma get_curr_win3_low_equal: "low_equal s1 s2 \<Longrightarrow>
 (traps (snd (fst (get_curr_win () s1)))) =
 (traps (snd (fst (get_curr_win () s2))))"
 using low_equal_def get_curr_win2_low_equal by blast
 
 lemma get_addr_low_equal: "low_equal s1 s2 \<Longrightarrow>
 ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s1)))))::word3) =
 ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s2)))))::word3) \<and>
 ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s1)))))::word2) =
 ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s2)))))::word2) \<and>
 ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s1)))))::word1) =
 ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s2)))))::word1)"
 apply (simp add: low_equal_def)
 apply (simp add: get_curr_win_def cpu_reg_val_def get_CWP_def)
 apply (simp add: simpler_gets_def get_addr_def user_reg_val_def)
 apply (simp add: Let_def )
 apply (simp add: get_CWP_def cpu_reg_val_def get_operand2_def)
 by (simp add: user_reg_val_def)
 
 lemma get_addr2_low_equal: "low_equal s1 s2 \<Longrightarrow>
 get_addr (snd instr) (snd (fst (get_curr_win () s1))) =
 get_addr (snd instr) (snd (fst (get_curr_win () s2)))"
 apply (simp add: low_equal_def)
 apply (simp add: get_curr_win_def cpu_reg_val_def get_CWP_def)
 apply (simp add: simpler_gets_def get_addr_def user_reg_val_def)
 apply (simp add: Let_def )
 apply (simp add: get_CWP_def cpu_reg_val_def get_operand2_def)
 by (simp add: user_reg_val_def)
 
 lemma sys_reg_low_equal: "low_equal s1 s2 \<Longrightarrow>
 sys_reg s1 = sys_reg s2"
 by (simp add: low_equal_def)
 
 lemma user_reg_low_equal: "low_equal s1 s2 \<Longrightarrow>
 user_reg s1 = user_reg s2"
 by (simp add: low_equal_def)
 
 lemma user_reg_val_low_equal: "low_equal s1 s2 \<Longrightarrow>
 user_reg_val win ur s1 = user_reg_val win ur s2"
 apply (simp add: user_reg_val_def)
 by (simp add: user_reg_low_equal)
 
 lemma get_operand2_low_equal: "low_equal s1 s2 \<Longrightarrow>
 get_operand2 op_list s1 = get_operand2 op_list s2"
 apply (simp add: get_operand2_def)
 apply (simp add: cpu_reg_val_low_equal)
 apply auto
 apply (simp add: user_reg_val_def)
 using user_reg_low_equal by fastforce
 
 lemma mem_val_mod_cache: "mem_val_alt asi a s = 
 mem_val_alt asi a (s\<lparr>cache := new_cache\<rparr>)"
 apply (simp add: mem_val_alt_def)
 by (simp add: Let_def)
 
 lemma mem_val_w32_mod_cache: "mem_val_w32 asi a s = 
 mem_val_w32 asi a (s\<lparr>cache := new_cache\<rparr>)"
 apply (simp add: mem_val_w32_def)
 apply (simp add: Let_def)
 by (metis mem_val_mod_cache)
 
 lemma load_word_mem_mod_cache: 
 "load_word_mem s addr asi =
 load_word_mem (s\<lparr>cache := new_cache\<rparr>) addr asi"
 apply (simp add: load_word_mem_def)
 apply (case_tac "virt_to_phys addr (mmu s) (mem s) = None")
  apply auto
 by (simp add: mem_val_w32_mod_cache)
 
 lemma memory_read_8_mod_cache:
 "fst (memory_read 8 addr s) = fst (memory_read 8 addr (s\<lparr>cache := new_cache\<rparr>))"
 apply (simp add: memory_read_def)
 apply (case_tac "sys_reg s CCR AND 1 \<noteq> 0")
  apply auto
  apply (simp add: option.case_eq_if load_word_mem_mod_cache)
  apply (auto intro: load_word_mem_mod_cache)
  apply (metis load_word_mem_mod_cache option.distinct(1))
 by (metis load_word_mem_mod_cache option.distinct(1))
 
 lemma memory_read_10_mod_cache:
 "fst (memory_read 10 addr s) = fst (memory_read 10 addr (s\<lparr>cache := new_cache\<rparr>))"
 apply (simp add: memory_read_def)
 apply (case_tac "sys_reg s CCR AND 1 \<noteq> 0")
  apply auto
  apply (simp add: option.case_eq_if load_word_mem_mod_cache)
  apply (auto intro: load_word_mem_mod_cache)
  apply (metis load_word_mem_mod_cache option.distinct(1))
 by (metis load_word_mem_mod_cache option.distinct(1))
 
 lemma mem_equal_mod_cache: "mem_equal s1 s2 pa \<Longrightarrow>
 mem_equal (s1\<lparr>cache := new_cache1\<rparr>) (s2\<lparr>cache := new_cache2\<rparr>) pa"
 by (simp add: mem_equal_def)
 
 lemma user_accessible_mod_cache: "user_accessible (s\<lparr>cache := new_cache\<rparr>) pa =
 user_accessible s pa"
 by (simp add: user_accessible_def)
 
 lemma mem_equal_mod_user_reg: "mem_equal s1 s2 pa \<Longrightarrow>
 mem_equal (s1\<lparr>user_reg := new_user_reg1\<rparr>) (s2\<lparr>user_reg := user_reg2\<rparr>) pa"
 by (simp add: mem_equal_def)
 
 lemma user_accessible_mod_user_reg: "user_accessible (s\<lparr>user_reg := new_user_reg\<rparr>) pa =
 user_accessible s pa"
 by (simp add: user_accessible_def)
 
 lemma mem_equal_mod_cpu_reg: "mem_equal s1 s2 pa \<Longrightarrow>
 mem_equal (s1\<lparr>cpu_reg := new_cpu1\<rparr>) (s2\<lparr>cpu_reg := cpu_reg2\<rparr>) pa"
 by (simp add: mem_equal_def)
 
 lemma user_accessible_mod_cpu_reg: "user_accessible (s\<lparr>cpu_reg := new_cpu_reg\<rparr>) pa =
 user_accessible s pa"
 by (simp add: user_accessible_def)
 
 lemma mem_equal_mod_trap: "mem_equal s1 s2 pa \<Longrightarrow>
 mem_equal (s1\<lparr>traps := new_traps1\<rparr>) (s2\<lparr>traps := traps2\<rparr>) pa"
 by (simp add: mem_equal_def)
 
 lemma user_accessible_mod_trap: "user_accessible (s\<lparr>traps := new_traps\<rparr>) pa =
 user_accessible s pa"
 by (simp add: user_accessible_def)
 
 lemma mem_equal_annul: "mem_equal s1 s2 pa \<Longrightarrow>
 mem_equal (s1\<lparr>state_var := new_state_var,
    cpu_reg := new_cpu_reg\<rparr>) (s2\<lparr>state_var := new_state_var2,
    cpu_reg := new_cpu_reg2\<rparr>) pa"
 by (simp add: mem_equal_def)
 
 lemma user_accessible_annul: "user_accessible (s\<lparr>state_var := new_state_var, 
   cpu_reg := new_cpu_reg\<rparr>) pa =
 user_accessible s pa"
 by (simp add: user_accessible_def)
 
 lemma mem_val_alt_10_mem_equal_0: "mem_equal s1 s2 pa \<Longrightarrow>
 mem_val_alt 10 (pa AND 68719476732) s1 = mem_val_alt 10 (pa AND 68719476732) s2"
 apply (simp add: mem_val_alt_def)
 apply (simp add: Let_def)
 apply (simp add: mem_equal_def)
 by (metis option.distinct(1))
 
 lemma mem_val_alt_10_mem_equal_1: "mem_equal s1 s2 pa \<Longrightarrow>
 mem_val_alt 10 ((pa AND 68719476732) + 1) s1 = mem_val_alt 10 ((pa AND 68719476732) + 1) s2"
 apply (simp add: mem_val_alt_def)
 apply (simp add: Let_def)
 apply (simp add: mem_equal_def)
 by (metis option.distinct(1))
 
 lemma mem_val_alt_10_mem_equal_2: "mem_equal s1 s2 pa \<Longrightarrow>
 mem_val_alt 10 ((pa AND 68719476732) + 2) s1 = mem_val_alt 10 ((pa AND 68719476732) + 2) s2"
 apply (simp add: mem_val_alt_def)
 apply (simp add: Let_def)
 apply (simp add: mem_equal_def)
 by (metis option.distinct(1))
 
 lemma mem_val_alt_10_mem_equal_3: "mem_equal s1 s2 pa \<Longrightarrow>
 mem_val_alt 10 ((pa AND 68719476732) + 3) s1 = mem_val_alt 10 ((pa AND 68719476732) + 3) s2"
 apply (simp add: mem_val_alt_def)
 apply (simp add: Let_def)
 apply (simp add: mem_equal_def)
 by (metis option.distinct(1))
 
 lemma mem_val_alt_10_mem_equal: 
 assumes a1: "mem_equal s1 s2 pa"
 shows "mem_val_alt 10 (pa AND 68719476732) s1 = mem_val_alt 10 (pa AND 68719476732) s2 \<and>
   mem_val_alt 10 ((pa AND 68719476732) + 1) s1 = mem_val_alt 10 ((pa AND 68719476732) + 1) s2 \<and>
   mem_val_alt 10 ((pa AND 68719476732) + 2) s1 = mem_val_alt 10 ((pa AND 68719476732) + 2) s2 \<and>
   mem_val_alt 10 ((pa AND 68719476732) + 3) s1 = mem_val_alt 10 ((pa AND 68719476732) + 3) s2"
 using mem_val_alt_10_mem_equal_0 mem_val_alt_10_mem_equal_1
 mem_val_alt_10_mem_equal_2 mem_val_alt_10_mem_equal_3 a1
 by blast
 
 lemma mem_val_w32_10_mem_equal: 
 assumes a1: "mem_equal s1 s2 a"
 shows "mem_val_w32 10 a s1 = mem_val_w32 10 a s2"
 apply (simp add: mem_val_w32_def)
 apply (simp add: Let_def)
 using mem_val_alt_10_mem_equal a1 apply auto
         apply fastforce 
        apply fastforce
       apply fastforce
      apply fastforce
     apply fastforce
    apply fastforce
   apply fastforce
  apply fastforce
 by fastforce
 
 lemma mem_val_alt_8_mem_equal_0: "mem_equal s1 s2 pa \<Longrightarrow>
 mem_val_alt 8 (pa AND 68719476732) s1 = mem_val_alt 8 (pa AND 68719476732) s2"
 apply (simp add: mem_val_alt_def)
 apply (simp add: Let_def)
 apply (simp add: mem_equal_def)
 by (metis option.distinct(1))
 
 lemma mem_val_alt_8_mem_equal_1: "mem_equal s1 s2 pa \<Longrightarrow>
 mem_val_alt 8 ((pa AND 68719476732) + 1) s1 = mem_val_alt 8 ((pa AND 68719476732) + 1) s2"
 apply (simp add: mem_val_alt_def)
 apply (simp add: Let_def)
 apply (simp add: mem_equal_def)
 by (metis option.distinct(1))
 
 lemma mem_val_alt_8_mem_equal_2: "mem_equal s1 s2 pa \<Longrightarrow>
 mem_val_alt 8 ((pa AND 68719476732) + 2) s1 = mem_val_alt 8 ((pa AND 68719476732) + 2) s2"
 apply (simp add: mem_val_alt_def)
 apply (simp add: Let_def)
 apply (simp add: mem_equal_def)
 by (metis option.distinct(1))
 
 lemma mem_val_alt_8_mem_equal_3: "mem_equal s1 s2 pa \<Longrightarrow>
 mem_val_alt 8 ((pa AND 68719476732) + 3) s1 = mem_val_alt 8 ((pa AND 68719476732) + 3) s2"
 apply (simp add: mem_val_alt_def)
 apply (simp add: Let_def)
 apply (simp add: mem_equal_def)
 by (metis option.distinct(1))
 
 lemma mem_val_alt_8_mem_equal: 
 assumes a1: "mem_equal s1 s2 pa"
 shows "mem_val_alt 8 (pa AND 68719476732) s1 = mem_val_alt 8 (pa AND 68719476732) s2 \<and>
   mem_val_alt 8 ((pa AND 68719476732) + 1) s1 = mem_val_alt 8 ((pa AND 68719476732) + 1) s2 \<and>
   mem_val_alt 8 ((pa AND 68719476732) + 2) s1 = mem_val_alt 8 ((pa AND 68719476732) + 2) s2 \<and>
   mem_val_alt 8 ((pa AND 68719476732) + 3) s1 = mem_val_alt 8 ((pa AND 68719476732) + 3) s2"
 using mem_val_alt_8_mem_equal_0 mem_val_alt_8_mem_equal_1
 mem_val_alt_8_mem_equal_2 mem_val_alt_8_mem_equal_3 a1
 by blast
 
 lemma mem_val_w32_8_mem_equal: 
 assumes a1: "mem_equal s1 s2 a"
 shows "mem_val_w32 8 a s1 = mem_val_w32 8 a s2"
 apply (simp add: mem_val_w32_def)
 apply (simp add: Let_def)
 using mem_val_alt_8_mem_equal a1 apply auto
         apply fastforce 
        apply fastforce
       apply fastforce
      apply fastforce
     apply fastforce
    apply fastforce
   apply fastforce
  apply fastforce
 by fastforce
 
 lemma load_word_mem_10_low_equal: 
 assumes a1: "low_equal s1 s2"
 shows "load_word_mem s1 address 10 = load_word_mem s2 address 10"
 using a1 apply (simp add: low_equal_def load_word_mem_def)
 apply clarsimp
 apply (case_tac "virt_to_phys address (mmu s2) (mem s2) = None")
  apply auto
  apply (simp add: user_accessible_def)
  using mem_val_w32_10_mem_equal apply blast 
 apply (simp add: user_accessible_def)
 using mem_val_w32_10_mem_equal by blast 
 
 lemma load_word_mem_8_low_equal: 
 assumes a1: "low_equal s1 s2"
 shows "load_word_mem s1 address 8 = load_word_mem s2 address 8"
 using a1 apply (simp add: low_equal_def load_word_mem_def)
 apply clarsimp
 apply (case_tac "virt_to_phys address (mmu s2) (mem s2) = None")
  apply auto
  apply (simp add: user_accessible_def)
  using mem_val_w32_8_mem_equal user_accessible_8 apply fastforce
 apply (simp add: user_accessible_def)
 using mem_val_w32_8_mem_equal user_accessible_8 by fastforce
 
 lemma mem_read_low_equal: 
 assumes a1: "low_equal s1 s2 \<and> asi \<in> {8,10}"
 shows "fst (memory_read asi address s1) = fst (memory_read asi address s2)"
 proof (cases "asi = 8")
   case True
   then show ?thesis using a1 
   apply (simp add: low_equal_def)
   apply (simp add: memory_read_def)
   using a1 load_word_mem_8_low_equal apply auto
   apply (simp add: option.case_eq_if)
   by (simp add: option.case_eq_if)
 next
   case False
   then have "asi = 10" using a1 by auto
   then show ?thesis using a1
   apply (simp add: low_equal_def)
   apply (simp add: memory_read_def)
   using a1 load_word_mem_10_low_equal apply auto
   apply (simp add: option.case_eq_if)
   by (simp add: option.case_eq_if)
 qed 
 
 lemma read_mem_pc_low_equal: 
 assumes a1: "low_equal s1 s2"
 shows "fst (memory_read 8 (cpu_reg_val PC s1) s1) = 
 fst (memory_read 8 (cpu_reg_val PC s2) s2)"
 proof -
   have f2: "cpu_reg_val PC s1 = cpu_reg_val PC s2" using a1 
     by (simp add: low_equal_def cpu_reg_val_def)
   then show ?thesis using a1 f2 mem_read_low_equal
     by auto
 qed
 
 lemma dcache_mod_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>
 t1 = dcache_mod c v s1 \<and>
 t2 = dcache_mod c v s2"
 shows "low_equal t1 t2"
 using a1 apply (simp add: low_equal_def)
 apply (simp add: dcache_mod_def)
 apply auto
  apply (simp add: user_accessible_mod_cache mem_equal_mod_cache)
 by (simp add: user_accessible_mod_cache mem_equal_mod_cache)
 
 lemma add_data_cache_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>
 t1 = add_data_cache s1 address w bm \<and>
 t2 = add_data_cache s2 address w bm"
 shows "low_equal t1 t2"
 using a1 apply (simp add: add_data_cache_def)
 apply (case_tac "bm AND 8 >> 3 = 1")
  apply auto
  apply (case_tac "bm AND 4 >> 2 = 1")
   apply auto
   apply (case_tac "bm AND 2 >> Suc 0 = 1")
    apply auto
    apply (case_tac "bm AND 1 = 1")
     apply auto
     apply (meson dcache_mod_low_equal)
    apply (meson dcache_mod_low_equal)
   apply (case_tac "bm AND 1 = 1")
    apply auto
    apply (meson dcache_mod_low_equal)
   apply (meson dcache_mod_low_equal)
  apply (case_tac "bm AND 2 >> Suc 0 = 1")
   apply auto
   apply (case_tac "bm AND 1 = 1")
    apply auto
    apply (meson dcache_mod_low_equal)
   apply (meson dcache_mod_low_equal)
  apply (case_tac "bm AND 1 = 1")
   apply auto
   apply (meson dcache_mod_low_equal)
  apply (meson dcache_mod_low_equal)
 apply (case_tac "bm AND 4 >> 2 = 1")
  apply auto
  apply (case_tac "bm AND 2 >> Suc 0 = 1")
   apply auto
   apply (case_tac "bm AND 1 = 1")
    apply auto
    apply (meson dcache_mod_low_equal)
   apply (meson dcache_mod_low_equal)
  apply (case_tac "bm AND 1 = 1")
   apply auto
   apply (meson dcache_mod_low_equal)
  apply (meson dcache_mod_low_equal)
 apply (case_tac "bm AND 2 >> Suc 0 = 1")
  apply auto
  apply (case_tac "bm AND 1 = 1")
   apply auto
   apply (meson dcache_mod_low_equal)
  apply (meson dcache_mod_low_equal)
 by (meson dcache_mod_low_equal)
 
 lemma mem_read2_low_equal:
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (memory_read (10::word8) address s1) \<and>
 t2 = snd (memory_read (10::word8) address s2)"
 shows "low_equal t1 t2"
 using a1 apply (simp add: memory_read_def)
 using a1 apply (auto simp add: sys_reg_low_equal)
 using a1 apply (simp add: load_word_mem_10_low_equal)
 by (metis (no_types, lifting) add_data_cache_low_equal option.case_eq_if snd_conv)
 
 lemma mem_read_delayed_write_low_equal:
 assumes a1: "low_equal s1 s2 \<and> get_delayed_pool s1 = [] \<and> get_delayed_pool s2 = []"
 shows "fst (memory_read 8 (cpu_reg_val PC (delayed_pool_write s1)) (delayed_pool_write s1)) =
 fst (memory_read 8 (cpu_reg_val PC (delayed_pool_write s2)) (delayed_pool_write s2))"
 using a1 apply (simp add: delayed_pool_write_def)
 apply (simp add: Let_def)
 apply (simp add: get_delayed_write_def)
 by (simp add: read_mem_pc_low_equal)
 
 lemma global_reg_mod_low_equal: 
 assumes a1: "low_equal s1 s2\<and>
 t1 = (global_reg_mod w n rd s1) \<and>
 t2 = (global_reg_mod w n rd s2)"
 shows "low_equal t1 t2"
 using a1 apply (induction n arbitrary: s1 s2)
  apply clarsimp
 apply auto
 apply (simp add: Let_def)
 apply (simp add: user_reg_low_equal)
 using user_reg_state_mod_low_equal by blast
 
 lemma out_reg_mod_low_equal: 
 assumes a1: "low_equal s1 s2\<and>
 t1 = (out_reg_mod w curr_win rd s1) \<and>
 t2 = (out_reg_mod w curr_win rd s2)"
 shows "low_equal t1 t2"
 using a1 apply (simp add: out_reg_mod_def Let_def)
 apply auto
  apply (simp add: user_reg_low_equal)
  using user_reg_state_mod_low_equal apply fastforce
 apply (simp add: user_reg_low_equal)
 using user_reg_state_mod_low_equal by blast
 
 lemma in_reg_mod_low_equal: 
 assumes a1: "low_equal s1 s2\<and>
 t1 = (in_reg_mod w curr_win rd s1) \<and>
 t2 = (in_reg_mod w curr_win rd s2)"
 shows "low_equal t1 t2"
 using a1 apply (simp add: in_reg_mod_def Let_def)
 apply auto
  apply (simp add: user_reg_low_equal)
  using user_reg_state_mod_low_equal apply fastforce
 apply (simp add: user_reg_low_equal)
 using user_reg_state_mod_low_equal by blast
 
 lemma user_reg_mod_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>
 t1 = user_reg_mod w curr_win rd s1 \<and> t2 = user_reg_mod w curr_win rd s2"
 shows "low_equal t1 t2"
 proof (cases "rd = 0")
   case True
   then show ?thesis using a1
   by (simp add: user_reg_mod_def)
 next
   case False
   then have f1: "rd \<noteq> 0" by auto
   then show ?thesis 
   proof (cases "0 < rd \<and> rd < 8")
     case True
     then show ?thesis using a1 f1
     apply (simp add: user_reg_mod_def)
     using global_reg_mod_low_equal by blast    
   next
     case False
     then have f2: "\<not> (0 < rd \<and> rd < 8)" by auto
     then show ?thesis  
     proof (cases "7 < rd \<and> rd < 16")
       case True
       then show ?thesis using a1 f1 f2
       apply (simp add: user_reg_mod_def)
       by (auto intro: out_reg_mod_low_equal)
     next
       case False
       then have f3: "\<not> (7 < rd \<and> rd < 16)" by auto      
       then show ?thesis 
       proof (cases "15 < rd \<and> rd < 24")
         case True
         then show ?thesis using a1 f1 f2 f3
         apply (simp add: user_reg_mod_def)
         apply (simp add: low_equal_def)
         apply clarsimp
         by (simp add: user_accessible_mod_user_reg mem_equal_mod_user_reg)     
       next
         case False
         then show ?thesis using a1 f1 f2 f3
         apply (simp add: user_reg_mod_def)
         by (auto intro: in_reg_mod_low_equal)
       qed
     qed
   qed
 qed
 
 lemma virt_to_phys_low_equal: "low_equal s1 s2 \<Longrightarrow>
 virt_to_phys addr (mmu s1) (mem s1) = virt_to_phys addr (mmu s2) (mem s2)"
 by (auto simp add: low_equal_def)
 
 lemma write_reg_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>
 t1 = (snd (fst (write_reg w curr_win rd s1))) \<and>
 t2 = (snd (fst (write_reg w curr_win rd s2)))"
 shows "low_equal t1 t2"
 using a1 apply (simp add: write_reg_def)
 apply (simp add: simpler_modify_def)
 by (auto intro: user_reg_mod_low_equal)
 
 lemma write_cpu_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (write_cpu w cr s1)) \<and>
 t2 = (snd (fst (write_cpu w cr s2)))"
 shows "low_equal t1 t2"
 using a1
 apply (simp add: write_cpu_def simpler_modify_def)
 apply (simp add: cpu_reg_mod_def)
 apply (simp add: low_equal_def)
 using user_accessible_mod_cpu_reg mem_equal_mod_cpu_reg
 by metis
 
 lemma cpu_reg_mod_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>
 t1 = cpu_reg_mod w cr s1 \<and>
 t2 = cpu_reg_mod w cr s2"
 shows "low_equal t1 t2"
 using a1
 apply (simp add: cpu_reg_mod_def)
 apply (simp add: low_equal_def)
 using user_accessible_mod_cpu_reg mem_equal_mod_cpu_reg
 by metis
 
 lemma load_sub2_low_equal:
 assumes a1: "low_equal s1 s2 \<and>
 t1 = (snd (fst (load_sub2 address 10 rd curr_win w s1))) \<and>
 t2 = (snd (fst (load_sub2 address 10 rd curr_win w s2)))"
 shows "low_equal t1 t2"
 proof (cases "fst (memory_read 10 (address + 4)
         (snd (fst (write_reg w curr_win (rd AND 30) s1)))) = None")
   case True
   then have f0: "fst (memory_read 10 (address + 4) 
         (snd (fst (write_reg w curr_win (rd AND 30) s1)))) = None" by auto
   have f1: "low_equal (snd (fst (write_reg w curr_win (rd AND 30) s1)))
           (snd (fst (write_reg w curr_win (rd AND 30) s2)))"
     using a1 by (auto intro: write_reg_low_equal)
   then have "fst (memory_read 10 (address + 4)
         (snd (fst (write_reg w curr_win (rd AND 30) s1)))) = None \<and>
         fst (memory_read 10 (address + 4)
         (snd (fst (write_reg w curr_win (rd AND 30) s1)))) =
         fst (memory_read 10 (address + 4)
         (snd (fst (write_reg w curr_win (rd AND 30) s2))))"
     using f0 by (blast intro: mem_read_low_equal)
   then have "fst (memory_read 10 (address + 4)
         (snd (fst (write_reg w curr_win (rd AND 30) s1)))) = None \<and>
         fst (memory_read 10 (address + 4)
         (snd (fst (write_reg w curr_win (rd AND 30) s2)))) = None"
     by auto
   then show ?thesis using a1
   apply (simp add: load_sub2_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   apply (simp add: case_prod_unfold)
   apply (simp add: raise_trap_def add_trap_set_def)
   apply (simp add: simpler_modify_def)
   using f1 apply (simp add: traps_low_equal)
   using f1 by (auto intro: mod_trap_low_equal)
 next
   case False
   then have f2: "fst (memory_read 10 (address + 4)
         (snd (fst (write_reg w curr_win (rd AND 30) s1)))) \<noteq> None"
     by auto
   have f3: "low_equal (snd (fst (write_reg w curr_win (rd AND 30) s1)))
           (snd (fst (write_reg w curr_win (rd AND 30) s2)))"
     using a1 by (auto intro: write_reg_low_equal)
   then have f4: "fst (memory_read 10 (address + 4)
         (snd (fst (write_reg w curr_win (rd AND 30) s1)))) =
         fst (memory_read 10 (address + 4)
         (snd (fst (write_reg w curr_win (rd AND 30) s2))))"
     using f2 by (blast intro: mem_read_low_equal)
   then have "fst (memory_read 10 (address + 4)
         (snd (fst (write_reg w curr_win (rd AND 30) s1)))) \<noteq> None \<and>
         fst (memory_read 10 (address + 4)
         (snd (fst (write_reg w curr_win (rd AND 30) s2)))) \<noteq> None"
     using f2 by auto
   then show ?thesis using a1
   apply (simp add: load_sub2_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   apply (simp add: case_prod_unfold)
   apply clarsimp
   apply (simp add: simpler_modify_def bind_def h1_def h2_def Let_def)
   using f4 apply clarsimp
   using f3 by (auto intro: mem_read2_low_equal write_reg_low_equal)
 qed
 
 lemma load_sub3_low_equal:
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (load_sub3 instr curr_win rd (10::word8) address s1)) \<and>
 t2 = snd (fst (load_sub3 instr curr_win rd (10::word8) address s2))"
 shows "low_equal t1 t2"
 proof (cases "fst (memory_read 10 address s1) = None")
   case True
   then have "fst (memory_read 10 address s1) = None \<and>
     fst (memory_read 10 address s2) = None"
     using a1 by (auto simp add: mem_read_low_equal)
   then show ?thesis using a1
   apply (simp add: load_sub3_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def)
   apply (simp add: case_prod_unfold)
   apply (simp add: raise_trap_def add_trap_set_def)
   apply (simp add: simpler_modify_def)
   apply (auto simp add: traps_low_equal)
   by (auto intro: mod_trap_low_equal)
 next
   case False
   then have f1: "fst (memory_read 10 address s1) \<noteq> None \<and> 
     fst (memory_read 10 address s2) \<noteq> None"
     using a1 by (auto simp add: mem_read_low_equal)  
   then show ?thesis 
   proof (cases "rd \<noteq> 0 \<and>
                           (fst instr = load_store_type LD \<or>
                            fst instr = load_store_type LDA \<or>
                            fst instr = load_store_type LDUH \<or>
                            fst instr = load_store_type LDSB \<or>
                            fst instr = load_store_type LDUB \<or>
                            fst instr = load_store_type LDUBA \<or>
                            fst instr = load_store_type LDSH \<or>
                            fst instr = load_store_type LDSHA \<or>
                            fst instr = load_store_type LDUHA \<or>
                            fst instr = load_store_type LDSBA)")
     case True
     then show ?thesis using a1 f1
     apply (simp add: load_sub3_def)
     apply (simp add: simpler_gets_def bind_def h1_def h2_def)
     apply (simp add: case_prod_unfold)
     apply clarsimp
     apply (simp add: simpler_modify_def bind_def h1_def h2_def Let_def)
     apply (simp add: mem_read_low_equal)
     by (meson mem_read2_low_equal write_reg_low_equal)
   next
     case False
     then show ?thesis using a1 f1
     apply (simp add: load_sub3_def)
     apply (simp add: simpler_gets_def bind_def h1_def h2_def)
     apply (simp add: case_prod_unfold)
     apply clarsimp
     apply (simp add: simpler_modify_def bind_def h1_def h2_def Let_def)
     apply (simp add: mem_read_low_equal)
     by (meson load_sub2_low_equal mem_read2_low_equal)
   qed
 qed
 
 lemma ld_asi_user:
 "(fst instr = load_store_type LDSB \<or>
 fst instr = load_store_type LDUB \<or>
 fst instr = load_store_type LDUH \<or> 
 fst instr = load_store_type LD \<or> 
 fst instr = load_store_type LDD) \<Longrightarrow> 
 ld_asi instr 0 = 10"
 apply (simp add: ld_asi_def)
 by auto
 
 lemma load_sub1_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>
 (fst instr = load_store_type LDSB \<or>
 fst instr = load_store_type LDUB \<or>
 fst instr = load_store_type LDUH \<or>
 fst instr = load_store_type LD \<or> 
 fst instr = load_store_type LDD) \<and>
 t1 = snd (fst (load_sub1 instr rd 0 s1)) \<and> 
 t2 = snd (fst (load_sub1 instr rd 0 s2))" 
 shows "low_equal t1 t2"
 proof (cases "(fst instr = load_store_type LDD \<or> fst instr = load_store_type LDDA) \<and>
                        ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s1)))))::word3) \<noteq> 0 \<or>
                        (fst instr = load_store_type LD \<or> fst instr = load_store_type LDA) \<and>
                        ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s1)))))::word2) \<noteq> 0 \<or>
                        (fst instr = load_store_type LDUH \<or>
                         fst instr = load_store_type LDUHA \<or>
                         fst instr = load_store_type LDSH \<or> fst instr = load_store_type LDSHA) \<and>
                        ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s1)))))::word1) \<noteq> 0")
   case True
   then have "((fst instr = load_store_type LDD \<or> fst instr = load_store_type LDDA) \<and>
                        ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s1)))))::word3) \<noteq> 0 \<or>
                        (fst instr = load_store_type LD \<or> fst instr = load_store_type LDA) \<and>
                        ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s1)))))::word2) \<noteq> 0 \<or>
                        (fst instr = load_store_type LDUH \<or>
                         fst instr = load_store_type LDUHA \<or>
                         fst instr = load_store_type LDSH \<or> fst instr = load_store_type LDSHA) \<and>
                        ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s1)))))::word1) \<noteq> 0) \<and>
             ((fst instr = load_store_type LDD \<or> fst instr = load_store_type LDDA) \<and>
                        ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s2)))))::word3) \<noteq> 0 \<or>
                        (fst instr = load_store_type LD \<or> fst instr = load_store_type LDA) \<and>
                        ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s2)))))::word2) \<noteq> 0 \<or>
                        (fst instr = load_store_type LDUH \<or>
                         fst instr = load_store_type LDUHA \<or>
                         fst instr = load_store_type LDSH \<or> fst instr = load_store_type LDSHA) \<and>
                        ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s2)))))::word1) \<noteq> 0)"
     by (metis (mono_tags, lifting) assms get_addr_low_equal)    
   then show ?thesis using a1
   apply (simp add: load_sub1_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   apply (simp add: case_prod_unfold)
   apply (simp add: raise_trap_def add_trap_set_def)
   apply (simp add: simpler_modify_def)
   apply clarsimp
   apply (simp add: get_curr_win3_low_equal)
   by (auto intro: get_curr_win2_low_equal mod_trap_low_equal)
 next
   case False
   then have f1: "\<not> ((fst instr = load_store_type LDD \<or> fst instr = load_store_type LDDA) \<and>
                        ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s1)))))::word3) \<noteq> 0 \<or>
                        (fst instr = load_store_type LD \<or> fst instr = load_store_type LDA) \<and>
                        ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s1)))))::word2) \<noteq> 0 \<or>
                        (fst instr = load_store_type LDUH \<or>
                         fst instr = load_store_type LDUHA \<or>
                         fst instr = load_store_type LDSH \<or> fst instr = load_store_type LDSHA) \<and>
                        ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s1)))))::word1) \<noteq> 0) \<and>
             \<not> ((fst instr = load_store_type LDD \<or> fst instr = load_store_type LDDA) \<and>
                        ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s2)))))::word3) \<noteq> 0 \<or>
                        (fst instr = load_store_type LD \<or> fst instr = load_store_type LDA) \<and>
                        ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s2)))))::word2) \<noteq> 0 \<or>
                        (fst instr = load_store_type LDUH \<or>
                         fst instr = load_store_type LDUHA \<or>
                         fst instr = load_store_type LDSH \<or> fst instr = load_store_type LDSHA) \<and>
                        ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s2)))))::word1) \<noteq> 0)"
     by (metis assms get_addr_low_equal)    
   show ?thesis  
   proof -
     have "low_equal s1 s2 \<Longrightarrow> 
           low_equal (snd (fst (get_curr_win () s1))) 
                     (snd (fst (get_curr_win () s2)))"
       using get_curr_win2_low_equal by auto
     then have f2: "low_equal s1 s2 \<Longrightarrow>
       low_equal (snd (fst (load_sub3 instr (fst (fst (get_curr_win () s2))) rd 10
                     (get_addr (snd instr) (snd (fst (get_curr_win () s2))))
                     (snd (fst (get_curr_win () s1)))))) 
                 (snd (fst (load_sub3 instr (fst (fst (get_curr_win () s2))) rd 10
                     (get_addr (snd instr) (snd (fst (get_curr_win () s2))))
                     (snd (fst (get_curr_win () s2))))))"
       using load_sub3_low_equal by blast 
     show ?thesis using a1
     unfolding load_sub1_def simpler_gets_def bind_def h1_def h2_def Let_def case_prod_unfold
     using f1 f2 apply clarsimp
     by (simp add: get_addr2_low_equal get_curr_win_low_equal ld_asi_user)
   qed
 qed
 
 lemma load_instr_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>
 (fst instr = load_store_type LDSB \<or>
 fst instr = load_store_type LDUB \<or>
 fst instr = load_store_type LDUBA \<or>
 fst instr = load_store_type LDUH \<or>
 fst instr = load_store_type LD \<or> 
 fst instr = load_store_type LDA \<or> 
 fst instr = load_store_type LDD) \<and>
 ((ucast (get_S (cpu_reg_val PSR s1)))::word1) = 0 \<and>
 ((ucast (get_S (cpu_reg_val PSR s2)))::word1) = 0 \<and>
 t1 = snd (fst (load_instr instr s1)) \<and> t2 = snd (fst (load_instr instr s2))"
 shows "low_equal t1 t2"
 proof -
   have "get_S (cpu_reg_val PSR s1) = 0 \<and> get_S (cpu_reg_val PSR s2) = 0"
     using a1 by (simp add: ucast_id) 
   then show ?thesis using a1
   apply (simp add: load_instr_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def)
   apply (simp add: Let_def)
   apply clarsimp
   apply (simp add: raise_trap_def add_trap_set_def)
   apply (simp add: simpler_modify_def)
   apply (simp add: traps_low_equal)
   by (auto intro: mod_trap_low_equal load_sub1_low_equal)
 qed
 
 lemma st_data0_low_equal: "low_equal s1 s2 \<Longrightarrow>
 st_data0 instr curr_win rd addr s1 = st_data0 instr curr_win rd addr s2"
 apply (simp add: st_data0_def)
 by (simp add: user_reg_val_def low_equal_def)
 
 lemma store_word_mem_low_equal_none: "low_equal s1 s2 \<Longrightarrow>
 store_word_mem (add_data_cache s1 addr data bm) addr data bm 10 = None \<Longrightarrow>
 store_word_mem (add_data_cache s2 addr data bm) addr data bm 10 = None"
 apply (simp add: store_word_mem_def)
 proof -
   assume a1: "low_equal s1 s2"
   assume a2: "(case virt_to_phys addr (mmu (add_data_cache s1 addr data bm)) (mem (add_data_cache s1 addr data bm)) of None \<Rightarrow> None | Some pair \<Rightarrow> if mmu_writable (get_acc_flag (snd pair)) 10 then Some (mem_mod_w32 10 (fst pair) bm data (add_data_cache s1 addr data bm)) else None) = None"
   have f3: "(if mmu_writable (get_acc_flag (snd (v1_2 (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)))))) 10 then Some (mem_mod_w32 10 (fst (v1_2 (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm))))) bm data (add_data_cache s2 addr data bm)) else None) = (case Some (v1_2 (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)))) of None \<Rightarrow> if mmu_writable (get_acc_flag (snd (v1_2 (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)))))) 10 then Some (mem_mod_w32 10 (fst (v1_2 (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm))))) bm data (add_data_cache s1 addr data bm)) else None | Some p \<Rightarrow> if mmu_writable (get_acc_flag (snd p)) 10 then Some (mem_mod_w32 10 (fst p) bm data (add_data_cache s2 addr data bm)) else None)"
     by auto
   obtain pp :: "(word36 \<times> word8) option \<Rightarrow> word36 \<times> word8" where
     f4: "virt_to_phys addr (mmu (add_data_cache s1 addr data bm)) (mem (add_data_cache s1 addr data bm)) = None \<or> virt_to_phys addr (mmu (add_data_cache s1 addr data bm)) (mem (add_data_cache s1 addr data bm)) = Some (pp (virt_to_phys addr (mmu (add_data_cache s1 addr data bm)) (mem (add_data_cache s1 addr data bm))))"
     by (metis (no_types) option.exhaust)
   have f5: "virt_to_phys addr (mmu (add_data_cache s1 addr data bm)) (mem (add_data_cache s1 addr data bm)) = virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm))"
     using a1 by (meson add_data_cache_low_equal virt_to_phys_low_equal)
   { assume "Some (mem_mod_w32 10 (fst (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm))))) bm data (add_data_cache s1 addr data bm)) \<noteq> (case Some (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)))) of None \<Rightarrow> None | Some p \<Rightarrow> if mmu_writable (get_acc_flag (snd p)) 10 then Some (mem_mod_w32 10 (fst p) bm data (add_data_cache s1 addr data bm)) else None)"
     then have "None = (if mmu_writable (get_acc_flag (snd (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)))))) 10 then Some (mem_mod_w32 10 (fst (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm))))) bm data (add_data_cache s2 addr data bm)) else None)"
       by fastforce
     moreover
     { assume "(if mmu_writable (get_acc_flag (snd (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)))))) 10 then Some (mem_mod_w32 10 (fst (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm))))) bm data (add_data_cache s2 addr data bm)) else None) \<noteq> (case virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)) of None \<Rightarrow> None | Some p \<Rightarrow> if mmu_writable (get_acc_flag (snd p)) 10 then Some (mem_mod_w32 10 (fst p) bm data (add_data_cache s2 addr data bm)) else None)"
       then have "(case Some (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)))) of None \<Rightarrow> if mmu_writable (get_acc_flag (snd (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)))))) 10 then Some (mem_mod_w32 10 (fst (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm))))) bm data (add_data_cache s1 addr data bm)) else None | Some p \<Rightarrow> if mmu_writable (get_acc_flag (snd p)) 10 then Some (mem_mod_w32 10 (fst p) bm data (add_data_cache s2 addr data bm)) else None) \<noteq> (case virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)) of None \<Rightarrow> None | Some p \<Rightarrow> if mmu_writable (get_acc_flag (snd p)) 10 then Some (mem_mod_w32 10 (fst p) bm data (add_data_cache s2 addr data bm)) else None)"
         using f3 by simp
       then have "Some (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)))) \<noteq> virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)) \<or> (if mmu_writable (get_acc_flag (snd (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)))))) 10 then Some (mem_mod_w32 10 (fst (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm))))) bm data (add_data_cache s1 addr data bm)) else None) \<noteq> None"
       proof -
         have "(case virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)) of None \<Rightarrow> if mmu_writable (get_acc_flag (snd (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)))))) 10 then Some (mem_mod_w32 10 (fst (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm))))) bm data (add_data_cache s1 addr data bm)) else None | Some p \<Rightarrow> if mmu_writable (get_acc_flag (snd p)) 10 then Some (mem_mod_w32 10 (fst p) bm data (add_data_cache s2 addr data bm)) else None) = (case virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)) of None \<Rightarrow> None | Some p \<Rightarrow> if mmu_writable (get_acc_flag (snd p)) 10 then Some (mem_mod_w32 10 (fst p) bm data (add_data_cache s2 addr data bm)) else None) \<or> Some (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)))) \<noteq> virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)) \<or> (if mmu_writable (get_acc_flag (snd (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)))))) 10 then Some (mem_mod_w32 10 (fst (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm))))) bm data (add_data_cache s1 addr data bm)) else None) \<noteq> None"
           by simp
         then show ?thesis
           using \<open>(case Some (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)))) of None \<Rightarrow> if mmu_writable (get_acc_flag (snd (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)))))) 10 then Some (mem_mod_w32 10 (fst (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm))))) bm data (add_data_cache s1 addr data bm)) else None | Some p \<Rightarrow> if mmu_writable (get_acc_flag (snd p)) 10 then Some (mem_mod_w32 10 (fst p) bm data (add_data_cache s2 addr data bm)) else None) \<noteq> (case virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)) of None \<Rightarrow> None | Some p \<Rightarrow> if mmu_writable (get_acc_flag (snd p)) 10 then Some (mem_mod_w32 10 (fst p) bm data (add_data_cache s2 addr data bm)) else None)\<close> by force
       qed
       moreover
       { assume "Some (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)))) \<noteq> virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm))"
         then have "virt_to_phys addr (mmu (add_data_cache s1 addr data bm)) (mem (add_data_cache s1 addr data bm)) \<noteq> Some (pp (virt_to_phys addr (mmu (add_data_cache s1 addr data bm)) (mem (add_data_cache s1 addr data bm))))"
           using f5 by simp }
       ultimately have "virt_to_phys addr (mmu (add_data_cache s1 addr data bm)) (mem (add_data_cache s1 addr data bm)) \<noteq> Some (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)))) \<or> virt_to_phys addr (mmu (add_data_cache s1 addr data bm)) (mem (add_data_cache s1 addr data bm)) \<noteq> Some (pp (virt_to_phys addr (mmu (add_data_cache s1 addr data bm)) (mem (add_data_cache s1 addr data bm))))"
         using a2 by force }
     ultimately have "virt_to_phys addr (mmu (add_data_cache s1 addr data bm)) (mem (add_data_cache s1 addr data bm)) = Some (pp (virt_to_phys addr (mmu (add_data_cache s1 addr data bm)) (mem (add_data_cache s1 addr data bm)))) \<and> virt_to_phys addr (mmu (add_data_cache s1 addr data bm)) (mem (add_data_cache s1 addr data bm)) = Some (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)))) \<longrightarrow> (case virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)) of None \<Rightarrow> None | Some p \<Rightarrow> if mmu_writable (get_acc_flag (snd p)) 10 then Some (mem_mod_w32 10 (fst p) bm data (add_data_cache s2 addr data bm)) else None) = None"
       by fastforce }
   then have "virt_to_phys addr (mmu (add_data_cache s1 addr data bm)) (mem (add_data_cache s1 addr data bm)) = Some (pp (virt_to_phys addr (mmu (add_data_cache s1 addr data bm)) (mem (add_data_cache s1 addr data bm)))) \<and> virt_to_phys addr (mmu (add_data_cache s1 addr data bm)) (mem (add_data_cache s1 addr data bm)) = Some (pp (virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)))) \<longrightarrow> (case virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)) of None \<Rightarrow> None | Some p \<Rightarrow> if mmu_writable (get_acc_flag (snd p)) 10 then Some (mem_mod_w32 10 (fst p) bm data (add_data_cache s2 addr data bm)) else None) = None"
     using a2 by force
   then show "(case virt_to_phys addr (mmu (add_data_cache s2 addr data bm)) (mem (add_data_cache s2 addr data bm)) of None \<Rightarrow> None | Some p \<Rightarrow> if mmu_writable (get_acc_flag (snd p)) 10 then Some (mem_mod_w32 10 (fst p) bm data (add_data_cache s2 addr data bm)) else None) = None"
     using f5 f4 by force
 qed
 
 lemma memory_write_asi_low_equal_none: "low_equal s1 s2 \<Longrightarrow>
 memory_write_asi 10 addr bm data s1 = None \<Longrightarrow>
 memory_write_asi 10 addr bm data s2 = None"
 apply (simp add: memory_write_asi_def)
 by (simp add: store_word_mem_low_equal_none)
 
 lemma memory_write_low_equal_none: "low_equal s1 s2 \<Longrightarrow>
 memory_write 10 addr bm data s1 = None \<Longrightarrow>
 memory_write 10 addr bm data s2 = None"
 apply (simp add: memory_write_def)
 by (metis map_option_case memory_write_asi_low_equal_none option.map_disc_iff)
 
 lemma memory_write_low_equal_none2: "low_equal s1 s2 \<Longrightarrow>
 memory_write 10 addr bm data s2 = None \<Longrightarrow>
 memory_write 10 addr bm data s1 = None"
 apply (simp add: memory_write_def)
 by (metis low_equal_com memory_write_def memory_write_low_equal_none)
 
 lemma mem_context_val_9_unchanged:
 "mem_context_val 9 addr1 (mem s1) =
 mem_context_val 9 addr1
               ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None)))"
 apply (simp add: mem_context_val_def)
 by (simp add: Let_def)
 
 lemma mem_context_val_w32_9_unchanged:
 "mem_context_val_w32 9 addr1 (mem s1) =
 mem_context_val_w32 9 addr1
               ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None)))"
 apply (simp add: mem_context_val_w32_def)
 apply (simp add: Let_def)
 by (metis mem_context_val_9_unchanged)
 
 lemma ptd_lookup_unchanged_4: 
 "ptd_lookup va ptp (mem s1) 4 = 
 ptd_lookup va ptp ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 
                             11 := (mem s1 11)(addr := None))) 4"
 by auto
 
 lemma ptd_lookup_unchanged_3: 
 "ptd_lookup va ptp (mem s1) 3 = 
 ptd_lookup va ptp ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 
                             11 := (mem s1 11)(addr := None))) 3"
 proof (cases "mem_context_val_w32 9 ((ucast (ptp OR ((ucast ((ucast (va >> 12))::word6))::word32)))::word36) (mem s1) = None")
   case True
   then have "mem_context_val_w32 9 ((ucast (ptp OR ((ucast ((ucast (va >> 12))::word6))::word32)))::word36) (mem s1) = None \<and>
     mem_context_val_w32 9 ((ucast (ptp OR ((ucast ((ucast (va >> 12))::word6))::word32)))::word36)
            ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) = None"
     using mem_context_val_w32_9_unchanged by metis    
   then show ?thesis 
   by auto  
 next
   case False
   then have "mem_context_val_w32 9 
     ((ucast (ptp OR ((ucast ((ucast (va >> 12))::word6))::word32)))::word36) (mem s1) \<noteq> None \<and>
     mem_context_val_w32 9 ((ucast (ptp OR ((ucast ((ucast (va >> 12))::word6))::word32)))::word36) 
       ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) \<noteq> None"
     using mem_context_val_w32_9_unchanged by metis
   then have "mem_context_val_w32 9 
     ((ucast (ptp OR ((ucast ((ucast (va >> 12))::word6))::word32)))::word36) (mem s1) \<noteq> None \<and>
     mem_context_val_w32 9 ((ucast (ptp OR ((ucast ((ucast (va >> 12))::word6))::word32)))::word36) 
       ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) \<noteq> None \<and>
     (\<forall>y. (mem_context_val_w32 9 
     ((ucast (ptp OR ((ucast ((ucast (va >> 12))::word6))::word32)))::word36) (mem s1) = Some y) \<longrightarrow> 
     (mem_context_val_w32 9 
     ((ucast (ptp OR ((ucast ((ucast (va >> 12))::word6))::word32)))::word36) 
       ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None)))= Some y))"
     using mem_context_val_w32_9_unchanged by metis
   then show ?thesis 
   apply auto
   by (simp add: Let_def)
 qed
 
 lemma ptd_lookup_unchanged_2: 
 "ptd_lookup va ptp (mem s1) 2 = 
 ptd_lookup va ptp ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 
                             11 := (mem s1 11)(addr := None))) 2"
 proof (cases "mem_context_val_w32 9 ((ucast (ptp OR ((ucast ((ucast (va >> 18))::word6))::word32)))::word36) (mem s1) = None")
   case True
   then have "mem_context_val_w32 9 ((ucast (ptp OR ((ucast ((ucast (va >> 18))::word6))::word32)))::word36) (mem s1) = None \<and>
     mem_context_val_w32 9 ((ucast (ptp OR ((ucast ((ucast (va >> 18))::word6))::word32)))::word36)
            ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) = None"
     using mem_context_val_w32_9_unchanged by metis    
   then show ?thesis 
   by auto  
 next
   case False
   then have "mem_context_val_w32 9 
     ((ucast (ptp OR ((ucast ((ucast (va >> 18))::word6))::word32)))::word36) (mem s1) \<noteq> None \<and>
     mem_context_val_w32 9 ((ucast (ptp OR ((ucast ((ucast (va >> 18))::word6))::word32)))::word36) 
       ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) \<noteq> None"
     using mem_context_val_w32_9_unchanged by metis
   then have "mem_context_val_w32 9 
     ((ucast (ptp OR ((ucast ((ucast (va >> 18))::word6))::word32)))::word36) (mem s1) \<noteq> None \<and>
     mem_context_val_w32 9 ((ucast (ptp OR ((ucast ((ucast (va >> 18))::word6))::word32)))::word36) 
       ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) \<noteq> None \<and>
     (\<forall>y. (mem_context_val_w32 9 
     ((ucast (ptp OR ((ucast ((ucast (va >> 18))::word6))::word32)))::word36) (mem s1) = Some y) \<longrightarrow> 
     (mem_context_val_w32 9 
     ((ucast (ptp OR ((ucast ((ucast (va >> 18))::word6))::word32)))::word36) 
       ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None)))= Some y))"
     using mem_context_val_w32_9_unchanged by metis
   then show ?thesis 
   apply auto
   using ptd_lookup_unchanged_3   
   unfolding Let_def
   by auto
 qed
 
 lemma ptd_lookup_unchanged_1: 
 "ptd_lookup va ptp (mem s1) 1 = 
 ptd_lookup va ptp ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 
                             11 := (mem s1 11)(addr := None))) 1"
 proof (cases "mem_context_val_w32 9 ((ucast (ptp OR ((ucast ((ucast (va >> 24))::word8))::word32)))::word36) (mem s1) = None")
   case True
   then have "mem_context_val_w32 9 ((ucast (ptp OR ((ucast ((ucast (va >> 24))::word8))::word32)))::word36) (mem s1) = None \<and>
     mem_context_val_w32 9 ((ucast (ptp OR ((ucast ((ucast (va >> 24))::word8))::word32)))::word36)
            ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) = None"
     using mem_context_val_w32_9_unchanged by metis    
   then show ?thesis 
   by auto  
 next
   case False
   then have "mem_context_val_w32 9 
     ((ucast (ptp OR ((ucast ((ucast (va >> 24))::word8))::word32)))::word36) (mem s1) \<noteq> None \<and>
     mem_context_val_w32 9 ((ucast (ptp OR ((ucast ((ucast (va >> 24))::word8))::word32)))::word36) 
       ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) \<noteq> None"
     using mem_context_val_w32_9_unchanged by metis
   then have "mem_context_val_w32 9 
     ((ucast (ptp OR ((ucast ((ucast (va >> 24))::word8))::word32)))::word36) (mem s1) \<noteq> None \<and>
     mem_context_val_w32 9 ((ucast (ptp OR ((ucast ((ucast (va >> 24))::word8))::word32)))::word36) 
       ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) \<noteq> None \<and>
     (\<forall>y. (mem_context_val_w32 9 
     ((ucast (ptp OR ((ucast ((ucast (va >> 24))::word8))::word32)))::word36) (mem s1) = Some y) \<longrightarrow> 
     (mem_context_val_w32 9 
     ((ucast (ptp OR ((ucast ((ucast (va >> 24))::word8))::word32)))::word36) 
       ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None)))= Some y))"
     using mem_context_val_w32_9_unchanged by metis
   then show ?thesis 
   apply auto
   using ptd_lookup_unchanged_2   
   unfolding Let_def
   proof -
     fix y :: word32
     have "(y AND 3 \<noteq> 0 \<or> y AND 3 = 0 \<or> (y AND 3 \<noteq> 1 \<or> ptd_lookup va (y AND 4294967292) (mem s1) (Suc 0 + 1) = None) \<and> (y AND 3 = 1 \<or> y AND 3 \<noteq> 2 \<or> None = Some ((ucast (ucast (y >> 8)::word24) << 12) OR (ucast (ucast va::word12)::word36), ucast y::word8))) \<and> (y AND 3 = 0 \<or> (y AND 3 \<noteq> 1 \<or> (y AND 3 \<noteq> 0 \<or> ptd_lookup va (y AND 4294967292) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) (Suc 0 + 1) = None) \<and> (y AND 3 = 0 \<or> (y AND 3 \<noteq> 1 \<or> ptd_lookup va (y AND 4294967292) (mem s1) (Suc 0 + 1) = ptd_lookup va (y AND 4294967292) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) (Suc 0 + 1)) \<and> (y AND 3 = 1 \<or> (y AND 3 \<noteq> 2 \<or> ptd_lookup va (y AND 4294967292) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) (Suc 0 + 1) = Some ((ucast (ucast (y >> 8)::word24) << 12) OR ucast (ucast va::word12), ucast y)) \<and> (y AND 3 = 2 \<or> ptd_lookup va (y AND 4294967292) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) (Suc 0 + 1) = None)))) \<and> (y AND 3 = 1 \<or> (y AND 3 \<noteq> 2 \<or> (y AND 3 \<noteq> 0 \<or> None = Some ((ucast (ucast (y >> 8)::word24) << 12) OR (ucast (ucast va::word12)::word36), ucast y::word8)) \<and> (y AND 3 = 0 \<or> (y AND 3 \<noteq> 1 \<or> ptd_lookup va (y AND 4294967292) (mem s1) (Suc 0 + 1) = Some ((ucast (ucast (y >> 8)::word24) << 12) OR ucast (ucast va::word12), ucast y)) \<and> (y AND 3 = 1 \<or> y AND 3 = 2 \<or> None = Some ((ucast (ucast (y >> 8)::word24) << 12) OR (ucast (ucast va::word12)::word36), ucast y::word8)))) \<and> (y AND 3 = 2 \<or> y AND 3 = 0 \<or> (y AND 3 \<noteq> 1 \<or> ptd_lookup va (y AND 4294967292) (mem s1) (Suc 0 + 1) = None) \<and> (y AND 3 = 1 \<or> y AND 3 \<noteq> 2 \<or> None = Some ((ucast (ucast (y >> 8)::word24) << 12) OR (ucast (ucast va::word12)::word36), ucast y::word8))))) \<or> (\<forall>w. mem s1 w = ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) w)"
       by (metis (no_types) One_nat_def Suc_1 Suc_eq_plus1 ptd_lookup_unchanged_2)
     then show "(if y AND 3 = 0 then None else if y AND 3 = 1 then ptd_lookup va (y AND 4294967292) (mem s1) (Suc 0 + 1) else if y AND 3 = 2 then Some ((ucast (ucast (y >> 8)::word24) << 12) OR ucast (ucast va::word12), ucast y) else None) = (if y AND 3 = 0 then None else if y AND 3 = 1 then ptd_lookup va (y AND 4294967292) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) (Suc 0 + 1) else if y AND 3 = 2 then Some ((ucast (ucast (y >> 8)::word24) << 12) OR ucast (ucast va::word12), ucast y) else None)"
     proof -
       have f1: "2 = Suc 0 + 1"
         by (metis One_nat_def Suc_1 Suc_eq_plus1)
       { assume "y AND 3 = 1"
         moreover
         { assume "y AND 3 = 1 \<and> (if y AND 3 = 0 then None else if y AND 3 = 1 then ptd_lookup va (y AND 4294967292) (mem s1) (Suc 0 + 1) else if y AND 3 = 2 then Some ((ucast (ucast (y >> 8)::word24) << 12) OR ucast (ucast va::word12), ucast y) else None) \<noteq> (if y AND 3 = 0 then None else if y AND 3 = 1 then ptd_lookup va (y AND 4294967292) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) (Suc 0 + 1) else if y AND 3 = 2 then Some ((ucast (ucast (y >> 8)::word24) << 12) OR ucast (ucast va::word12), ucast y) else None)"
           have "y AND 3 = 1 \<and> (if y AND 3 = 0 then None else if y AND 3 = 1 then ptd_lookup va (y AND 4294967292) (mem s1) (Suc 0 + 1) else if y AND 3 = 2 then Some ((ucast (ucast (y >> 8)::word24) << 12) OR ucast (ucast va::word12), ucast y) else None) \<noteq> ptd_lookup va (y AND 4294967292) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) (Suc 0 + 1) \<or> (if y AND 3 = 0 then None else if y AND 3 = 1 then ptd_lookup va (y AND 4294967292) (mem s1) (Suc 0 + 1) else if y AND 3 = 2 then Some ((ucast (ucast (y >> 8)::word24) << 12) OR ucast (ucast va::word12), ucast y) else None) = (if y AND 3 = 0 then None else if y AND 3 = 1 then ptd_lookup va (y AND 4294967292) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) (Suc 0 + 1) else if y AND 3 = 2 then Some ((ucast (ucast (y >> 8)::word24) << 12) OR ucast (ucast va::word12), ucast y) else None)"
             by presburger
           moreover
           { assume "y AND 3 = 1 \<and> (if y AND 3 = 0 then None else if y AND 3 = 1 then ptd_lookup va (y AND 4294967292) (mem s1) (Suc 0 + 1) else if y AND 3 = 2 then Some ((ucast (ucast (y >> 8)::word24) << 12) OR ucast (ucast va::word12), ucast y) else None) \<noteq> ptd_lookup va (y AND 4294967292) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) (Suc 0 + 1)"
             then have "y AND 3 = 1 \<and> (if y AND 3 = 0 then None else if y AND 3 = 1 then ptd_lookup va (y AND 4294967292) (mem s1) (Suc 0 + 1) else if y AND 3 = 2 then Some ((ucast (ucast (y >> 8)::word24) << 12) OR ucast (ucast va::word12), ucast y) else None) \<noteq> ptd_lookup va (y AND 4294967292) (mem s1) 2"
               by (metis One_nat_def Suc_1 Suc_eq_plus1 ptd_lookup_unchanged_2)
             then have ?thesis
               using f1 by auto }
           ultimately have ?thesis
             by blast }
         ultimately have ?thesis
           by blast }
       then show ?thesis
         by presburger
     qed  
   qed
 qed
 
 lemma virt_to_phys_unchanged_sub1: 
 assumes a1: "(let context_table_entry = (v1 >> 11 << 11) OR (v2 AND 511 << 2)
   in Let (mem_context_val_w32 (word_of_int 9) (ucast context_table_entry) (mem s1))
     (case_option None (\<lambda>lvl1_page_table. ptd_lookup va lvl1_page_table (mem s1) 1))) =
  (let context_table_entry = (v1 >> 11 << 11) OR (v2 AND 511 << 2)
   in Let (mem_context_val_w32 (word_of_int 9) (ucast context_table_entry) (mem s2))
     (case_option None (\<lambda>lvl1_page_table. ptd_lookup va lvl1_page_table (mem s2) 1)))"
 shows "(let context_table_entry = (v1 >> 11 << 11) OR (v2 AND 511 << 2)
   in Let (mem_context_val_w32 (word_of_int 9) (ucast context_table_entry)
     ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))))
      (case_option None (\<lambda>lvl1_page_table. ptd_lookup va lvl1_page_table
       ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) 1))) =
  (let context_table_entry = (v1 >> 11 << 11) OR (v2 AND 511 << 2)
   in Let (mem_context_val_w32 (word_of_int 9) (ucast context_table_entry)
     ((mem s2)(10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))))
      (case_option None (\<lambda>lvl1_page_table. ptd_lookup va lvl1_page_table
       ((mem s2)(10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))) 1)))"
 proof -
   from a1 have 
    "(case mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) (mem s1) of
      None \<Rightarrow> None | Some lvl1_page_table \<Rightarrow> ptd_lookup va lvl1_page_table (mem s1) 1) =
     (case mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) (mem s2) of
      None \<Rightarrow> None | Some lvl1_page_table \<Rightarrow> ptd_lookup va lvl1_page_table (mem s2) 1)" 
      unfolding Let_def by auto
   then have "(case mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) 
      ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) of
      None \<Rightarrow> None | Some lvl1_page_table \<Rightarrow> ptd_lookup va lvl1_page_table (mem s1) 1) =
     (case mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) 
      ((mem s2)(10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))) of
      None \<Rightarrow> None | Some lvl1_page_table \<Rightarrow> ptd_lookup va lvl1_page_table (mem s2) 1)"
     using mem_context_val_w32_9_unchanged
     by (metis word_numeral_alt) 
  then have "(case mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) 
      ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) of
      None \<Rightarrow> None | Some lvl1_page_table \<Rightarrow> ptd_lookup va lvl1_page_table 
       ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) 1) =
     (case mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) 
      ((mem s2)(10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))) of
      None \<Rightarrow> None | Some lvl1_page_table \<Rightarrow> ptd_lookup va lvl1_page_table 
      ((mem s2)(10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))) 1)"   
     using ptd_lookup_unchanged_1
     proof -
       obtain ww :: "word32 option \<Rightarrow> word32" where
         f1: "\<forall>z. (z = None \<or> z = Some (ww z)) \<and> (z \<noteq> None \<or> (\<forall>w. z \<noteq> Some w))"
         by moura
       then have f2: "(mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) = None \<or> mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) = Some (ww (mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None)))))) \<and> (mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) \<noteq> None \<or> (\<forall>w. mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) \<noteq> Some w))"
         by blast
       then have f3: "(case mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) of None \<Rightarrow> None | Some w \<Rightarrow> ptd_lookup va w ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) 1) \<noteq> None \<longrightarrow> (case mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) of None \<Rightarrow> None | Some w \<Rightarrow> ptd_lookup va w ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) 1) = (case mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) of None \<Rightarrow> None | Some w \<Rightarrow> ptd_lookup va w (mem s1) 1)"
         by (metis (no_types) \<open>\<And>val va s1 ptp addr. ptd_lookup va ptp (mem s1) 1 = ptd_lookup va ptp ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) 1\<close> option.case(2) option.simps(4))
       have f4: "mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s2) (10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))) = Some (ww (mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s2) (10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))))) \<and> mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) = Some (ww (mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))))) \<longrightarrow> (case mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) of None \<Rightarrow> None | Some w \<Rightarrow> ptd_lookup va w ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) 1) = (case Some (ww (mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s2) (10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))))) of None \<Rightarrow> None | Some w \<Rightarrow> ptd_lookup va w ((mem s2) (10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))) 1)"
         by (metis (no_types) \<open>(case mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) of None \<Rightarrow> None | Some lvl1_page_table \<Rightarrow> ptd_lookup va lvl1_page_table (mem s1) 1) = (case mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s2) (10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))) of None \<Rightarrow> None | Some lvl1_page_table \<Rightarrow> ptd_lookup va lvl1_page_table (mem s2) 1)\<close> \<open>\<And>val va s1 ptp addr. ptd_lookup va ptp (mem s1) 1 = ptd_lookup va ptp ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) 1\<close> option.case(2))
       have f5: "(mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s2) (10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))) = None \<or> mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s2) (10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))) = Some (ww (mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s2) (10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None)))))) \<and> (mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s2) (10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))) \<noteq> None \<or> (\<forall>w. mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s2) (10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))) \<noteq> Some w))"
         using f1 by blast
       { assume "(case mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) of None \<Rightarrow> None | Some w \<Rightarrow> ptd_lookup va w ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) 1) \<noteq> (case mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s2) (10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))) of None \<Rightarrow> None | Some w \<Rightarrow> ptd_lookup va w ((mem s2) (10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))) 1)"
         { assume "(case mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s2) (10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))) of None \<Rightarrow> None | Some w \<Rightarrow> ptd_lookup va w (mem s2) 1) \<noteq> None \<and> (case mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s2) (10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))) of None \<Rightarrow> None | Some w \<Rightarrow> ptd_lookup va w (mem s2) 1) \<noteq> None"
           then have "(case mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s2) (10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))) of None \<Rightarrow> None | Some w \<Rightarrow> ptd_lookup va w (mem s2) 1) \<noteq> None \<and> mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) \<noteq> None"
             by (metis (no_types) \<open>(case mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) of None \<Rightarrow> None | Some lvl1_page_table \<Rightarrow> ptd_lookup va lvl1_page_table (mem s1) 1) = (case mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s2) (10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))) of None \<Rightarrow> None | Some lvl1_page_table \<Rightarrow> ptd_lookup va lvl1_page_table (mem s2) 1)\<close> option.simps(4))
           then have ?thesis
             using f5 f4 f2 by force }
         then have ?thesis
           using f5 f3 by (metis (no_types) \<open>(case mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) of None \<Rightarrow> None | Some lvl1_page_table \<Rightarrow> ptd_lookup va lvl1_page_table (mem s1) 1) = (case mem_context_val_w32 (word_of_int 9) (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s2) (10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))) of None \<Rightarrow> None | Some lvl1_page_table \<Rightarrow> ptd_lookup va lvl1_page_table (mem s2) 1)\<close> \<open>\<And>val va s1 ptp addr. ptd_lookup va ptp (mem s1) 1 = ptd_lookup va ptp ((mem s1) (10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) 1\<close> option.case(2) option.simps(4)) }
       then show ?thesis
         by blast
     qed
  then show ?thesis 
   unfolding Let_def by auto 
 qed
 
 lemma virt_to_phys_unchanged: 
 assumes a1: "(\<forall>va. virt_to_phys va (mmu s2) (mem s1) = virt_to_phys va (mmu s2) (mem s2))"
 shows "(\<forall>va. virt_to_phys va (mmu s2) ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 
                                          11 := (mem s1 11)(addr := None))) =
              virt_to_phys va (mmu s2) ((mem s2)(10 := mem s2 10(addr \<mapsto> val), 
                                          11 := (mem s2 11)(addr := None))))"
 proof (cases "registers (mmu s2) CR AND 1 \<noteq> 0")
   case True
   then have f1: "registers (mmu s2) CR AND 1 \<noteq> 0" by auto
   then show ?thesis 
   proof (cases "mmu_reg_val (mmu s2) 256 = None")
     case True
     then show ?thesis 
     by (simp add: virt_to_phys_def)
   next
     case False
     then have f2: "mmu_reg_val (mmu s2) 256 \<noteq> None" by auto
     then show ?thesis 
     proof (cases "mmu_reg_val (mmu s2) 512 = None")
       case True
       then show ?thesis using f1 f2
       apply (simp add: virt_to_phys_def)
       by auto
     next
       case False
       then show ?thesis using f1 f2 a1
       apply (simp add: virt_to_phys_def)
       apply clarify
       using virt_to_phys_unchanged_sub1 by fastforce
     qed
   qed
 next
   case False
   then show ?thesis 
   by (simp add: virt_to_phys_def)
 qed
 
 lemma virt_to_phys_unchanged2_sub1: 
 "(case mem_context_val_w32 (word_of_int 9) 
   (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) (mem s2) of
   None \<Rightarrow> None | Some lvl1_page_table \<Rightarrow> ptd_lookup va lvl1_page_table (mem s2) 1) =
 (case mem_context_val_w32 (word_of_int 9) 
   (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s2)
     (10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))) of
   None \<Rightarrow> None | Some lvl1_page_table \<Rightarrow> ptd_lookup va lvl1_page_table ((mem s2)
     (10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))) 1)"
 proof (cases "mem_context_val_w32 9 (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) (mem s2) = None")
   case True
   then have "mem_context_val_w32 9 (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) (mem s2) = None \<and>
     mem_context_val_w32 9 (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s2)
     (10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))) = None"
     using mem_context_val_w32_9_unchanged by metis
   then show ?thesis 
   by auto
 next
   case False
   then have "mem_context_val_w32 9 (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) (mem s2) \<noteq> None \<and> 
     (\<forall>y. mem_context_val_w32 9 (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) (mem s2) = Some y \<longrightarrow>
          mem_context_val_w32 9 (ucast ((v1 >> 11 << 11) OR (v2 AND 511 << 2))) ((mem s2)
          (10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))) = Some y)"
     using mem_context_val_w32_9_unchanged by metis 
   then show ?thesis
   using ptd_lookup_unchanged_1 by fastforce 
 qed
 
 lemma virt_to_phys_unchanged2: 
 "virt_to_phys va (mmu s2) (mem s2) =
 virt_to_phys va (mmu s2) ((mem s2)(10 := mem s2 10(addr \<mapsto> val), 
                                          11 := (mem s2 11)(addr := None)))"
 proof (cases "registers (mmu s2) CR AND 1 \<noteq> 0")
   case True
   then have f1: "registers (mmu s2) CR AND 1 \<noteq> 0" by auto
   then show ?thesis 
   proof (cases "mmu_reg_val (mmu s2) 256 = None")
     case True
     then show ?thesis 
     by (simp add: virt_to_phys_def)
   next
     case False
     then have f2: "mmu_reg_val (mmu s2) 256 \<noteq> None" by auto
     then show ?thesis 
     proof (cases "mmu_reg_val (mmu s2) 512 = None")
       case True
       then show ?thesis using f1 f2
       apply (simp add: virt_to_phys_def)
       by auto
     next
       case False
       then show ?thesis 
       using f1 f2
       apply (simp add: virt_to_phys_def)
       apply clarify
       unfolding Let_def
       using virt_to_phys_unchanged2_sub1
       by auto      
     qed
   qed
 next
   case False
   then show ?thesis 
   by (simp add: virt_to_phys_def)
 qed
 
 lemma virt_to_phys_unchanged_low_equal: 
 assumes a1: "low_equal s1 s2"
 shows "(\<forall>va. virt_to_phys va (mmu s2) ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 
                                          11 := (mem s1 11)(addr := None))) =
              virt_to_phys va (mmu s2) ((mem s2)(10 := mem s2 10(addr \<mapsto> val), 
                                          11 := (mem s2 11)(addr := None))))"
 using a1 apply (simp add: low_equal_def)
 using virt_to_phys_unchanged
 by metis 
 
 lemma mmu_low_equal: "low_equal s1 s2 \<Longrightarrow> mmu s1 = mmu s2"
 by (simp add: low_equal_def)
 
 lemma mem_val_alt_8_unchanged0: 
 assumes a1: "mem_equal s1 s2 pa"
 shows "mem_val_alt 8 (pa AND 68719476732) (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
   11 := (mem s1 11)(addr := None))\<rparr>) = 
   mem_val_alt 8 (pa AND 68719476732) (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
   11 := (mem s2 11)(addr := None))\<rparr>)"
 apply (simp add: mem_val_alt_def)
 apply (simp add: Let_def)
 using a1 apply (simp add: mem_equal_def)
 by (metis option.distinct(1))
 
 lemma mem_val_alt_8_unchanged1: 
 assumes a1: "mem_equal s1 s2 pa"
 shows "mem_val_alt 8 ((pa AND 68719476732) + 1) (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
   11 := (mem s1 11)(addr := None))\<rparr>) = 
   mem_val_alt 8 ((pa AND 68719476732) + 1) (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
   11 := (mem s2 11)(addr := None))\<rparr>)"
 apply (simp add: mem_val_alt_def)
 apply (simp add: Let_def)
 using a1 apply (simp add: mem_equal_def)
 by (metis option.distinct(1))
 
 lemma mem_val_alt_8_unchanged2: 
 assumes a1: "mem_equal s1 s2 pa"
 shows "mem_val_alt 8 ((pa AND 68719476732) + 2) (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
   11 := (mem s1 11)(addr := None))\<rparr>) = 
   mem_val_alt 8 ((pa AND 68719476732) + 2) (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
   11 := (mem s2 11)(addr := None))\<rparr>)"
 apply (simp add: mem_val_alt_def)
 apply (simp add: Let_def)
 using a1 apply (simp add: mem_equal_def)
 by (metis option.distinct(1))
 
 lemma mem_val_alt_8_unchanged3: 
 assumes a1: "mem_equal s1 s2 pa"
 shows "mem_val_alt 8 ((pa AND 68719476732) + 3) (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
   11 := (mem s1 11)(addr := None))\<rparr>) = 
   mem_val_alt 8 ((pa AND 68719476732) + 3) (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
   11 := (mem s2 11)(addr := None))\<rparr>)"
 apply (simp add: mem_val_alt_def)
 apply (simp add: Let_def)
 using a1 apply (simp add: mem_equal_def)
 by (metis option.distinct(1))
 
 lemma mem_val_alt_8_unchanged: 
 assumes a1: "mem_equal s1 s2 pa"
 shows "mem_val_alt 8 (pa AND 68719476732) (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
   11 := (mem s1 11)(addr := None))\<rparr>) = 
   mem_val_alt 8 (pa AND 68719476732) (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
   11 := (mem s2 11)(addr := None))\<rparr>) \<and>
   mem_val_alt 8 ((pa AND 68719476732) + 1) (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
   11 := (mem s1 11)(addr := None))\<rparr>) = 
   mem_val_alt 8 ((pa AND 68719476732) + 1) (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
   11 := (mem s2 11)(addr := None))\<rparr>) \<and>
   mem_val_alt 8 ((pa AND 68719476732) + 2) (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
   11 := (mem s1 11)(addr := None))\<rparr>) = 
   mem_val_alt 8 ((pa AND 68719476732) + 2) (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
   11 := (mem s2 11)(addr := None))\<rparr>) \<and>
   mem_val_alt 8 ((pa AND 68719476732) + 3) (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
   11 := (mem s1 11)(addr := None))\<rparr>) = 
   mem_val_alt 8 ((pa AND 68719476732) + 3) (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
   11 := (mem s2 11)(addr := None))\<rparr>)"
 using a1 mem_val_alt_8_unchanged0 mem_val_alt_8_unchanged1
 mem_val_alt_8_unchanged2 mem_val_alt_8_unchanged3
 by blast
 
 lemma mem_val_w32_8_unchanged: 
 assumes a1: "mem_equal s1 s2 a"
 shows "mem_val_w32 8 a (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
   11 := (mem s1 11)(addr := None))\<rparr>) =
 mem_val_w32 8 a (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
   11 := (mem s2 11)(addr := None))\<rparr>)"
 apply (simp add: mem_val_w32_def)
 apply (simp add: Let_def)
 using mem_val_alt_8_unchanged a1 apply auto
         apply fastforce
        apply fastforce
       apply fastforce
      apply fastforce
     apply fastforce
    apply fastforce
   apply fastforce
  apply fastforce
 by fastforce
 
 lemma load_word_mem_8_unchanged: 
 assumes a1: "low_equal s1 s2 \<and> 
 load_word_mem s1 addra 8 = load_word_mem s2 addra 8"
 shows "load_word_mem (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
                                          11 := (mem s1 11)(addr := None))\<rparr>) addra 8 =
        load_word_mem (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
                                          11 := (mem s2 11)(addr := None))\<rparr>) addra 8"
 proof (cases "virt_to_phys addra (mmu s1) ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 
           11 := (mem s1 11)(addr := None))) = None")
   case True
   then have "virt_to_phys addra (mmu s1) ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 
           11 := (mem s1 11)(addr := None))) = None \<and>
              virt_to_phys addra (mmu s2) ((mem s2)(10 := mem s2 10(addr \<mapsto> val), 
           11 := (mem s2 11)(addr := None))) = None"
     using a1 apply (auto simp add: mmu_low_equal)
     using a1 virt_to_phys_unchanged_low_equal by metis
   then show ?thesis
   by (simp add: load_word_mem_def)
 next
   case False
   then have "\<exists>p. virt_to_phys addra (mmu s1) ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 
           11 := (mem s1 11)(addr := None))) = Some p \<and>
              virt_to_phys addra (mmu s2) ((mem s2)(10 := mem s2 10(addr \<mapsto> val), 
           11 := (mem s2 11)(addr := None))) = Some p"
     using a1 apply (auto simp add: mmu_low_equal)
     using a1 virt_to_phys_unchanged_low_equal by metis
   then have "\<exists>p. virt_to_phys addra (mmu s1) ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 
           11 := (mem s1 11)(addr := None))) = Some p \<and>
             virt_to_phys addra (mmu s2) ((mem s2)(10 := mem s2 10(addr \<mapsto> val), 
           11 := (mem s2 11)(addr := None))) = Some p \<and> 
             virt_to_phys addra (mmu s1) (mem s1) = Some p \<and>
             virt_to_phys addra (mmu s2) (mem s2) = Some p"
     using virt_to_phys_unchanged2 by metis
   then show ?thesis using a1  
   apply (simp add: load_word_mem_def)
   apply auto
   apply (simp add: low_equal_def)
   apply (simp add: user_accessible_def)
   using mem_val_w32_8_unchanged a1 user_accessible_8
   by (metis snd_conv)
 qed
 
 lemma load_word_mem_select_8: 
 assumes a1: "fst (case load_word_mem s1 addra 8 of None \<Rightarrow> (None, s1)
   | Some w \<Rightarrow> (Some w, add_instr_cache s1 addra w 15)) =
 fst (case load_word_mem s2 addra 8 of None \<Rightarrow> (None, s2)
   | Some w \<Rightarrow> (Some w, add_instr_cache s2 addra w 15))"
 shows "load_word_mem s1 addra 8 = load_word_mem s2 addra 8"
 using a1
 by (metis (mono_tags, lifting) fst_conv not_None_eq option.simps(4) option.simps(5))
 
 lemma memory_read_8_unchanged: 
 assumes a1: "low_equal s1 s2 \<and>
 fst (memory_read 8 addra s1) = fst (memory_read 8 addra s2)"
 shows "fst (memory_read 8 addra
                    (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
                                        11 := (mem s1 11)(addr := None))\<rparr>)) =
          fst (memory_read 8 addra
                    (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
                                        11 := (mem s2 11)(addr := None))\<rparr>))"
 proof (cases "sys_reg s1 CCR AND 1 = 0")
   case True
   then have "sys_reg s1 CCR AND 1 = 0 \<and> sys_reg s2 CCR AND 1 = 0"
     using a1 sys_reg_low_equal by fastforce
   then show ?thesis using a1
   apply (simp add: memory_read_def)
   using load_word_mem_8_unchanged by blast
 next
   case False
   then have f1: "sys_reg s1 CCR AND 1 \<noteq> 0 \<and> sys_reg s2 CCR AND 1 \<noteq> 0"
     using a1 sys_reg_low_equal by fastforce
   then show ?thesis using a1
   proof (cases "load_word_mem (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
       11 := (mem s1 11)(addr := None))\<rparr>) addra 8 = None")
     case True
     then have "load_word_mem (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
       11 := (mem s1 11)(addr := None))\<rparr>) addra 8 = None \<and> 
       load_word_mem (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
       11 := (mem s2 11)(addr := None))\<rparr>) addra 8 = None"
       using a1 f1  
       apply (simp add: memory_read_def)
       apply clarsimp
       using load_word_mem_select_8 load_word_mem_8_unchanged
       by fastforce      
     then show ?thesis
     by (simp add: memory_read_def)
   next
     case False
     then have "\<exists>y. load_word_mem (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
       11 := (mem s1 11)(addr := None))\<rparr>) addra 8 = Some y" by auto
     then have "\<exists>y. load_word_mem (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
       11 := (mem s1 11)(addr := None))\<rparr>) addra 8 = Some y \<and> 
                    load_word_mem (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
       11 := (mem s2 11)(addr := None))\<rparr>) addra 8 = Some y"
       using a1 f1
       apply (simp add: memory_read_def)
       apply clarsimp
       using load_word_mem_select_8 load_word_mem_8_unchanged by fastforce
     then show ?thesis using a1 f1
     apply (simp add: memory_read_def)
     by auto
   qed
 qed
 
 lemma mem_val_alt_mod: 
 assumes a1: "addr1 \<noteq> addr2"
 shows "mem_val_alt 10 addr1 s = 
 mem_val_alt 10 addr1 (s\<lparr>mem := (mem s)(10 := mem s 10(addr2 \<mapsto> val), 
   11 := (mem s 11)(addr2 := None))\<rparr>)"
 using a1 apply (simp add: mem_val_alt_def)
 by (simp add: Let_def)
 
 lemma mem_val_alt_mod2: 
 "mem_val_alt 10 addr (s\<lparr>mem := (mem s)(10 := mem s 10(addr \<mapsto> val), 
   11 := (mem s 11)(addr := None))\<rparr>) = Some val"
 by (simp add: mem_val_alt_def)
 
 lemma mem_val_alt_10_unchanged0: 
 assumes a1: "mem_equal s1 s2 pa"
 shows "mem_val_alt 10 (pa AND 68719476732) (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
   11 := (mem s1 11)(addr := None))\<rparr>) = 
   mem_val_alt 10 (pa AND 68719476732) (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
   11 := (mem s2 11)(addr := None))\<rparr>)"
 apply (simp add: mem_val_alt_def)
 apply (simp add: Let_def)
 using a1 apply (simp add: mem_equal_def)
 by (metis option.distinct(1))
 
 lemma mem_val_alt_10_unchanged1: 
 assumes a1: "mem_equal s1 s2 pa"
 shows "mem_val_alt 10 ((pa AND 68719476732) + 1) (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
   11 := (mem s1 11)(addr := None))\<rparr>) = 
   mem_val_alt 10 ((pa AND 68719476732) + 1) (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
   11 := (mem s2 11)(addr := None))\<rparr>)"
 apply (simp add: mem_val_alt_def)
 apply (simp add: Let_def)
 using a1 apply (simp add: mem_equal_def)
 by (metis option.distinct(1))
 
 lemma mem_val_alt_10_unchanged2: 
 assumes a1: "mem_equal s1 s2 pa"
 shows "mem_val_alt 10 ((pa AND 68719476732) + 2) (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
   11 := (mem s1 11)(addr := None))\<rparr>) = 
   mem_val_alt 10 ((pa AND 68719476732) + 2) (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
   11 := (mem s2 11)(addr := None))\<rparr>)"
 apply (simp add: mem_val_alt_def)
 apply (simp add: Let_def)
 using a1 apply (simp add: mem_equal_def)
 by (metis option.distinct(1))
 
 lemma mem_val_alt_10_unchanged3: 
 assumes a1: "mem_equal s1 s2 pa"
 shows "mem_val_alt 10 ((pa AND 68719476732) + 3) (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
   11 := (mem s1 11)(addr := None))\<rparr>) = 
   mem_val_alt 10 ((pa AND 68719476732) + 3) (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
   11 := (mem s2 11)(addr := None))\<rparr>)"
 apply (simp add: mem_val_alt_def)
 apply (simp add: Let_def)
 using a1 apply (simp add: mem_equal_def)
 by (metis option.distinct(1))
 
 lemma mem_val_alt_10_unchanged: 
 assumes a1: "mem_equal s1 s2 pa"
 shows "mem_val_alt 10 (pa AND 68719476732) (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
   11 := (mem s1 11)(addr := None))\<rparr>) = 
   mem_val_alt 10 (pa AND 68719476732) (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
   11 := (mem s2 11)(addr := None))\<rparr>) \<and>
   mem_val_alt 10 ((pa AND 68719476732) + 1) (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
   11 := (mem s1 11)(addr := None))\<rparr>) = 
   mem_val_alt 10 ((pa AND 68719476732) + 1) (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
   11 := (mem s2 11)(addr := None))\<rparr>) \<and>
   mem_val_alt 10 ((pa AND 68719476732) + 2) (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
   11 := (mem s1 11)(addr := None))\<rparr>) = 
   mem_val_alt 10 ((pa AND 68719476732) + 2) (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
   11 := (mem s2 11)(addr := None))\<rparr>) \<and>
   mem_val_alt 10 ((pa AND 68719476732) + 3) (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
   11 := (mem s1 11)(addr := None))\<rparr>) = 
   mem_val_alt 10 ((pa AND 68719476732) + 3) (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
   11 := (mem s2 11)(addr := None))\<rparr>)"
 using a1 mem_val_alt_10_unchanged0 mem_val_alt_10_unchanged1
 mem_val_alt_10_unchanged2 mem_val_alt_10_unchanged3
 by blast
 
 lemma mem_val_w32_10_unchanged: 
 assumes a1: "mem_equal s1 s2 a"
 shows "mem_val_w32 10 a (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
   11 := (mem s1 11)(addr := None))\<rparr>) =
 mem_val_w32 10 a (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
   11 := (mem s2 11)(addr := None))\<rparr>)"
 apply (simp add: mem_val_w32_def)
 apply (simp add: Let_def)
 using mem_val_alt_10_unchanged a1 apply auto
         apply fastforce
        apply fastforce
       apply fastforce
      apply fastforce
     apply fastforce
    apply fastforce
   apply fastforce
  apply fastforce
 by fastforce
 
 lemma is_accessible: "low_equal s1 s2 \<Longrightarrow>
 virt_to_phys addra (mmu s1) (mem s1) = Some (a, b) \<Longrightarrow>
 virt_to_phys addra (mmu s2) (mem s2) = Some (a, b) \<Longrightarrow>
 mmu_readable (get_acc_flag b) 10 \<Longrightarrow>
 mem_equal s1 s2 a"
 apply (simp add: low_equal_def)
 apply (simp add: user_accessible_def)
 by fastforce
 
 lemma load_word_mem_10_unchanged: 
 assumes a1: "low_equal s1 s2 \<and> 
 load_word_mem s1 addra 10 = load_word_mem s2 addra 10"
 shows "load_word_mem (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
                                          11 := (mem s1 11)(addr := None))\<rparr>) addra 10 =
        load_word_mem (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
                                          11 := (mem s2 11)(addr := None))\<rparr>) addra 10"
 proof (cases "virt_to_phys addra (mmu s1) ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 
           11 := (mem s1 11)(addr := None))) = None")
   case True
   then have "virt_to_phys addra (mmu s1) ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 
           11 := (mem s1 11)(addr := None))) = None \<and>
              virt_to_phys addra (mmu s2) ((mem s2)(10 := mem s2 10(addr \<mapsto> val), 
           11 := (mem s2 11)(addr := None))) = None"
     using a1 apply (auto simp add: mmu_low_equal)
     using a1 virt_to_phys_unchanged_low_equal by metis
   then show ?thesis
   by (simp add: load_word_mem_def)
 next
   case False
   then have "\<exists>p. virt_to_phys addra (mmu s1) ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 
           11 := (mem s1 11)(addr := None))) = Some p \<and>
              virt_to_phys addra (mmu s2) ((mem s2)(10 := mem s2 10(addr \<mapsto> val), 
           11 := (mem s2 11)(addr := None))) = Some p"
     using a1 apply (auto simp add: mmu_low_equal)
     using a1 virt_to_phys_unchanged_low_equal by metis
   then have "\<exists>p. virt_to_phys addra (mmu s1) ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 
           11 := (mem s1 11)(addr := None))) = Some p \<and>
             virt_to_phys addra (mmu s2) ((mem s2)(10 := mem s2 10(addr \<mapsto> val), 
           11 := (mem s2 11)(addr := None))) = Some p \<and> 
             virt_to_phys addra (mmu s1) (mem s1) = Some p \<and>
             virt_to_phys addra (mmu s2) (mem s2) = Some p"
     using virt_to_phys_unchanged2 by metis
   then show ?thesis using a1  
   apply (simp add: load_word_mem_def)
   apply auto
   apply (simp add: low_equal_def)
   apply (simp add: user_accessible_def)
   using mem_val_w32_10_unchanged a1 by metis
 qed
 
 lemma load_word_mem_select_10: 
 assumes a1: "fst (case load_word_mem s1 addra 10 of None \<Rightarrow> (None, s1)
   | Some w \<Rightarrow> (Some w, add_data_cache s1 addra w 15)) =
 fst (case load_word_mem s2 addra 10 of None \<Rightarrow> (None, s2)
   | Some w \<Rightarrow> (Some w, add_data_cache s2 addra w 15))"
 shows "load_word_mem s1 addra 10 = load_word_mem s2 addra 10"
 using a1
 by (metis (mono_tags, lifting) fst_conv not_None_eq option.simps(4) option.simps(5))
 
 lemma memory_read_10_unchanged: 
 assumes a1: "low_equal s1 s2 \<and>
 fst (memory_read 10 addra s1) = fst (memory_read 10 addra s2)"
 shows "fst (memory_read 10 addra
                    (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
                                        11 := (mem s1 11)(addr := None))\<rparr>)) =
          fst (memory_read 10 addra
                    (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
                                        11 := (mem s2 11)(addr := None))\<rparr>))"
 proof (cases "sys_reg s1 CCR AND 1 = 0")
   case True
   then have "sys_reg s1 CCR AND 1 = 0 \<and> sys_reg s2 CCR AND 1 = 0"
     using a1 sys_reg_low_equal by fastforce
   then show ?thesis using a1
   apply (simp add: memory_read_def)
   using load_word_mem_10_unchanged by blast
 next
   case False
   then have f1: "sys_reg s1 CCR AND 1 \<noteq> 0 \<and> sys_reg s2 CCR AND 1 \<noteq> 0"
     using a1 sys_reg_low_equal by fastforce
   then show ?thesis using a1
   proof (cases "load_word_mem (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
       11 := (mem s1 11)(addr := None))\<rparr>) addra 10 = None")
     case True
     then have "load_word_mem (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
       11 := (mem s1 11)(addr := None))\<rparr>) addra 10 = None \<and> 
       load_word_mem (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
       11 := (mem s2 11)(addr := None))\<rparr>) addra 10 = None"
       using a1 f1  
       apply (simp add: memory_read_def)
       apply clarsimp
       using load_word_mem_select_10 load_word_mem_10_unchanged by fastforce
     then show ?thesis
     by (simp add: memory_read_def)
   next
     case False
     then have "\<exists>y. load_word_mem (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
       11 := (mem s1 11)(addr := None))\<rparr>) addra 10 = Some y" by auto
     then have "\<exists>y. load_word_mem (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
       11 := (mem s1 11)(addr := None))\<rparr>) addra 10 = Some y \<and> 
                    load_word_mem (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
       11 := (mem s2 11)(addr := None))\<rparr>) addra 10 = Some y"
       using a1 f1
       apply (simp add: memory_read_def)
       apply clarsimp
       using load_word_mem_select_10 load_word_mem_10_unchanged by fastforce
     then show ?thesis using a1 f1
     apply (simp add: memory_read_def)
     by auto
   qed
 qed
 
 lemma state_mem_mod_1011_low_equal_sub1: 
 assumes a1: "(\<forall>va. virt_to_phys va (mmu s2) (mem s1) =
             virt_to_phys va (mmu s2) (mem s2)) \<and>
   (\<forall>pa. (\<exists>va b. virt_to_phys va (mmu s2) (mem s2) = Some (pa, b) \<and>
   mmu_readable (get_acc_flag b) 10) \<longrightarrow>
   mem_equal s1 s2 pa) \<and>
   mmu s1 = mmu s2 \<and>
   virt_to_phys va (mmu s2)
   ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) =
   Some (pa, b) \<and>
   mmu_readable (get_acc_flag b) 10"
 shows "mem_equal s1 s2 pa"
 proof -
   have "virt_to_phys va (mmu s1)
   ((mem s1)(10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))) =
   Some (pa, b)"
     using a1 by auto
   then have "virt_to_phys va (mmu s1) (mem s1) = Some (pa, b)"
     using virt_to_phys_unchanged2 by metis
   then have "virt_to_phys va (mmu s2) (mem s2) = Some (pa, b)"
     using a1 by auto
   then show ?thesis using a1 by auto
 qed
 
 lemma mem_equal_unchanged: 
 assumes a1: "mem_equal s1 s2 pa"
 shows "mem_equal (s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 
   11 := (mem s1 11)(addr := None))\<rparr>)
  (s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 
   11 := (mem s2 11)(addr := None))\<rparr>)
  pa"
 using a1 apply (simp add: mem_equal_def)
 by auto
 
 lemma state_mem_mod_1011_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>
 t1 = s1\<lparr>mem := (mem s1)(10 := mem s1 10(addr \<mapsto> val), 11 := (mem s1 11)(addr := None))\<rparr> \<and>
 t2 = s2\<lparr>mem := (mem s2)(10 := mem s2 10(addr \<mapsto> val), 11 := (mem s2 11)(addr := None))\<rparr>"
 shows "low_equal t1 t2"
 using a1
 apply (simp add: low_equal_def)
 apply (simp add: user_accessible_def)
 apply auto
    apply (simp add: assms virt_to_phys_unchanged_low_equal)
   using state_mem_mod_1011_low_equal_sub1 mem_equal_unchanged
   apply metis
  apply (metis virt_to_phys_unchanged2)
 using state_mem_mod_1011_low_equal_sub1 mem_equal_unchanged
 by metis
 
 lemma mem_mod_low_equal:
 assumes a1: "low_equal s1 s2 \<and>
 t1 = (mem_mod 10 addr val s1) \<and>
 t2 = (mem_mod 10 addr val s2)"
 shows "low_equal t1 t2"
 using a1
 apply (simp add: mem_mod_def)
 by (auto intro: state_mem_mod_1011_low_equal)
 
 lemma mem_mod_w32_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>
 t1 = mem_mod_w32 10 a bm data s1 \<and>
 t2 = mem_mod_w32 10 a bm data s2"
 shows "low_equal t1 t2"
 using a1
 apply (simp add: mem_mod_w32_def)
 apply (simp add: Let_def)
 by (meson mem_mod_low_equal)
 
 lemma store_word_mem_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>
 Some t1 = store_word_mem s1 addr data bm 10 \<and>
 Some t2 = store_word_mem s2 addr data bm 10" 
 shows "low_equal t1 t2" using a1
 apply (simp add: store_word_mem_def)
 apply (auto simp add: virt_to_phys_low_equal)
 apply (case_tac "virt_to_phys addr (mmu s2) (mem s2) = None")
  apply auto
 apply (case_tac "mmu_writable (get_acc_flag b) 10")
  apply auto
 using mem_mod_w32_low_equal by blast
 
 lemma memory_write_asi_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>
 Some t1 = memory_write_asi 10 addr bm data s1 \<and>
 Some t2 = memory_write_asi 10 addr bm data s2"
 shows "low_equal t1 t2"
 using a1 apply (simp add: memory_write_asi_def)
 by (meson add_data_cache_low_equal store_word_mem_low_equal)
 
 lemma store_barrier_pending_mod_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>
 t1 = store_barrier_pending_mod False s1 \<and>
 t2 = store_barrier_pending_mod False s2"
 shows "low_equal t1 t2"
 using a1 apply (simp add: store_barrier_pending_mod_def)
 apply clarsimp
 using a1 apply (auto simp add: state_var_low_equal)
 by (auto intro: state_var2_low_equal)
 
 lemma memory_write_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>
 Some t1 = memory_write 10 addr bm data s1 \<and>
 Some t2 = memory_write 10 addr bm data s2"
 shows "low_equal t1 t2"
 apply (case_tac "memory_write_asi 10 addr bm data s1 = None")
  using a1 apply (simp add: memory_write_def)
 apply (case_tac "memory_write_asi 10 addr bm data s2 = None")
  apply (meson assms low_equal_com memory_write_asi_low_equal_none)
 using a1 apply (simp add: memory_write_def)
 apply auto
 by (metis memory_write_asi_low_equal store_barrier_pending_mod_low_equal)
 
 lemma memory_write_low_equal2: 
 assumes a1: "low_equal s1 s2 \<and>
 Some t1 = memory_write 10 addr bm data s1"
 shows "\<exists>t2. Some t2 = memory_write 10 addr bm data s2"
 using a1
 apply (simp add: memory_write_def)
 apply auto
 by (metis (full_types) memory_write_def memory_write_low_equal_none2 not_None_eq) 
 
 lemma store_sub2_low_equal_sub1:
 assumes a1: "low_equal s1 s2 \<and>
 memory_write 10 addr (st_byte_mask instr addr)
   (st_data0 instr curr_win rd addr s2) s1 = Some y \<and>
 memory_write 10 addr (st_byte_mask instr addr)
   (st_data0 instr curr_win rd addr s2) s2 = Some ya"
 shows "low_equal (y\<lparr>traps := insert data_access_exception (traps y)\<rparr>)
         (ya\<lparr>traps := insert data_access_exception (traps ya)\<rparr>)"
 proof -
   from a1 have f1: "low_equal y ya" using memory_write_low_equal by metis
   then have "traps y = traps ya" by (simp add: low_equal_def)
   then show ?thesis using f1 mod_trap_low_equal by fastforce
 qed
 
 lemma store_sub2_low_equal_sub2:
 assumes a1: "low_equal s1 s2 \<and>
 memory_write 10 addr (st_byte_mask instr addr)
   (st_data0 instr curr_win rd addr s2) s1 = Some y \<and>
 memory_write 10 addr (st_byte_mask instr addr)
   (st_data0 instr curr_win rd addr s2) s2 = Some ya \<and>
 memory_write 10 (addr + 4) 15 (user_reg_val curr_win (rd OR 1) y) y = None \<and>
 memory_write 10 (addr + 4) 15 (user_reg_val curr_win (rd OR 1) ya) ya = Some yb"
 shows "False"
 proof -
   from a1 have f1: "low_equal y ya" using memory_write_low_equal by metis
   then have "(user_reg_val curr_win (rd OR 1) y) = 
     (user_reg_val curr_win (rd OR 1) ya)" 
     by (simp add: low_equal_def user_reg_val_def)
   then show ?thesis using a1
   using f1 memory_write_low_equal_none by fastforce  
 qed
 
 lemma store_sub2_low_equal_sub3:
 assumes a1: "low_equal s1 s2 \<and>
 memory_write 10 addr (st_byte_mask instr addr)
   (st_data0 instr curr_win rd addr s2) s1 = Some y \<and>
 memory_write 10 addr (st_byte_mask instr addr)
   (st_data0 instr curr_win rd addr s2) s2 = Some ya \<and>
 memory_write 10 (addr + 4) 15 (user_reg_val curr_win (rd OR 1) y) y = Some yb \<and>
 memory_write 10 (addr + 4) 15 (user_reg_val curr_win (rd OR 1) ya) ya = None"
 shows "False"
 proof -
   from a1 have f1: "low_equal y ya" using memory_write_low_equal by metis
   then have "(user_reg_val curr_win (rd OR 1) y) = 
     (user_reg_val curr_win (rd OR 1) ya)" 
     by (simp add: low_equal_def user_reg_val_def)
   then show ?thesis using a1
   using f1 memory_write_low_equal_none2 by fastforce  
 qed
 
 lemma store_sub2_low_equal_sub4:
 assumes a1: "low_equal s1 s2 \<and>
 memory_write 10 addr (st_byte_mask instr addr)
   (st_data0 instr curr_win rd addr s2) s1 = Some y \<and>
 memory_write 10 addr (st_byte_mask instr addr)
   (st_data0 instr curr_win rd addr s2) s2 = Some ya \<and>
 memory_write 10 (addr + 4) 15 (user_reg_val curr_win (rd OR 1) y) y = Some yb \<and>
 memory_write 10 (addr + 4) 15 (user_reg_val curr_win (rd OR 1) ya) ya = Some yc" 
 shows "low_equal yb yc"
 proof -
   from a1 have f1: "low_equal y ya" using memory_write_low_equal by metis
   then have "(user_reg_val curr_win (rd OR 1) y) = 
     (user_reg_val curr_win (rd OR 1) ya)" 
     by (simp add: low_equal_def user_reg_val_def)
   then show ?thesis using a1 f1
   by (metis memory_write_low_equal)  
 qed
 
 lemma store_sub2_low_equal:
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (store_sub2 instr curr_win rd 10 addr s1)) \<and>
 t2 = snd (fst (store_sub2 instr curr_win rd 10 addr s2))"
 shows "low_equal t1 t2"
 proof (cases "memory_write 10 addr (st_byte_mask instr addr)
         (st_data0 instr curr_win rd addr s1) s1 = None")
   case True
   then have "memory_write 10 addr (st_byte_mask instr addr)
         (st_data0 instr curr_win rd addr s1) s1 = None \<and>
         memory_write 10 addr (st_byte_mask instr addr)
         (st_data0 instr curr_win rd addr s2) s2 = None"
     using a1 by (metis memory_write_low_equal_none st_data0_low_equal) 
   then show ?thesis using a1
   apply (simp add: store_sub2_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   apply (simp add: case_prod_unfold return_def)
   apply (simp add: raise_trap_def add_trap_set_def)
   apply (simp add: simpler_modify_def)
   using mod_trap_low_equal traps_low_equal by fastforce  
 next
   case False
   then have f1: "memory_write 10 addr (st_byte_mask instr addr) 
     (st_data0 instr curr_win rd addr s1) s1 \<noteq> None \<and>
     memory_write 10 addr (st_byte_mask instr addr) 
     (st_data0 instr curr_win rd addr s2) s2 \<noteq> None"
     using a1 by (metis memory_write_low_equal_none2 st_data0_low_equal)     
   then show ?thesis 
   proof (cases "(fst instr) \<in> {load_store_type STD,load_store_type STDA}")
     case True
     then show ?thesis using a1 f1
     apply (simp add: store_sub2_def)
     apply (simp add: simpler_gets_def bind_def h1_def h2_def)
     apply (simp add: simpler_modify_def bind_def h1_def h2_def Let_def)
     apply (simp add: return_def)
     apply (simp add: bind_def case_prod_unfold)
     apply (simp add: simpler_modify_def)
     apply clarsimp
     apply (simp add: case_prod_unfold bind_def h1_def h2_def Let_def simpler_modify_def)
     apply (simp add: simpler_gets_def)
     apply auto
            apply (simp add: raise_trap_def add_trap_set_def)
            apply (simp add: simpler_modify_def)
            apply (simp add: st_data0_low_equal)    
            apply (simp add: store_sub2_low_equal_sub1)
           apply (simp add: st_data0_low_equal)
           using store_sub2_low_equal_sub2 apply blast
          apply (simp add: st_data0_low_equal)
          using store_sub2_low_equal_sub3 apply blast
         apply (simp add: st_data0_low_equal)
         using store_sub2_low_equal_sub4 apply blast
        apply (simp add: st_data0_low_equal)
        apply (simp add: raise_trap_def add_trap_set_def)
        apply (simp add: simpler_modify_def)
        using store_sub2_low_equal_sub1 apply blast
       apply (simp add: st_data0_low_equal)
       using store_sub2_low_equal_sub2 apply blast
      apply (simp add: st_data0_low_equal)
      using store_sub2_low_equal_sub3 apply blast
     apply (simp add: st_data0_low_equal)
     using store_sub2_low_equal_sub4 by blast
   next
     case False
     then show ?thesis using a1 f1
     apply (simp add: store_sub2_def)
     apply (simp add: simpler_gets_def bind_def h1_def h2_def)
     apply (simp add: simpler_modify_def bind_def h1_def h2_def Let_def)
     apply (simp add: return_def)
     apply (simp add: bind_def case_prod_unfold)
     apply clarsimp
     apply (simp add: simpler_modify_def)
     apply (simp add: st_data0_low_equal)
     using memory_write_low_equal by metis
   qed
 qed
 
 lemma store_sub1_low_equal:
 assumes a1: "low_equal s1 s2 \<and>
 (fst instr = load_store_type STB \<or>
 fst instr = load_store_type STH \<or>
 fst instr = load_store_type ST \<or> 
 fst instr = load_store_type STD) \<and>
 t1 = snd (fst (store_sub1 instr rd 0 s1)) \<and>
 t2 = snd (fst (store_sub1 instr rd 0 s2))"
 shows "low_equal t1 t2"
 proof (cases "(fst instr = load_store_type STH \<or> fst instr = load_store_type STHA) \<and>
               ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s1)))))::word1) \<noteq> 0")
   case True
   then have "((fst instr = load_store_type STH \<or> fst instr = load_store_type STHA) \<and>
               ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s1)))))::word1) \<noteq> 0) \<and> 
              ((fst instr = load_store_type STH \<or> fst instr = load_store_type STHA) \<and>
               ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s2)))))::word1) \<noteq> 0)"
     by (metis (mono_tags, lifting) assms get_addr_low_equal) 
   then show ?thesis using a1
   apply (simp add: store_sub1_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   apply (simp add: case_prod_unfold)
   apply (simp add: raise_trap_def add_trap_set_def)
   apply (simp add: simpler_modify_def)
   apply clarsimp
   apply (simp add: get_curr_win3_low_equal)
   by (auto intro: get_curr_win2_low_equal mod_trap_low_equal)
 next
   case False
   then have f1: "\<not> ((fst instr = load_store_type STH \<or> fst instr = load_store_type STHA) \<and>
       ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s1)))))::word1) \<noteq> 0) \<and>
       \<not> ((fst instr = load_store_type STH \<or> fst instr = load_store_type STHA) \<and>
       ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s2)))))::word1) \<noteq> 0)"
     by (metis (mono_tags, lifting) assms get_addr_low_equal) 
   then show ?thesis 
   proof (cases "(fst instr \<in> {load_store_type ST,load_store_type STA}) \<and>
               ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s1)))))::word2) \<noteq> 0")
     case True
     then have "(fst instr \<in> {load_store_type ST,load_store_type STA}) \<and>
               ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s1)))))::word2) \<noteq> 0 \<and>
               (fst instr \<in> {load_store_type ST,load_store_type STA}) \<and>
               ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s2)))))::word2) \<noteq> 0"
       by (metis (mono_tags, lifting) assms get_addr_low_equal) 
     then show ?thesis using a1 f1
     apply (simp add: store_sub1_def)
     apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
     apply (simp add: case_prod_unfold) 
     apply (simp add: raise_trap_def add_trap_set_def)
     apply (simp add: simpler_modify_def)
     apply clarsimp
     apply (simp add: get_curr_win3_low_equal)
     by (auto intro: get_curr_win2_low_equal mod_trap_low_equal)
   next
     case False
     then have "\<not>((fst instr \<in> {load_store_type ST,load_store_type STA}) \<and>
               ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s1)))))::word2) \<noteq> 0) \<and>
               \<not>((fst instr \<in> {load_store_type ST,load_store_type STA}) \<and>
               ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s2)))))::word2) \<noteq> 0)"
       by (metis (mono_tags, lifting) assms get_addr_low_equal) 
     then have f2: "\<not>((fst instr = load_store_type ST \<or> fst instr = load_store_type STA) \<and>
               ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s1)))))::word2) \<noteq> 0) \<and>
               \<not>((fst instr = load_store_type ST \<or> fst instr = load_store_type STA) \<and>
               ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s2)))))::word2) \<noteq> 0)"
       by auto
     then show ?thesis 
     proof (cases "(fst instr \<in> {load_store_type STD,load_store_type STDA}) \<and>
               ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s1)))))::word3) \<noteq> 0")
       case True
       then have "(fst instr \<in> {load_store_type STD,load_store_type STDA}) \<and>
               ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s1)))))::word3) \<noteq> 0 \<and>
               (fst instr \<in> {load_store_type STD,load_store_type STDA}) \<and>
               ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s2)))))::word3) \<noteq> 0"
         by (metis (mono_tags, lifting) assms get_addr_low_equal) 
       then show ?thesis using a1 
       apply (simp add: store_sub1_def)
       apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
       apply auto
       apply (simp add: case_prod_unfold) 
       apply (simp add: raise_trap_def add_trap_set_def)
       apply (simp add: simpler_modify_def)
       apply (simp add: get_curr_win3_low_equal)
       by (auto intro: get_curr_win2_low_equal mod_trap_low_equal)         
     next
       case False
       then have "\<not> (fst instr \<in> {load_store_type STD, load_store_type STDA} \<and>
         ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s1)))))::word3) \<noteq> 0) \<and>
         \<not> (fst instr \<in> {load_store_type STD, load_store_type STDA} \<and>
         ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s2)))))::word3) \<noteq> 0)"
         by (metis (mono_tags, lifting) assms get_addr_low_equal)
       then have f3: "\<not> ((fst instr = load_store_type STD \<or> fst instr = load_store_type STDA) \<and>
         ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s1)))))::word3) \<noteq> 0) \<and>
         \<not> ((fst instr = load_store_type STD \<or> fst instr = load_store_type STDA) \<and>
         ((ucast (get_addr (snd instr) (snd (fst (get_curr_win () s2)))))::word3) \<noteq> 0)"
         by auto
       show ?thesis using a1
       apply (simp add: store_sub1_def)
       apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
       apply (unfold case_prod_beta)
       apply (simp add: f1 f2 f3)
       apply (simp_all add: st_asi_def)
       using a1 apply clarsimp
       apply (simp add: get_curr_win_low_equal get_addr2_low_equal)
       by (metis store_sub2_low_equal get_curr_win2_low_equal)      
     qed
   qed
 qed
 
 lemma store_instr_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>
 (fst instr = load_store_type STB \<or>
 fst instr = load_store_type STH \<or>
 fst instr = load_store_type ST \<or> 
 fst instr = load_store_type STA \<or> 
 fst instr = load_store_type STD) \<and>
 ((ucast (get_S (cpu_reg_val PSR s1)))::word1) = 0 \<and>
 ((ucast (get_S (cpu_reg_val PSR s2)))::word1) = 0 \<and>
 t1 = snd (fst (store_instr instr s1)) \<and> t2 = snd (fst (store_instr instr s2))"
 shows "low_equal t1 t2"
 proof -
   have "get_S (cpu_reg_val PSR s1) = 0 \<and> get_S (cpu_reg_val PSR s2) = 0"
     using a1 by (simp add: ucast_id) 
   then show ?thesis using a1
   apply (simp add: store_instr_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def)
   apply (simp add: Let_def)
   apply clarsimp
   apply (simp add: raise_trap_def add_trap_set_def)
   apply (simp add: simpler_modify_def)
   apply (simp add: traps_low_equal)
   by (auto intro: mod_trap_low_equal store_sub1_low_equal)
 qed
 
 lemma sethi_low_equal: "low_equal s1 s2 \<and>
 t1 = snd (fst (sethi_instr instr s1)) \<and> t2 = snd (fst (sethi_instr instr s2)) \<Longrightarrow>
 low_equal t1 t2"
 apply (simp add: sethi_instr_def)
 apply (simp add: Let_def)
 apply (case_tac "get_operand_w5 (snd instr ! Suc 0) \<noteq> 0")
  apply auto
  apply (simp add: bind_def h1_def h2_def Let_def)
  apply (simp add: case_prod_unfold)
  apply (simp add: get_curr_win_low_equal)
  using get_curr_win2_low_equal write_reg_low_equal
  apply metis
 by (simp add: return_def)
 
 lemma nop_low_equal: "low_equal s1 s2 \<and>
 t1 = snd (fst (nop_instr instr s1)) \<and> t2 = snd (fst (nop_instr instr s2)) \<Longrightarrow>
 low_equal t1 t2"
 apply (simp add: nop_instr_def)
 by (simp add: return_def)
 
 lemma logical_instr_sub1_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (logical_instr_sub1 instr_name result s1)) \<and> 
 t2 = snd (fst (logical_instr_sub1 instr_name result s2))"
 shows "low_equal t1 t2"
 proof (cases "instr_name = logic_type ANDcc \<or>
               instr_name = logic_type ANDNcc \<or>
               instr_name = logic_type ORcc \<or>
               instr_name = logic_type ORNcc \<or>
               instr_name = logic_type XORcc \<or> instr_name = logic_type XNORcc")
   case True
   then show ?thesis using a1
   apply (simp add: logical_instr_sub1_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   apply (simp add: logical_new_psr_val_def)    
   using write_cpu_low_equal cpu_reg_val_low_equal
   by fastforce  
 next
   case False
   then show ?thesis using a1
   apply (simp add: logical_instr_sub1_def)
   by (simp add: return_def)
 qed
 
 lemma logical_instr_low_equal: "low_equal s1 s2 \<and>
 t1 = snd (fst (logical_instr instr s1)) \<and> t2 = snd (fst (logical_instr instr s2)) \<Longrightarrow>
 low_equal t1 t2"
 apply (simp add: logical_instr_def)
 apply (simp add: Let_def simpler_gets_def bind_def h1_def h2_def)
 apply (simp add: case_prod_unfold)
 apply auto
  apply (simp_all add: get_curr_win_low_equal)
  apply (simp_all add: get_operand2_low_equal)
  using logical_instr_sub1_low_equal get_operand2_low_equal
  get_curr_win2_low_equal write_reg_low_equal user_reg_val_low_equal
  proof -
   assume a1: "low_equal s1 s2"
   assume "t2 = snd (fst (logical_instr_sub1 (fst instr) (logical_result (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) (get_operand2 (snd instr) s2)) (snd (fst (write_reg (logical_result (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) (get_operand2 (snd instr) s2)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s2))))))))"
   assume "t1 = snd (fst (logical_instr_sub1 (fst instr) (logical_result (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) (get_operand2 (snd instr) s2)) (snd (fst (write_reg (logical_result (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) (get_operand2 (snd instr) s2)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s1))))))))"
   have "\<And>w wa. user_reg_val w wa (snd (fst (get_curr_win () s2))) = user_reg_val w wa (snd (fst (get_curr_win () s1)))"
     using a1 by (metis (no_types) get_curr_win2_low_equal user_reg_val_low_equal)
   then show "low_equal (snd (fst (logical_instr_sub1 (fst instr) (logical_result (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) (get_operand2 (snd instr) s2)) (snd (fst (write_reg (logical_result (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) (get_operand2 (snd instr) s2)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s1))))))))) (snd (fst (logical_instr_sub1 (fst instr) (logical_result (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) (get_operand2 (snd instr) s2)) (snd (fst (write_reg (logical_result (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) (get_operand2 (snd instr) s2)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s2)))))))))"
     using a1 by (metis (no_types) get_curr_win2_low_equal logical_instr_sub1_low_equal write_reg_low_equal)
  next
   assume a2: "low_equal s1 s2"
   assume "t1 = snd (fst (logical_instr_sub1 (fst instr)
                     (logical_result (fst instr)
                       (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                         (snd (fst (get_curr_win () s1))))
                       (get_operand2 (snd instr) s2))
                     (snd (fst (write_reg
                                 (user_reg_val (fst (fst (get_curr_win () s2))) 0
                                   (snd (fst (get_curr_win () s1))))
                                 (fst (fst (get_curr_win () s2))) 0
                                 (snd (fst (get_curr_win () s1))))))))"
   assume "t2 = snd (fst (logical_instr_sub1 (fst instr)
                     (logical_result (fst instr)
                       (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                         (snd (fst (get_curr_win () s2))))
                       (get_operand2 (snd instr) s2))
                     (snd (fst (write_reg
                                 (user_reg_val (fst (fst (get_curr_win () s2))) 0
                                   (snd (fst (get_curr_win () s2))))
                                 (fst (fst (get_curr_win () s2))) 0
                                 (snd (fst (get_curr_win () s2))))))))"
   have "\<And>w wa. user_reg_val w wa (snd (fst (get_curr_win () s2))) = user_reg_val w wa (snd (fst (get_curr_win () s1)))"
     using a2 by (metis (no_types) get_curr_win2_low_equal user_reg_val_low_equal)
   then show "low_equal
      (snd (fst (logical_instr_sub1 (fst instr)
                  (logical_result (fst instr)
                    (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                      (snd (fst (get_curr_win () s1))))
                    (get_operand2 (snd instr) s2))
                  (snd (fst (write_reg
                              (user_reg_val (fst (fst (get_curr_win () s2))) 0
                                (snd (fst (get_curr_win () s1))))
                              (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s1)))))))))
      (snd (fst (logical_instr_sub1 (fst instr)
                  (logical_result (fst instr)
                    (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                      (snd (fst (get_curr_win () s2))))
                    (get_operand2 (snd instr) s2))
                  (snd (fst (write_reg
                              (user_reg_val (fst (fst (get_curr_win () s2))) 0
                                (snd (fst (get_curr_win () s2))))
                              (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2)))))))))"
   proof -
     have "low_equal (snd (fst (logical_instr_sub1 (fst instr) (logical_result (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) (get_operand2 (snd instr) s2)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s1))))))))) (snd (fst (logical_instr_sub1 (fst instr) (logical_result (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) (get_operand2 (snd instr) s2)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2)))))))))"
       by (meson a2 get_curr_win2_low_equal logical_instr_sub1_low_equal write_reg_low_equal)
     then show ?thesis
       using \<open>\<And>wa w. user_reg_val w wa (snd (fst (get_curr_win () s2))) = user_reg_val w wa (snd (fst (get_curr_win () s1)))\<close> by presburger
   qed   
  qed
 
 lemma shift_instr_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (shift_instr instr s1)) \<and> t2 = snd (fst (shift_instr instr s2))"
 shows "low_equal t1 t2"
 proof (cases "(fst instr = shift_type SLL) \<and> (get_operand_w5 ((snd instr)!3) \<noteq> 0)")
   case True
   then show ?thesis using a1
   apply (simp add: shift_instr_def)
   apply (simp add: Let_def)
   apply (simp add: simpler_gets_def)
   apply (simp add: bind_def h1_def h2_def Let_def case_prod_unfold)
   apply auto
     apply (simp_all add: get_curr_win_low_equal)
     proof -
       assume a1: "low_equal s1 s2"
       assume "t2 = snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) << unat (ucast (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 2)) (snd (fst (get_curr_win () s2))))::word5)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s2)))))"
       assume "t1 = snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) << unat (ucast (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 2)) (snd (fst (get_curr_win () s1))))::word5)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s1)))))"
       have "\<And>w wa wb. low_equal (snd (fst (write_reg w wa wb s1))) (snd (fst (write_reg w wa wb s2)))"
         using a1 by (metis write_reg_low_equal)
       then show "low_equal (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) << unat (ucast (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 2)) (snd (fst (get_curr_win () s1))))::word5)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s1)))))) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) << unat (ucast (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 2)) (snd (fst (get_curr_win () s2))))::word5)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s2))))))"
         using a1 by (simp add: get_curr_win_def simpler_gets_def user_reg_val_low_equal)
     next
       assume a2: "low_equal s1 s2"
       assume "t1 = snd (fst (write_reg
                     (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                       (snd (fst (get_curr_win () s1))) <<
                      unat (get_operand_w5 (snd instr ! 2)))
                     (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
                     (snd (fst (get_curr_win () s1)))))"
       assume "t2 = snd (fst (write_reg
                     (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                       (snd (fst (get_curr_win () s2))) <<
                      unat (get_operand_w5 (snd instr ! 2)))
                     (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
                     (snd (fst (get_curr_win () s2)))))"
       have "\<And>w wa wb. low_equal (snd (fst (write_reg w wa wb s1))) (snd (fst (write_reg w wa wb s2)))"
         using a2 by (metis write_reg_low_equal)
       then show "low_equal
                 (snd (fst (write_reg
                  (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                    (snd (fst (get_curr_win () s1))) <<
                   unat (get_operand_w5 (snd instr ! 2)))
                  (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
                  (snd (fst (get_curr_win () s1))))))
                 (snd (fst (write_reg
                  (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                    (snd (fst (get_curr_win () s2))) <<
                   unat (get_operand_w5 (snd instr ! 2)))
                  (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
                  (snd (fst (get_curr_win () s2))))))"
       proof -
         assume a1: "\<And>w wa wb. low_equal (snd (fst (write_reg w wa wb s1))) (snd (fst (write_reg w wa wb s2)))"
         have "\<And>u s. fst (get_curr_win u s) = (ucast (get_CWP (cpu_reg_val PSR s))::'a word, s)"
           by (simp add: get_curr_win_def simpler_gets_def)
         then show ?thesis
           using a1 assms user_reg_val_low_equal by fastforce
       qed      
     qed
 next
   case False
   then have f1: "\<not>((fst instr = shift_type SLL) \<and> (get_operand_w5 ((snd instr)!3) \<noteq> 0))"
     by auto
   then show ?thesis
   proof (cases "(fst instr = shift_type SRL) \<and> (get_operand_w5 ((snd instr)!3) \<noteq> 0)")
     case True
     then show ?thesis using a1 f1
     apply (simp add: shift_instr_def)
     apply (simp add: Let_def)
     apply (simp add: simpler_gets_def)
     apply (simp add: bind_def h1_def h2_def Let_def case_prod_unfold)
     apply auto
       apply (simp_all add: get_curr_win_low_equal)
       proof -
         assume a1: "low_equal s1 s2"
         assume "t2 = snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) >> unat (ucast (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 2)) (snd (fst (get_curr_win () s2))))::word5)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s2)))))"
         assume "t1 = snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) >> unat (ucast (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 2)) (snd (fst (get_curr_win () s1))))::word5)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s1)))))"
         have "\<And>u s. fst (get_curr_win u s) = (ucast (get_CWP (cpu_reg_val PSR s))::'a word, s)"
           by (simp add: get_curr_win_def simpler_gets_def)
         then show "low_equal (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) >> unat (ucast (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 2)) (snd (fst (get_curr_win () s1))))::word5)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s1)))))) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) >> unat (ucast (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 2)) (snd (fst (get_curr_win () s2))))::word5)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s2))))))"
           using a1 user_reg_val_low_equal write_reg_low_equal by fastforce
       next
         assume a2: "low_equal s1 s2"
         assume "t1 = snd (fst (write_reg
                     (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                       (snd (fst (get_curr_win () s1))) >>
                      unat (get_operand_w5 (snd instr ! 2)))
                     (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
                     (snd (fst (get_curr_win () s1)))))" 
         assume "t2 = snd (fst (write_reg
                     (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                       (snd (fst (get_curr_win () s2))) >>
                      unat (get_operand_w5 (snd instr ! 2)))
                     (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
                     (snd (fst (get_curr_win () s2)))))"
         have "\<And>u s. fst (get_curr_win u s) = (ucast (get_CWP (cpu_reg_val PSR s))::'a word, s)"
           by (simp add: get_curr_win_def simpler_gets_def)
         then show "low_equal
                 (snd (fst (write_reg
                  (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                    (snd (fst (get_curr_win () s1))) >>
                   unat (get_operand_w5 (snd instr ! 2)))
                  (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
                  (snd (fst (get_curr_win () s1))))))
                 (snd (fst (write_reg
                  (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                    (snd (fst (get_curr_win () s2))) >>
                   unat (get_operand_w5 (snd instr ! 2)))
                  (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
                  (snd (fst (get_curr_win () s2))))))"
           using a2 user_reg_val_low_equal write_reg_low_equal by fastforce
       qed  
   next
     case False
     then have f2: "\<not>((fst instr = shift_type SRL) \<and> (get_operand_w5 ((snd instr)!3) \<noteq> 0))"
       by auto
     then show ?thesis 
     proof (cases "(fst instr = shift_type SRA) \<and> (get_operand_w5 ((snd instr)!3) \<noteq> 0)")
       case True
       then show ?thesis using a1 f1 f2
       apply (simp add: shift_instr_def)
       apply (simp add: Let_def)
       apply (simp add: simpler_gets_def)
       apply (simp add: bind_def h1_def h2_def Let_def case_prod_unfold)
       apply auto
        apply (simp_all add: get_curr_win_low_equal)
        proof -
         assume a1: "low_equal s1 s2"
         assume "t1 = snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) >>> unat (ucast (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 2)) (snd (fst (get_curr_win () s1))))::word5)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s1)))))"
         assume "t2 = snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) >>> unat (ucast (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 2)) (snd (fst (get_curr_win () s2))))::word5)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s2)))))"
         have "\<forall>w wa. user_reg_val wa w (snd (fst (get_curr_win () s1))) = user_reg_val wa w (snd (fst (get_curr_win () s2)))"
           using a1 by (meson get_curr_win2_low_equal user_reg_val_low_equal)
         then show "low_equal (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) >>> unat (ucast (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 2)) (snd (fst (get_curr_win () s1))))::word5)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s1)))))) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) >>> unat (ucast (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 2)) (snd (fst (get_curr_win () s2))))::word5)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s2))))))"
           using a1 by (metis (no_types) get_curr_win2_low_equal write_reg_low_equal)
        next
         assume a2: "low_equal s1 s2"
         assume "t1 = snd (fst (write_reg
                     (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                       (snd (fst (get_curr_win () s1))) >>>
                      unat (get_operand_w5 (snd instr ! 2)))
                     (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
                     (snd (fst (get_curr_win () s1)))))"
         assume "t2 = snd (fst (write_reg
                     (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                       (snd (fst (get_curr_win () s2))) >>>
                      unat (get_operand_w5 (snd instr ! 2)))
                     (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
                     (snd (fst (get_curr_win () s2)))))"
         have "\<forall>w wa. user_reg_val wa w (snd (fst (get_curr_win () s1))) = user_reg_val wa w (snd (fst (get_curr_win () s2)))"
           using a2 by (meson get_curr_win2_low_equal user_reg_val_low_equal)
         then show "low_equal
                 (snd (fst (write_reg
                  (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                    (snd (fst (get_curr_win () s1))) >>>
                   unat (get_operand_w5 (snd instr ! 2)))
                  (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
                  (snd (fst (get_curr_win () s1))))))
                 (snd (fst (write_reg
                  (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                    (snd (fst (get_curr_win () s2))) >>>
                   unat (get_operand_w5 (snd instr ! 2)))
                  (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
                  (snd (fst (get_curr_win () s2))))))"
            using a2 get_curr_win2_low_equal write_reg_low_equal by fastforce         
        qed
     next
       case False
       then show ?thesis using a1 f1 f2
       apply (simp add: shift_instr_def)
       apply (simp add: Let_def) 
       apply (simp add: simpler_gets_def)
       apply (simp add: bind_def h1_def h2_def Let_def case_prod_unfold)
       apply (simp add: return_def)
       using get_curr_win2_low_equal by blast
     qed
   qed
 qed
 
 lemma add_instr_sub1_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (add_instr_sub1 instr_name result rs1_val operand2 s1)) \<and>
 t2 = snd (fst (add_instr_sub1 instr_name result rs1_val operand2 s2))"
 shows "low_equal t1 t2"
 proof (cases "instr_name = arith_type ADDcc \<or> instr_name = arith_type ADDXcc")
   case True
   then show ?thesis using a1
   apply (simp add: add_instr_sub1_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   apply (clarsimp simp add: cpu_reg_val_low_equal)
   using write_cpu_low_equal by blast
 next
   case False
   then show ?thesis using a1
   apply (simp add: add_instr_sub1_def)
   by (simp add: return_def)
 qed
 
 lemma add_instr_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (add_instr instr s1)) \<and> t2 = snd (fst (add_instr instr s2))"
 shows "low_equal t1 t2"
 proof -
   have f1: "low_equal s1 s2 \<and>
         t1 = snd (fst (add_instr_sub1 (fst instr)
                     (if fst instr = arith_type ADD \<or> fst instr = arith_type ADDcc
                      then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0))
                            (snd (fst (get_curr_win () s1))) +
                           get_operand2 (snd instr) s1
                      else user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0))
                            (snd (fst (get_curr_win () s1))) +
                           get_operand2 (snd instr) s1 +
                           ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s1))))))
                     (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0))
                       (snd (fst (get_curr_win () s1))))
                     (get_operand2 (snd instr) s1)
                     (snd (fst (write_reg
                                 (if get_operand_w5 (snd instr ! 3) \<noteq> 0
                                  then if fst instr = arith_type ADD \<or> fst instr = arith_type ADDcc
                                       then user_reg_val (fst (fst (get_curr_win () s1)))
                                             (get_operand_w5 (snd instr ! Suc 0))
                                             (snd (fst (get_curr_win () s1))) +
                                            get_operand2 (snd instr) s1
                                       else user_reg_val (fst (fst (get_curr_win () s1)))
                                             (get_operand_w5 (snd instr ! Suc 0))
                                             (snd (fst (get_curr_win () s1))) +
                                            get_operand2 (snd instr) s1 +
                                            ucast (get_icc_C
                                                    (cpu_reg_val PSR (snd (fst (get_curr_win () s1)))))
                                  else user_reg_val (fst (fst (get_curr_win () s1)))
                                        (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s1))))
                                 (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3))
                                 (snd (fst (get_curr_win () s1)))))))) \<and>
     t2 = snd (fst (add_instr_sub1 (fst instr)
                     (if fst instr = arith_type ADD \<or> fst instr = arith_type ADDcc
                      then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                            (snd (fst (get_curr_win () s2))) +
                           get_operand2 (snd instr) s2
                      else user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                            (snd (fst (get_curr_win () s2))) +
                           get_operand2 (snd instr) s2 +
                           ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s2))))))
                     (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                       (snd (fst (get_curr_win () s2))))
                     (get_operand2 (snd instr) s2)
                     (snd (fst (write_reg
                                 (if get_operand_w5 (snd instr ! 3) \<noteq> 0
                                  then if fst instr = arith_type ADD \<or> fst instr = arith_type ADDcc
                                       then user_reg_val (fst (fst (get_curr_win () s2)))
                                             (get_operand_w5 (snd instr ! Suc 0))
                                             (snd (fst (get_curr_win () s2))) +
                                            get_operand2 (snd instr) s2
                                       else user_reg_val (fst (fst (get_curr_win () s2)))
                                             (get_operand_w5 (snd instr ! Suc 0))
                                             (snd (fst (get_curr_win () s2))) +
                                            get_operand2 (snd instr) s2 +
                                            ucast (get_icc_C
                                                    (cpu_reg_val PSR (snd (fst (get_curr_win () s2)))))
                                  else user_reg_val (fst (fst (get_curr_win () s2)))
                                        (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s2))))
                                 (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
                                 (snd (fst (get_curr_win () s2))))))))"
   using a1 apply (simp add: add_instr_def)
   apply (simp add: Let_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   by (simp add: case_prod_unfold)
   then show ?thesis
   proof (cases "get_operand_w5 (snd instr ! 3) \<noteq> 0")
     case True
     then have f2: "get_operand_w5 (snd instr ! 3) \<noteq> 0" by auto
     then show ?thesis
     proof (cases "fst instr = arith_type ADD \<or> fst instr = arith_type ADDcc")
       case True
       then show ?thesis 
       using f1 f2 apply clarsimp
       proof -
         assume a1: "low_equal s1 s2"
         assume "t1 = snd (fst (add_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) + get_operand2 (snd instr) s1) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) (get_operand2 (snd instr) s1) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) + get_operand2 (snd instr) s1) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s1))))))))"
         assume a2: "t2 = snd (fst (add_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) + get_operand2 (snd instr) s2) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) (get_operand2 (snd instr) s2) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) + get_operand2 (snd instr) s2) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s2))))))))"
         have f3: "\<forall>is. get_operand2 is s1 = get_operand2 is s2"
           using a1 by (metis get_operand2_low_equal)
         have f4: "fst (fst (get_curr_win () s1)) = fst (fst (get_curr_win () s2))"
           using a1 by (meson get_curr_win_low_equal)
         have "\<forall>s. snd (fst (add_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) s + get_operand2 (snd instr) s2) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) s) (get_operand2 (snd instr) s2) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) s + get_operand2 (snd instr) s2) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s2)))))))) = t2 \<or> \<not> low_equal s (snd (fst (get_curr_win () s2)))"
           using a2 user_reg_val_low_equal by fastforce
         then show "low_equal (snd (fst (add_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) + get_operand2 (snd instr) s1) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) (get_operand2 (snd instr) s1) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) + get_operand2 (snd instr) s1) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s1))))))))) (snd (fst (add_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) + get_operand2 (snd instr) s2) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) (get_operand2 (snd instr) s2) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) + get_operand2 (snd instr) s2) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s2)))))))))"
           using f4 f3 a2 a1 by (metis (no_types) add_instr_sub1_low_equal get_curr_win2_low_equal write_reg_low_equal)
       qed
     next
       case False
       then show ?thesis
       using f1 f2 apply clarsimp
       proof -
         assume a1: "low_equal s1 s2"
         have f2: "\<forall>s sa sb w wa wb sc. (\<not> low_equal s sa \<or> sb \<noteq> snd (fst (write_reg w (wa::'a word) wb s)) \<or> sc \<noteq> snd (fst (write_reg w wa wb sa))) \<or> low_equal sb sc"
           by (meson write_reg_low_equal)
         have f3: "gets (\<lambda>s. ucast (get_CWP (cpu_reg_val PSR s))::'a word) = get_curr_win ()"
           by (simp add: get_curr_win_def)
         then have "((ucast (get_CWP (cpu_reg_val PSR s1)), s1), False) = (fst (get_curr_win () s1), snd (get_curr_win () s1))"
           by (metis (no_types) prod.collapse simpler_gets_def)
         then have "(ucast (get_CWP (cpu_reg_val PSR s1)), s1) = fst (get_curr_win () s1) \<and> \<not> snd (get_curr_win () s1)"
           by blast
         then have f4: "ucast (get_CWP (cpu_reg_val PSR s1)) = fst (fst (get_curr_win () s1)) \<and> s1 = snd (fst (get_curr_win () s1))"
           by (metis (no_types) prod.collapse prod.simps(1))
         have "((ucast (get_CWP (cpu_reg_val PSR s2)), s2), False) = (fst (get_curr_win () s2), snd (get_curr_win () s2))"
           using f3 by (metis (no_types) prod.collapse simpler_gets_def)
         then have "(ucast (get_CWP (cpu_reg_val PSR s2)), s2) = fst (get_curr_win () s2) \<and> \<not> snd (get_curr_win () s2)"
           by blast
         then have f5: "ucast (get_CWP (cpu_reg_val PSR s2)) = fst (fst (get_curr_win () s2)) \<and> s2 = snd (fst (get_curr_win () s2))"
           by (metis prod.collapse prod.simps(1))
         then have f6: "low_equal (snd (fst (get_curr_win () s1))) (snd (fst (get_curr_win () s2))) = low_equal s1 s2"
           using f4 by presburger
         have f7: "fst (fst (get_curr_win () s1)) = ucast (get_CWP (cpu_reg_val PSR s1))"
           using f4 by presburger
         have f8: "cpu_reg_val PSR s1 = cpu_reg_val PSR s2"
           using a1 by (meson cpu_reg_val_low_equal)
         have f9: "user_reg_val (ucast (get_CWP (cpu_reg_val PSR s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) = user_reg_val (ucast (get_CWP (cpu_reg_val PSR s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))"
           using f6 a1 by (meson user_reg_val_low_equal)
         have f10: "ucast (get_CWP (cpu_reg_val PSR s2)) = fst (fst (get_curr_win () s2))"
           using f5 by meson
         have f11: "\<forall>s sa is. \<not> low_equal (s::'a sparc_state) sa \<or> get_operand2 is s = get_operand2 is sa"
           using get_operand2_low_equal by blast
         then have f12: "user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) + get_operand2 (snd instr) s1 + ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s1))))) = user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) + get_operand2 (snd instr) s2 + ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s2)))))"
           using f9 f8 f5 f4 a1 by auto
         then have "low_equal (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) + get_operand2 (snd instr) s1 + ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s1)))))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s1)))))) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) + get_operand2 (snd instr) s2 + ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s2)))))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s2))))))"
           using f10 f8 f6 f4 f2 a1 by simp
         then show "low_equal (snd (fst (add_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) + get_operand2 (snd instr) s1 + ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s1)))))) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) (get_operand2 (snd instr) s1) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) + get_operand2 (snd instr) s1 + ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s1)))))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s1))))))))) (snd (fst (add_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) + get_operand2 (snd instr) s2 + ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s2)))))) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) (get_operand2 (snd instr) s2) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) + get_operand2 (snd instr) s2 + ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s2)))))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s2)))))))))"
           using f12 f11 f10 f9 f8 f7 a1 add_instr_sub1_low_equal by fastforce
       qed      
     qed
   next
     case False
     then have f3: "\<not> get_operand_w5 (snd instr ! 3) \<noteq> 0" by auto
     then show ?thesis
     proof (cases "fst instr = arith_type ADD \<or> fst instr = arith_type ADDcc")
       case True
       then show ?thesis
       using f1 f3 apply clarsimp
       proof -
         assume a1: "low_equal s1 s2"
         assume "t1 = snd (fst (add_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) + get_operand2 (snd instr) s1) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) (get_operand2 (snd instr) s1) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (get_curr_win () s1))))))))"
         assume "t2 = snd (fst (add_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) + get_operand2 (snd instr) s2) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) (get_operand2 (snd instr) s2) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2))))))))"
         have f2: "\<forall>is. get_operand2 is s1 = get_operand2 is s2"
           using a1 by (meson get_operand2_low_equal)
         have f3: "fst (fst (get_curr_win () s1)) = fst (fst (get_curr_win () s2))"
           using a1 by (meson get_curr_win_low_equal)
         have "\<forall>w wa. user_reg_val wa w (snd (fst (get_curr_win () s1))) = user_reg_val wa w (snd (fst (get_curr_win () s2)))"
           using a1 by (meson get_curr_win2_low_equal user_reg_val_low_equal)
         then show "low_equal (snd (fst (add_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) + get_operand2 (snd instr) s1) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) (get_operand2 (snd instr) s1) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (get_curr_win () s1))))))))) (snd (fst (add_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) + get_operand2 (snd instr) s2) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) (get_operand2 (snd instr) s2) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2)))))))))"
           using f3 f2 a1 by (metis (no_types) add_instr_sub1_low_equal get_curr_win2_low_equal write_reg_low_equal)
       qed      
     next
       case False
       then show ?thesis
       using f1 f3 apply clarsimp
       proof -
         assume a1: "low_equal s1 s2"
         have f2: "gets (\<lambda>s. ucast (get_CWP (cpu_reg_val PSR s))::'a word) = get_curr_win ()"
           by (simp add: get_curr_win_def)
         then have "((ucast (get_CWP (cpu_reg_val PSR s1)), s1), False) = (fst (get_curr_win () s1), snd (get_curr_win () s1))"
           by (metis (no_types) prod.collapse simpler_gets_def)
         then have "(ucast (get_CWP (cpu_reg_val PSR s1)), s1) = fst (get_curr_win () s1) \<and> \<not> snd (get_curr_win () s1)"
           by fastforce
         then have f3: "ucast (get_CWP (cpu_reg_val PSR s1)) = fst (fst (get_curr_win () s1)) \<and> s1 = snd (fst (get_curr_win () s1))"
           by (metis prod.collapse prod.simps(1))
         have "((ucast (get_CWP (cpu_reg_val PSR s2)), s2), False) = (fst (get_curr_win () s2), snd (get_curr_win () s2))"
           using f2 by (metis (no_types) prod.collapse simpler_gets_def)
         then have "(ucast (get_CWP (cpu_reg_val PSR s2)), s2) = fst (get_curr_win () s2) \<and> \<not> snd (get_curr_win () s2)"
           by fastforce
         then have f4: "ucast (get_CWP (cpu_reg_val PSR s2)) = fst (fst (get_curr_win () s2)) \<and> s2 = snd (fst (get_curr_win () s2))"
           by (metis (no_types) prod.collapse prod.simps(1))
         then have f5: "low_equal (snd (fst (get_curr_win () s1))) (snd (fst (get_curr_win () s2))) = low_equal s1 s2"
           using f3 by presburger
         have f6: "fst (fst (get_curr_win () s1)) = ucast (get_CWP (cpu_reg_val PSR s1))"
           using f3 by auto
         have f7: "cpu_reg_val PSR s1 = cpu_reg_val PSR s2"
           using a1 by (meson cpu_reg_val_low_equal)
         have f8: "\<forall>s sa w wa. \<not> low_equal s sa \<or> user_reg_val (w::'a word) wa s = user_reg_val w wa sa"
           by (meson user_reg_val_low_equal)
         have f9: "ucast (get_CWP (cpu_reg_val PSR s2)) = fst (fst (get_curr_win () s2))"
           using f4 by meson
         have "\<forall>s sa is. \<not> low_equal (s::'a sparc_state) sa \<or> get_operand2 is s = get_operand2 is sa"
           using get_operand2_low_equal by blast
         then have f10: "get_operand2 (snd instr) s1 = get_operand2 (snd instr) s2"
           using a1 by meson
         have f11: "cpu_reg_val PSR (snd (fst (get_curr_win () s2))) = cpu_reg_val PSR s1"
           using f4 a1 by (simp add: cpu_reg_val_low_equal)
         have f12: "user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (get_curr_win () s1))) = 0"
           by (meson user_reg_val_def)
         have "user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2))) = 0"
           by (meson user_reg_val_def)
         then have "low_equal (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (get_curr_win () s1)))))) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2))))))"
           using f12 f9 f7 f5 f3 a1 write_reg_low_equal by fastforce
         then have "low_equal (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (get_curr_win () s1)))))) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2)))))) \<and> snd (fst (add_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) + get_operand2 (snd instr) s1 + ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s1)))))) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) (get_operand2 (snd instr) s1) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (get_curr_win () s1)))))))) = snd (fst (add_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) + get_operand2 (snd instr) s2 + ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s2)))))) (if get_operand_w5 (snd instr ! Suc 0) = 0 then 0 else user_reg (snd (fst (get_curr_win () s2))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))) (get_operand2 (snd instr) s2) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (get_curr_win () s1)))))))) \<and> snd (fst (add_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) + get_operand2 (snd instr) s2 + ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s2)))))) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) (get_operand2 (snd instr) s2) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2)))))))) = snd (fst (add_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) + get_operand2 (snd instr) s2 + ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s2)))))) (if get_operand_w5 (snd instr ! Suc 0) = 0 then 0 else user_reg (snd (fst (get_curr_win () s2))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))) (get_operand2 (snd instr) s2) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2))))))))"
           using f11 f10 f9 f8 f7 f6 f5 f3 a1 by (simp add: user_reg_val_def)
         then show "low_equal (snd (fst (add_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) + get_operand2 (snd instr) s1 + ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s1)))))) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) (get_operand2 (snd instr) s1) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (get_curr_win () s1))))))))) (snd (fst (add_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) + get_operand2 (snd instr) s2 + ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s2)))))) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) (get_operand2 (snd instr) s2) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2)))))))))"
           using add_instr_sub1_low_equal by blast
       qed      
     qed
   qed
 qed
 
 lemma sub_instr_sub1_low_equal:
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (sub_instr_sub1 instr_name result rs1_val operand2 s1)) \<and> 
 t2 = snd (fst (sub_instr_sub1 instr_name result rs1_val operand2 s2))"
 shows "low_equal t1 t2"
 proof (cases "instr_name = arith_type SUBcc \<or> instr_name = arith_type SUBXcc")
   case True
   then show ?thesis using a1
   apply (simp add: sub_instr_sub1_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   apply (clarsimp simp add: cpu_reg_val_low_equal)
   using write_cpu_low_equal by blast
 next
   case False
   then show ?thesis using a1
   apply (simp add: sub_instr_sub1_def)
   by (simp add: return_def)
 qed
 
 lemma sub_instr_low_equal:
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (sub_instr instr s1)) \<and> t2 = snd (fst (sub_instr instr s2))"
 shows "low_equal t1 t2"
 proof -
   have f1: "low_equal s1 s2 \<and>
     t1 = snd (fst (sub_instr_sub1 (fst instr)
                     (if fst instr = arith_type SUB \<or> fst instr = arith_type SUBcc
                      then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0))
                            (snd (fst (get_curr_win () s1))) -
                           get_operand2 (snd instr) s1
                      else user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0))
                            (snd (fst (get_curr_win () s1))) -
                           get_operand2 (snd instr) s1 -
                           ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s1))))))
                     (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0))
                       (snd (fst (get_curr_win () s1))))
                     (get_operand2 (snd instr) s1)
                     (snd (fst (write_reg
                                 (if get_operand_w5 (snd instr ! 3) \<noteq> 0
                                  then if fst instr = arith_type SUB \<or> fst instr = arith_type SUBcc
                                       then user_reg_val (fst (fst (get_curr_win () s1)))
                                             (get_operand_w5 (snd instr ! Suc 0))
                                             (snd (fst (get_curr_win () s1))) -
                                            get_operand2 (snd instr) s1
                                       else user_reg_val (fst (fst (get_curr_win () s1)))
                                             (get_operand_w5 (snd instr ! Suc 0))
                                             (snd (fst (get_curr_win () s1))) -
                                            get_operand2 (snd instr) s1 -
                                            ucast (get_icc_C
                                                    (cpu_reg_val PSR (snd (fst (get_curr_win () s1)))))
                                  else user_reg_val (fst (fst (get_curr_win () s1)))
                                        (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s1))))
                                 (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3))
                                 (snd (fst (get_curr_win () s1)))))))) \<and>
     t2 = snd (fst (sub_instr_sub1 (fst instr)
                     (if fst instr = arith_type SUB \<or> fst instr = arith_type SUBcc
                      then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                            (snd (fst (get_curr_win () s2))) -
                           get_operand2 (snd instr) s2
                      else user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                            (snd (fst (get_curr_win () s2))) -
                           get_operand2 (snd instr) s2 -
                           ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s2))))))
                     (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                       (snd (fst (get_curr_win () s2))))
                     (get_operand2 (snd instr) s2)
                     (snd (fst (write_reg
                                 (if get_operand_w5 (snd instr ! 3) \<noteq> 0
                                  then if fst instr = arith_type SUB \<or> fst instr = arith_type SUBcc
                                       then user_reg_val (fst (fst (get_curr_win () s2)))
                                             (get_operand_w5 (snd instr ! Suc 0))
                                             (snd (fst (get_curr_win () s2))) -
                                            get_operand2 (snd instr) s2
                                       else user_reg_val (fst (fst (get_curr_win () s2)))
                                             (get_operand_w5 (snd instr ! Suc 0))
                                             (snd (fst (get_curr_win () s2))) -
                                            get_operand2 (snd instr) s2 -
                                            ucast (get_icc_C
                                                    (cpu_reg_val PSR (snd (fst (get_curr_win () s2)))))
                                  else user_reg_val (fst (fst (get_curr_win () s2)))
                                        (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s2))))
                                 (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
                                 (snd (fst (get_curr_win () s2))))))))"
   using a1 apply (simp add: sub_instr_def)
   apply (simp add: Let_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   by (simp add: case_prod_unfold)
   then show ?thesis
   proof (cases "get_operand_w5 (snd instr ! 3) \<noteq> 0")
     case True
     then have f2: "get_operand_w5 (snd instr ! 3) \<noteq> 0" by auto
     then show ?thesis
     proof (cases "fst instr = arith_type SUB \<or> fst instr = arith_type SUBcc")
       case True
       then show ?thesis
       using f1 f2 apply clarsimp
       proof -
         assume a1: "low_equal s1 s2"
         assume a2: "t1 = snd (fst (sub_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) - get_operand2 (snd instr) s1) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) (get_operand2 (snd instr) s1) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) - get_operand2 (snd instr) s1) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s1))))))))"
         assume a3: "t2 = snd (fst (sub_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) - get_operand2 (snd instr) s2) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) (get_operand2 (snd instr) s2) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) - get_operand2 (snd instr) s2) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s2))))))))"
         then have f4: "snd (fst (sub_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) - get_operand2 (snd instr) s1) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) (get_operand2 (snd instr) s1) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) - get_operand2 (snd instr) s1) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s2)))))))) = t2"
           using a1 by (simp add: get_operand2_low_equal)
         have "\<forall>s. \<not> low_equal (snd (fst (get_curr_win () s1))) s \<or> snd (fst (sub_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) s - get_operand2 (snd instr) s1) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) s) (get_operand2 (snd instr) s1) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) s - get_operand2 (snd instr) s1) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s1)))))))) = t1"
           using a2 a1 by (simp add: get_curr_win_low_equal user_reg_val_low_equal)
         then show "low_equal (snd (fst (sub_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) - get_operand2 (snd instr) s1) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) (get_operand2 (snd instr) s1) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) - get_operand2 (snd instr) s1) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s1))))))))) (snd (fst (sub_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) - get_operand2 (snd instr) s2) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) (get_operand2 (snd instr) s2) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) - get_operand2 (snd instr) s2) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s2)))))))))"
           using f4 a3 a2 a1 by (metis (no_types) get_curr_win2_low_equal sub_instr_sub1_low_equal write_reg_low_equal)
       qed      
     next
       case False
       then show ?thesis
       using f1 f2 apply clarsimp
       proof -
         assume a1: "low_equal s1 s2"
         have f2: "fst (get_curr_win () s1) = (ucast (get_CWP (cpu_reg_val PSR s1)), s1)"
           by (simp add: get_curr_win_def simpler_gets_def)
         have f3: "cpu_reg_val PSR s1 = cpu_reg_val PSR s2"
           using a1 by (meson cpu_reg_val_low_equal)
         then have f4: "user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) = user_reg_val (ucast (get_CWP (cpu_reg_val PSR s2))) (get_operand_w5 (snd instr ! Suc 0)) s1"
           using f2 by simp
         have f5: "\<forall>s sa is. \<not> low_equal (s::'a sparc_state) sa \<or> get_operand2 is s = get_operand2 is sa"
           using get_operand2_low_equal by blast
         then have f6: "sub_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) - get_operand2 (snd instr) s1 - ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s1)))))) (user_reg_val (ucast (get_CWP (cpu_reg_val PSR s2))) (get_operand_w5 (snd instr ! Suc 0)) s2) (get_operand2 (snd instr) s2) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) - get_operand2 (snd instr) s1 - ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s1)))))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s1)))))) = sub_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) - get_operand2 (snd instr) s1 - ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s1)))))) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) (get_operand2 (snd instr) s1) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) - get_operand2 (snd instr) s1 - ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s1)))))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s1))))))"
           using f4 a1 by (simp add: user_reg_val_low_equal)
         have f7: "fst (get_curr_win () s2) = (ucast (get_CWP (cpu_reg_val PSR s2)), s2)"
           by (simp add: get_curr_win_def simpler_gets_def)
         then have f8: "user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) - get_operand2 (snd instr) s2 - ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s2))))) = user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) - get_operand2 (snd instr) s1 - ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s1)))))"
           using f5 f2 a1 by (simp add: cpu_reg_val_low_equal user_reg_val_low_equal)
         then have f9: "sub_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) - get_operand2 (snd instr) s1 - ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s1)))))) (user_reg_val (ucast (get_CWP (cpu_reg_val PSR s2))) (get_operand_w5 (snd instr ! Suc 0)) s2) (get_operand2 (snd instr) s2) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) - get_operand2 (snd instr) s2 - ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s2)))))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s2)))))) = sub_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) - get_operand2 (snd instr) s2 - ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s2)))))) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) (get_operand2 (snd instr) s2) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) - get_operand2 (snd instr) s2 - ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s2)))))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s2))))))"
           using f7 by fastforce
         have "write_reg (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) - get_operand2 (snd instr) s1 - ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s1)))))) (ucast (get_CWP (cpu_reg_val PSR s2))) (get_operand_w5 (snd instr ! 3)) s2 = write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) - get_operand2 (snd instr) s2 - ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s2)))))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s2)))"
           using f8 f7 by simp
         then have "low_equal (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) - get_operand2 (snd instr) s1 - ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s1)))))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s1)))))) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) - get_operand2 (snd instr) s2 - ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s2)))))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s2))))))"
           using f3 f2 a1 by (metis (no_types) prod.sel(1) prod.sel(2) write_reg_low_equal)
         then show "low_equal (snd (fst (sub_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) - get_operand2 (snd instr) s1 - ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s1)))))) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) (get_operand2 (snd instr) s1) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) - get_operand2 (snd instr) s1 - ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s1)))))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s1))))))))) (snd (fst (sub_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) - get_operand2 (snd instr) s2 - ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s2)))))) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) (get_operand2 (snd instr) s2) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) - get_operand2 (snd instr) s2 - ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s2)))))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (get_curr_win () s2)))))))))"
           using f9 f6 by (metis (no_types) sub_instr_sub1_low_equal)
       qed      
     qed
   next
     case False
     then have f3: "\<not> get_operand_w5 (snd instr ! 3) \<noteq> 0" by auto
     then show ?thesis
     proof (cases "fst instr = arith_type SUB \<or> fst instr = arith_type SUBcc")
       case True
       then show ?thesis
       using f1 f3 apply clarsimp
       proof -
         assume a1: "low_equal s1 s2"
         assume "t1 = snd (fst (sub_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) - get_operand2 (snd instr) s1) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) (get_operand2 (snd instr) s1) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (get_curr_win () s1))))))))"
         assume "t2 = snd (fst (sub_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) - get_operand2 (snd instr) s2) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) (get_operand2 (snd instr) s2) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2))))))))"
         have f2: "\<forall>is. get_operand2 is s1 = get_operand2 is s2"
           using a1 get_operand2_low_equal by blast
         have f3: "fst (fst (get_curr_win () s1)) = fst (fst (get_curr_win () s2))"
           using a1 by (meson get_curr_win_low_equal)
         have "\<forall>w wa. user_reg_val wa w (snd (fst (get_curr_win () s1))) = user_reg_val wa w (snd (fst (get_curr_win () s2)))"
           using a1 by (metis (no_types) get_curr_win2_low_equal user_reg_val_low_equal)
         then show "low_equal (snd (fst (sub_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) - get_operand2 (snd instr) s1) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) (get_operand2 (snd instr) s1) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (get_curr_win () s1))))))))) (snd (fst (sub_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) - get_operand2 (snd instr) s2) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) (get_operand2 (snd instr) s2) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2)))))))))"
           using f3 f2 a1 by (metis (no_types) get_curr_win2_low_equal sub_instr_sub1_low_equal write_reg_low_equal)
       qed      
     next
       case False
       then show ?thesis
       using f1 f3 apply clarsimp
       proof -
         assume a1: "low_equal s1 s2"
         have f2: "\<forall>s sa sb w wa wb sc. (\<not> low_equal s sa \<or> sb \<noteq> snd (fst (write_reg w (wa::'a word) wb s)) \<or> sc \<noteq> snd (fst (write_reg w wa wb sa))) \<or> low_equal sb sc"
           by (meson write_reg_low_equal)
         have "((ucast (get_CWP (cpu_reg_val PSR s1)), s1), False) = get_curr_win () s1"
           by (simp add: get_curr_win_def simpler_gets_def)
         then have f3: "ucast (get_CWP (cpu_reg_val PSR s1)) = fst (fst (get_curr_win () s1)) \<and> s1 = snd (fst (get_curr_win () s1))"
           by (metis (no_types) prod.collapse prod.simps(1))
         have "((ucast (get_CWP (cpu_reg_val PSR s2)), s2), False) = get_curr_win () s2"
           by (simp add: get_curr_win_def simpler_gets_def)
         then have f4: "ucast (get_CWP (cpu_reg_val PSR s2)) = fst (fst (get_curr_win () s2)) \<and> s2 = snd (fst (get_curr_win () s2))"
           by (metis (no_types) prod.collapse prod.simps(1))
         have f5: "\<forall>s sa sb sc w wa wb sd. (\<not> low_equal (s::'a sparc_state) sa \<or> sb \<noteq> snd (fst (sub_instr_sub1 sc w wa wb s)) \<or> sd \<noteq> snd (fst (sub_instr_sub1 sc w wa wb sa))) \<or> low_equal sb sd"
           by (meson sub_instr_sub1_low_equal)
         have "low_equal (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (get_curr_win () s1)))))) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2))))))"
           using f4 f3 f2 a1 by (simp add: cpu_reg_val_low_equal user_reg_val_low_equal)
         then show "low_equal (snd (fst (sub_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) - get_operand2 (snd instr) s1 - ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s1)))))) (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) (get_operand2 (snd instr) s1) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (get_curr_win () s1))))))))) (snd (fst (sub_instr_sub1 (fst instr) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) - get_operand2 (snd instr) s2 - ucast (get_icc_C (cpu_reg_val PSR (snd (fst (get_curr_win () s2)))))) (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) (get_operand2 (snd instr) s2) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2)))))))))"
           using f5 f4 f3 a1 by (simp add: cpu_reg_val_low_equal get_operand2_low_equal user_reg_val_low_equal)
       qed      
     qed
   qed
 qed
 
 lemma mul_instr_sub1_low_equal:
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (mul_instr_sub1 instr_name result s1)) \<and>
 t2 = snd (fst (mul_instr_sub1 instr_name result s2))"
 shows "low_equal t1 t2"
 proof (cases "instr_name \<in> {arith_type SMULcc,arith_type UMULcc}")
   case True
   then show ?thesis using a1
   apply (simp add: mul_instr_sub1_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   apply (clarsimp simp add: cpu_reg_val_low_equal)
   using write_cpu_low_equal by blast
 next
   case False
   then show ?thesis using a1
   apply (simp add: mul_instr_sub1_def)
   by (simp add: return_def)
 qed
 
 lemma mul_instr_low_equal:
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (mul_instr instr s1)) \<and> t2 = snd (fst (mul_instr instr s2))"
 shows "low_equal t1 t2"
 using a1
 apply (simp add: mul_instr_def)
 apply (simp add: Let_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 proof -
   assume a1: "low_equal s1 s2 \<and> t1 = snd (fst (mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) \<noteq> 0 then ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) else user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1))))))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1))))))))))) \<and> t2 = snd (fst (mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) \<noteq> 0 then ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) else user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2))))))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))))"
   have f2: "\<forall>s sa sb sc w sd. \<not> low_equal (s::'a sparc_state) sa \<or> sb \<noteq> snd (fst (mul_instr_sub1 sc w s)) \<or> sd \<noteq> snd (fst (mul_instr_sub1 sc w sa)) \<or> low_equal sb sd"
     using mul_instr_sub1_low_equal by blast
   have f3: "\<forall>s sa sb w wa wb sc. \<not> low_equal s sa \<or> sb \<noteq> snd (fst (write_reg w (wa::'a word) wb s)) \<or> sc \<noteq> snd (fst (write_reg w wa wb sa)) \<or> low_equal sb sc"
     by (meson write_reg_low_equal)
   have f4: "\<forall>s sa sb w c sc. \<not> low_equal (s::'a sparc_state) sa \<or> sb \<noteq> snd (fst (write_cpu w c s)) \<or> sc \<noteq> snd (fst (write_cpu w c sa)) \<or> low_equal sb sc"
     by (meson write_cpu_low_equal)
   have f5: "low_equal s1 s2 \<and> t1 = snd (fst (mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1))))))))))) \<and> t2 = snd (fst (mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))))"
     using a1 by presburger
   have f6: "((ucast (get_CWP (cpu_reg_val PSR s1)), s1), False) = (fst (get_curr_win () s1), snd (get_curr_win () s1))"
     by (simp add: get_curr_win_def simpler_gets_def)
   have f7: "fst (fst (get_curr_win () s1)) = fst (fst (get_curr_win () s2))"
     using f5 by (meson get_curr_win_low_equal)
   have "((ucast (get_CWP (cpu_reg_val PSR s2)), s2), False) = (fst (get_curr_win () s2), snd (get_curr_win () s2))"
     by (simp add: get_curr_win_def simpler_gets_def)
   then have f8: "ucast (get_CWP (cpu_reg_val PSR s2)) = fst (fst (get_curr_win () s2)) \<and> s2 = snd (fst (get_curr_win () s2))"
     by (metis prod.collapse prod.simps(1))
   then have f9: "low_equal (snd (fst (get_curr_win () s1))) (snd (fst (get_curr_win () s2)))"
     using f6 f5 by (metis (no_types) prod.collapse prod.simps(1))
   have f10: "\<forall>s sa w wa. \<not> low_equal s sa \<or> user_reg_val (w::'a word) wa s = user_reg_val w wa sa"
     using user_reg_val_low_equal by blast
   have f11: "get_operand2 (snd instr) s1 = get_operand2 (snd instr) (snd (fst (get_curr_win () s2)))"
     using f9 f6 by (metis (no_types) get_operand2_low_equal prod.collapse prod.simps(1))
   then have f12: "uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2) = uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1)"
     using f10 f9 f8 f7 by presburger
   then have f13: "(word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) \<noteq> (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1)) else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) \<or> (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) \<noteq> (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2)) else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) \<or> low_equal (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2))))))"
     using f9 f4 by presburger
   have "get_operand_w5 (snd instr ! 3) = 0 \<and> low_equal (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) \<longrightarrow> write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) = write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1))))))"
     using f10 f7 by force
   then have f14: "get_operand_w5 (snd instr ! 3) \<noteq> 0 \<or> low_equal (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1))))))))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2))))))))) \<or> \<not> low_equal (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2))))))"
     using f3 by metis 
   then have f15: "low_equal (snd (fst (mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))))) \<or> fst instr \<noteq> arith_type UMULcc \<or> get_operand_w5 (snd instr ! 3) \<noteq> 0 \<or> (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) \<noteq> (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1)) else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) \<or> (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) \<noteq> (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2)) else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))"
     using f13 f12 f2 by fastforce
   have f16: "user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) = user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))"
     using f10 f9 f7 by presburger
   { assume "fst instr \<noteq> arith_type UMUL \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))"
     moreover
     { assume "\<not> low_equal (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))"
       moreover
       { assume "low_equal (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))))) \<noteq> low_equal (snd (fst (mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))"
         moreover
         { assume "mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1))))))))) \<noteq> mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))"
           then have "write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))) \<noteq> write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) \<or> fst instr \<noteq> arith_type UMULcc"
             by fastforce }
         moreover
         { assume "mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))) \<noteq> mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))"
           then have "write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2)))))) \<noteq> write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) \<or> fst instr \<noteq> arith_type UMULcc"
             by fastforce }
         ultimately have "write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2)))))) \<noteq> write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) \<or> write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))) \<noteq> write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) \<or> fst instr \<noteq> arith_type UMULcc"
           by force }
       ultimately have "write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2)))))) \<noteq> write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) \<or> write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))) \<noteq> write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) \<or> \<not> low_equal (snd (fst (mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))))) \<or> fst instr \<noteq> arith_type UMULcc"
         by fastforce }
     ultimately have "fst instr = arith_type UMULcc \<and> low_equal (snd (fst (mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))))) \<and> write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))) = write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) \<and> write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2)))))) = write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) \<longrightarrow> get_operand_w5 (snd instr ! 3) = 0 \<or> (fst instr \<noteq> arith_type UMUL \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr \<noteq> arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))))))"
       by blast }
   moreover
   { assume "\<not> low_equal (snd (fst (mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))"
     moreover
     { assume "\<not> low_equal (snd (fst (mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))))) \<and> snd (fst (mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1))))))))))) = snd (fst (mul_instr_sub1 (arith_type UMULcc) (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1))))))))))) \<and> snd (fst (mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))) = snd (fst (mul_instr_sub1 (arith_type UMULcc) (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))))"
       then have "\<not> low_equal (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1))))))))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))"
         using f2 by blast
       moreover
       { assume "(if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) \<noteq> (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))))"
         moreover
         { assume "(if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) \<noteq> ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))"
           then have "(if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) = (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1)) else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) \<longrightarrow> get_operand_w5 (snd instr ! 3) = 0"
             by (metis f11 f16 f8) }
         ultimately have "(if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) = (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1)) else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) \<longrightarrow> get_operand_w5 (snd instr ! 3) = 0"
           by fastforce }
       ultimately have "fst instr = arith_type UMULcc \<and> (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) = (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1)) else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) \<longrightarrow> get_operand_w5 (snd instr ! 3) = 0"
         using f13 f7 f3 by fastforce }
     moreover
     { assume "mul_instr_sub1 (arith_type UMULcc) (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2))))))))) \<noteq> mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))"
       moreover
       { assume "(if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) \<noteq> ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))"
         then have "(if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) = (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1)) else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) \<longrightarrow> get_operand_w5 (snd instr ! 3) = 0"
           by (metis f11 f16 f8) }
       ultimately have "fst instr = arith_type UMULcc \<and> (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) = (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1)) else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) \<longrightarrow> get_operand_w5 (snd instr ! 3) = 0"
         by fastforce }
     ultimately have "fst instr = arith_type UMULcc \<longrightarrow> get_operand_w5 (snd instr ! 3) = 0"
       using f12 by fastforce }
   moreover
   { assume "write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2)))))) \<noteq> write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2))))))"
     then have "fst instr = arith_type UMULcc \<longrightarrow> get_operand_w5 (snd instr ! 3) = 0"
       by presburger }
   ultimately have "fst instr = arith_type UMULcc \<longrightarrow> get_operand_w5 (snd instr ! 3) = 0 \<or> get_operand_w5 (snd instr ! 3) = 0 \<or> (fst instr \<noteq> arith_type UMUL \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr \<noteq> arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))))))"
     by force
   moreover
   { assume "fst instr \<noteq> arith_type UMULcc"
     { assume "fst instr \<noteq> arith_type UMULcc \<and> low_equal (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1))))))))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))"
       moreover
       { assume "fst instr \<noteq> arith_type UMULcc \<and> low_equal (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1))))))))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2))))))))) \<and> snd (fst (mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))) = snd (fst (mul_instr_sub1 (arith_type UMUL) (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))))"
         then have "(fst instr \<noteq> arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> fst instr \<noteq> arith_type UMUL \<and> fst instr \<noteq> arith_type UMULcc \<or> (get_operand_w5 (snd instr ! 3) = 0 \<or> (fst instr \<noteq> arith_type UMUL \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr \<noteq> arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))))))) \<or> get_operand_w5 (snd instr ! 3) = 0"
           using f2 by presburger }
       ultimately have "fst instr \<noteq> arith_type UMULcc \<and> (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) \<noteq> ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) \<or> (fst instr \<noteq> arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> fst instr \<noteq> arith_type UMUL \<and> fst instr \<noteq> arith_type UMULcc \<or> (get_operand_w5 (snd instr ! 3) = 0 \<or> (fst instr \<noteq> arith_type UMUL \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr \<noteq> arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))))))) \<or> get_operand_w5 (snd instr ! 3) = 0"
         by fastforce }
     then have "(get_operand_w5 (snd instr ! 3) = 0 \<or> (fst instr \<noteq> arith_type UMUL \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr \<noteq> arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))))))) \<or> get_operand_w5 (snd instr ! 3) = 0"
       using f16 f11 f9 f8 f7 f4 f3 f2 by force }
   moreover
   { assume "get_operand_w5 (snd instr ! 3) = 0"
     moreover
     { assume "(fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc) \<and> get_operand_w5 (snd instr ! 3) = 0"
       moreover
       { assume "((fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc) \<and> get_operand_w5 (snd instr ! 3) = 0) \<and> \<not> low_equal (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1))))))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))"
         moreover
         { assume "((fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc) \<and> get_operand_w5 (snd instr ! 3) = 0) \<and> low_equal (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1))))))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))))) \<noteq> low_equal (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1))))))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))"
           then have "((fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc) \<and> get_operand_w5 (snd instr ! 3) = 0) \<and> arith_type UMUL \<noteq> arith_type UMULcc \<or> fst instr \<noteq> arith_type UMULcc \<and> (fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc) \<and> get_operand_w5 (snd instr ! 3) = 0"
             by fastforce
           then have "((fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc) \<and> get_operand_w5 (snd instr ! 3) = 0) \<and> (fst instr \<noteq> arith_type UMUL \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1))))))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<or> fst instr \<noteq> arith_type UMULcc \<and> (fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc) \<and> get_operand_w5 (snd instr ! 3) = 0"
             by force }
         ultimately have "((fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc) \<and> get_operand_w5 (snd instr ! 3) = 0) \<and> (fst instr \<noteq> arith_type UMUL \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1))))))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<or> ((fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc) \<and> get_operand_w5 (snd instr ! 3) = 0) \<and> \<not> low_equal (snd (fst (mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))))) \<or> fst instr \<noteq> arith_type UMULcc \<and> (fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc) \<and> get_operand_w5 (snd instr ! 3) = 0"
           by simp }
       ultimately have "((fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc) \<and> get_operand_w5 (snd instr ! 3) = 0) \<and> \<not> low_equal (snd (fst (mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1)))) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (fst instr) (ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (snd (fst (write_reg (if get_operand_w5 (snd instr ! 3) = 0 then user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))) else ucast (if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((if fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc then word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64 else word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))))) \<or> fst instr \<noteq> arith_type UMULcc \<and> (fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc) \<and> get_operand_w5 (snd instr ! 3) = 0 \<or> (get_operand_w5 (snd instr ! 3) = 0 \<or> (fst instr \<noteq> arith_type UMUL \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr \<noteq> arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))))))) \<and> (get_operand_w5 (snd instr ! 3) \<noteq> 0 \<or> (fst instr \<noteq> arith_type UMUL \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1))))))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr \<noteq> arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1))))))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1))))))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))))"
         by auto
       then have "fst instr \<noteq> arith_type UMULcc \<and> (fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc) \<and> get_operand_w5 (snd instr ! 3) = 0 \<or> (get_operand_w5 (snd instr ! 3) = 0 \<or> (fst instr \<noteq> arith_type UMUL \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr \<noteq> arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))))))) \<and> (get_operand_w5 (snd instr ! 3) \<noteq> 0 \<or> (fst instr \<noteq> arith_type UMUL \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1))))))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr \<noteq> arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1))))))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1))))))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))))"
         using f15 by presburger
       then have "(get_operand_w5 (snd instr ! 3) = 0 \<or> (fst instr \<noteq> arith_type UMUL \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr \<noteq> arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))))))) \<and> (get_operand_w5 (snd instr ! 3) \<noteq> 0 \<or> (fst instr \<noteq> arith_type UMUL \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1))))))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr \<noteq> arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1))))))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1))))))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))))"
         using f14 f13 f12 f2 by force }
     ultimately have "(get_operand_w5 (snd instr ! 3) = 0 \<or> (fst instr \<noteq> arith_type UMUL \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr \<noteq> arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))))))) \<and> (get_operand_w5 (snd instr ! 3) \<noteq> 0 \<or> (fst instr \<noteq> arith_type UMUL \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1))))))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr \<noteq> arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1))))))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr = arith_type UMUL \<or> fst instr = arith_type UMULcc \<or> low_equal (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1))))))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))))"
       using f16 f14 f11 f9 f8 f4 f2 by fastforce }
   ultimately show "(get_operand_w5 (snd instr ! 3) \<noteq> 0 \<longrightarrow> (fst instr = arith_type UMUL \<longrightarrow> low_equal (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr = arith_type UMULcc \<longrightarrow> low_equal (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr \<noteq> arith_type UMUL \<and> fst instr \<noteq> arith_type UMULcc \<longrightarrow> low_equal (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3)) (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2)))))))))))))) \<and> (get_operand_w5 (snd instr ! 3) = 0 \<longrightarrow> (fst instr = arith_type UMUL \<longrightarrow> low_equal (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1))))))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMUL) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr = arith_type UMULcc \<longrightarrow> low_equal (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1))))))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * uint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (arith_type UMULcc) (ucast (word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (uint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * uint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))) \<and> (fst instr \<noteq> arith_type UMUL \<and> fst instr \<noteq> arith_type UMULcc \<longrightarrow> low_equal (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1))))))) (fst (fst (get_curr_win () s1))) 0 (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s1))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))) * sint (get_operand2 (snd instr) s1))::word64) >> 32)) Y (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (mul_instr_sub1 (fst instr) (ucast (word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64)) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (write_cpu (ucast ((word_of_int (sint (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))) * sint (get_operand2 (snd instr) s2))::word64) >> 32)) Y (snd (fst (get_curr_win () s2))))))))))))))"
     by blast
 qed
 
 lemma div_write_new_val_low_equal:
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (div_write_new_val i result temp_V s1)) \<and>
 t2 = snd (fst (div_write_new_val i result temp_V s2))"
 shows "low_equal t1 t2"
 proof (cases "(fst i) \<in> {arith_type UDIVcc,arith_type SDIVcc}")
   case True
   then show ?thesis using a1
   apply (simp add: div_write_new_val_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   apply (clarsimp simp add: cpu_reg_val_low_equal)
   using write_cpu_low_equal by blast
 next
   case False
   then show ?thesis using a1
   apply (simp add: div_write_new_val_def)
   by (simp add: return_def)
 qed
 
 lemma div_comp_low_equal:
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (div_comp instr rs1 rd operand2 s1)) \<and>
 t2 = snd (fst (div_comp instr rs1 rd operand2 s2))"
 shows "low_equal t1 t2"
 using a1
 apply (simp add: div_comp_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 apply (clarsimp simp add: get_curr_win_low_equal)
 proof -
   assume a1: "low_equal s1 s2"
   have f2: "\<forall>s sa sb w wa wb sc. \<not> low_equal s sa \<or> sb \<noteq> snd (fst (write_reg w (wa::'a word) wb s)) \<or> sc \<noteq> snd (fst (write_reg w wa wb sa)) \<or> low_equal sb sc"
     by (meson write_reg_low_equal)
   have f3: "gets (\<lambda>s. ucast (get_CWP (cpu_reg_val PSR s))::'a word) = get_curr_win ()"
     by (simp add: get_curr_win_def)
   then have "((ucast (get_CWP (cpu_reg_val PSR s1)), s1), False) = (fst (get_curr_win () s1), snd (get_curr_win () s1))"
     by (metis (no_types) prod.collapse simpler_gets_def)
   then have f4: "ucast (get_CWP (cpu_reg_val PSR s1)) = fst (fst (get_curr_win () s1)) \<and> s1 = snd (fst (get_curr_win () s1))"
     by (metis prod.collapse prod.simps(1))
   have "((ucast (get_CWP (cpu_reg_val PSR s2)), s2), False) = (fst (get_curr_win () s2), snd (get_curr_win () s2))"
     using f3 by (metis (no_types) prod.collapse simpler_gets_def)
   then have f5: "ucast (get_CWP (cpu_reg_val PSR s2)) = fst (fst (get_curr_win () s2)) \<and> s2 = snd (fst (get_curr_win () s2))"
     by (metis (no_types) prod.collapse prod.simps(1))
   then have f6: "low_equal (snd (fst (get_curr_win () s1))) (snd (fst (get_curr_win () s2)))"
     using f4 a1 by presburger
   have f7: "\<forall>s sa sb p w wa sc. \<not> low_equal (s::'a sparc_state) sa \<or> sb \<noteq> snd (fst (div_write_new_val p w wa s)) \<or> sc \<noteq> snd (fst (div_write_new_val p w wa sa)) \<or> low_equal sb sc"
     by (meson div_write_new_val_low_equal)
   have f8: "cpu_reg_val PSR s2 = cpu_reg_val PSR s1"
     using a1 by (simp add: cpu_reg_val_def low_equal_def)
   then have "fst (fst (get_curr_win () s2)) = ucast (get_CWP (cpu_reg_val PSR s1))"
     using f5 by presburger
   then have f9: "fst (fst (get_curr_win () s2)) = fst (fst (get_curr_win () s1))"
     using f4 by presburger
   have f10: "fst (fst (get_curr_win () s1)) = fst (fst (get_curr_win () s2))"
     using f8 f5 f4 by presburger
   have f11: "(word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))::word64) = word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))"
     using f5 f4 a1 by (metis (no_types) cpu_reg_val_def low_equal_def user_reg_val_low_equal)
   have f12: "ucast (get_CWP (cpu_reg_val PSR s1)) = fst (fst (get_curr_win () s2))"
     using f8 f5 by presburger
   then have "rd = 0 \<longrightarrow> (if rd = 0 then user_reg_val (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s2))) else div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) = user_reg_val (ucast (get_CWP (cpu_reg_val PSR s1))) 0 (snd (fst (get_curr_win () s1)))"
     using f6 user_reg_val_low_equal by fastforce
   then have f13: "rd = 0 \<longrightarrow> write_reg (if rd = 0 then user_reg_val (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s2))) else div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (ucast (get_CWP (cpu_reg_val PSR s1))) 0 (snd (fst (get_curr_win () s1))) = write_reg (if rd = 0 then user_reg_val (fst (fst (get_curr_win () s1))) rd (snd (fst (get_curr_win () s1))) else div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s1)))"
     using f12 f10 by presburger
   have f14: "write_reg (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (ucast (get_CWP (cpu_reg_val PSR s1))) rd (snd (fst (get_curr_win () s2))) = write_reg (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s2)))"
     using f12 f11 by auto
   have "write_reg (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (ucast (get_CWP (cpu_reg_val PSR s1))) rd (snd (fst (get_curr_win () s1))) = write_reg (if rd = 0 then user_reg_val (fst (fst (get_curr_win () s1))) rd (snd (fst (get_curr_win () s1))) else div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s1))) \<and> write_reg (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (ucast (get_CWP (cpu_reg_val PSR s1))) rd (snd (fst (get_curr_win () s2))) = write_reg (if rd = 0 then user_reg_val (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s2))) else div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s2))) \<longrightarrow> low_equal (snd (fst (write_reg (if rd = 0 then user_reg_val (fst (fst (get_curr_win () s1))) rd (snd (fst (get_curr_win () s1))) else div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s1)))))) (snd (fst (write_reg (if rd = 0 then user_reg_val (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s2))) else div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s2))))))"
     using f6 f2 by metis
   moreover
   { assume "low_equal (snd (fst (write_reg (if rd = 0 then user_reg_val (fst (fst (get_curr_win () s1))) rd (snd (fst (get_curr_win () s1))) else div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s1)))))) (snd (fst (write_reg (if rd = 0 then user_reg_val (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s2))) else div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s2))))))"
     then have "low_equal (snd (fst (div_write_new_val instr (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (snd (fst (write_reg (if rd = 0 then user_reg_val (fst (fst (get_curr_win () s1))) rd (snd (fst (get_curr_win () s1))) else div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s1))))))))) (snd (fst (div_write_new_val instr (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (snd (fst (write_reg (if rd = 0 then user_reg_val (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s2))) else div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s2)))))))))"
       using f11 f9 f7 by metis 
     moreover
     { assume "low_equal (snd (fst (div_write_new_val instr (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (snd (fst (write_reg (if rd = 0 then user_reg_val (fst (fst (get_curr_win () s1))) rd (snd (fst (get_curr_win () s1))) else div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s1))))))))) (snd (fst (div_write_new_val instr (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (snd (fst (write_reg (if rd = 0 then user_reg_val (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s2))) else div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s2))))))))) \<noteq> low_equal (snd (fst (div_write_new_val instr (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (snd (fst (write_reg (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s1))))))))) (snd (fst (div_write_new_val instr (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (snd (fst (write_reg (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s2)))))))))"
       then have "div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2) = (if rd = 0 then user_reg_val (fst (fst (get_curr_win () s1))) rd (snd (fst (get_curr_win () s1))) else div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) \<longrightarrow> rd = 0"
         by fastforce }
     ultimately have "div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2) = (if rd = 0 then user_reg_val (fst (fst (get_curr_win () s1))) rd (snd (fst (get_curr_win () s1))) else div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) \<longrightarrow> rd = 0 \<or> (rd \<noteq> 0 \<longrightarrow> low_equal (snd (fst (div_write_new_val instr (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (snd (fst (write_reg (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s1))))))))) (snd (fst (div_write_new_val instr (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (snd (fst (write_reg (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s2)))))))))) \<and> (rd = 0 \<longrightarrow> low_equal (snd (fst (div_write_new_val instr (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s1))))))))) (snd (fst (div_write_new_val instr (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2))))))))))"
       by fastforce }
   moreover
   { assume "write_reg (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (ucast (get_CWP (cpu_reg_val PSR s1))) rd (snd (fst (get_curr_win () s1))) \<noteq> write_reg (if rd = 0 then user_reg_val (fst (fst (get_curr_win () s1))) rd (snd (fst (get_curr_win () s1))) else div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s1)))"
     then have "div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2) \<noteq> (if rd = 0 then user_reg_val (fst (fst (get_curr_win () s1))) rd (snd (fst (get_curr_win () s1))) else div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2))"
       using f12 f9 by fastforce }
   moreover
   { assume "write_reg (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (ucast (get_CWP (cpu_reg_val PSR s1))) rd (snd (fst (get_curr_win () s2))) \<noteq> write_reg (if rd = 0 then user_reg_val (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s2))) else div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s2)))"
     then have "rd = 0"
       using f14 by presburger }
   moreover
   { assume "rd = 0"
     then have "rd = 0 \<and> low_equal (snd (fst (write_reg (if rd = 0 then user_reg_val (fst (fst (get_curr_win () s1))) rd (snd (fst (get_curr_win () s1))) else div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s1)))))) (snd (fst (write_reg (if rd = 0 then user_reg_val (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s2))) else div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s2))))))"
       using f13 f12 f6 f2 by metis 
     then have "rd = 0 \<and> low_equal (snd (fst (div_write_new_val instr (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (snd (fst (write_reg (if rd = 0 then user_reg_val (fst (fst (get_curr_win () s1))) rd (snd (fst (get_curr_win () s1))) else div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s1))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s1))))))))) (snd (fst (div_write_new_val instr (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (snd (fst (write_reg (if rd = 0 then user_reg_val (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s2))) else div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s2)))))))))"
       using f11 f9 f7 by metis 
     then have "(rd \<noteq> 0 \<longrightarrow> low_equal (snd (fst (div_write_new_val instr (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (snd (fst (write_reg (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s1))))))))) (snd (fst (div_write_new_val instr (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (snd (fst (write_reg (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s2)))))))))) \<and> (rd = 0 \<longrightarrow> low_equal (snd (fst (div_write_new_val instr (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s1))))))))) (snd (fst (div_write_new_val instr (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2))))))))))"
       using f10 by fastforce }
   ultimately show "(rd \<noteq> 0 \<longrightarrow> low_equal (snd (fst (div_write_new_val instr (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (snd (fst (write_reg (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s1))))))))) (snd (fst (div_write_new_val instr (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (snd (fst (write_reg (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (fst (fst (get_curr_win () s2))) rd (snd (fst (get_curr_win () s2)))))))))) \<and> (rd = 0 \<longrightarrow> low_equal (snd (fst (div_write_new_val instr (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2)) (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s1))))) operand2 >> 31))) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s1))))))))) (snd (fst (div_write_new_val instr (div_comp_result instr (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2)) (div_comp_temp_V instr (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 32)) (ucast (div_comp_temp_64bit instr (word_cat (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (user_reg_val (fst (fst (get_curr_win () s2))) rs1 (snd (fst (get_curr_win () s2))))) operand2 >> 31))) (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) 0 (snd (fst (get_curr_win () s2))))))))))"
     using f9 by fastforce
 qed
 
 lemma div_instr_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (div_instr instr s1)) \<and> t2 = snd (fst (div_instr instr s2))"
 shows "low_equal t1 t2"
 using a1
 apply (simp add: div_instr_def)
 apply (simp add: Let_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 apply (simp add: return_def)
 apply (auto simp add: get_operand2_low_equal)
  apply (simp add: raise_trap_def add_trap_set_def simpler_modify_def)
  apply (auto simp add: traps_low_equal)
  apply (blast intro: mod_trap_low_equal)
 using div_comp_low_equal by blast
 
 lemma get_curr_win_traps_low_equal: 
 assumes a1: "low_equal s1 s2"
 shows "low_equal
 (snd (fst (get_curr_win () s1))
   \<lparr>traps := insert some_trap (traps (snd (fst (get_curr_win () s1))))\<rparr>)
 (snd (fst (get_curr_win () s2))
   \<lparr>traps := insert some_trap (traps (snd (fst (get_curr_win () s2))))\<rparr>)"
 proof -
   from a1 have f1: "low_equal (snd (fst (get_curr_win () s1))) (snd (fst (get_curr_win () s2)))"
     using get_curr_win2_low_equal by auto
   then have f2: "(traps (snd (fst (get_curr_win () s1)))) = 
     (traps (snd (fst (get_curr_win () s2))))"
     using traps_low_equal by auto
   then show ?thesis using f1 f2 mod_trap_low_equal
   by fastforce
 qed
 
 lemma save_restore_instr_sub1_low_equal:
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (save_retore_sub1 result new_cwp rd s1)) \<and> 
 t2 = snd (fst (save_retore_sub1 result new_cwp rd s2))"
 shows "low_equal t1 t2"
 using a1
 apply (simp add: save_retore_sub1_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 apply (auto simp add: cpu_reg_val_low_equal)
 using write_cpu_low_equal write_reg_low_equal
 by fastforce
 
 lemma get_WIM_bit_low_equal: 
 assumes a1: "low_equal s1 s2"
 shows "get_WIM_bit (unat (((word_of_int ((uint (fst (fst (get_curr_win () s1))) - 1) mod NWINDOWS)))::word5))
  (cpu_reg_val WIM (snd (fst (get_curr_win () s1)))) =
 get_WIM_bit (unat (((word_of_int ((uint (fst (fst (get_curr_win () s2))) -1) mod NWINDOWS)))::word5))
   (cpu_reg_val WIM (snd (fst (get_curr_win () s2))))"
 proof -
   from a1 have f1: "low_equal (snd (fst (get_curr_win () s1))) (snd (fst (get_curr_win () s2)))"
   using get_curr_win2_low_equal by blast
   then have f2: "(cpu_reg_val WIM (snd (fst (get_curr_win () s1)))) =
     (cpu_reg_val WIM (snd (fst (get_curr_win () s2))))"
   using cpu_reg_val_low_equal by auto
   from a1 have "(fst (fst (get_curr_win () s1))) = (fst (fst (get_curr_win () s2)))"
   using get_curr_win_low_equal by auto
   then show ?thesis using f1 f2
   by auto 
 qed
 
 lemma get_WIM_bit_low_equal2: 
 assumes a1: "low_equal s1 s2"
 shows "get_WIM_bit (unat (((word_of_int ((uint (fst (fst (get_curr_win () s1))) + 1) mod NWINDOWS)))::word5))
  (cpu_reg_val WIM (snd (fst (get_curr_win () s1)))) =
 get_WIM_bit (unat (((word_of_int ((uint (fst (fst (get_curr_win () s2))) + 1) mod NWINDOWS)))::word5))
   (cpu_reg_val WIM (snd (fst (get_curr_win () s2))))"
 proof -
   from a1 have f1: "low_equal (snd (fst (get_curr_win () s1))) (snd (fst (get_curr_win () s2)))"
   using get_curr_win2_low_equal by blast
   then have f2: "(cpu_reg_val WIM (snd (fst (get_curr_win () s1)))) =
     (cpu_reg_val WIM (snd (fst (get_curr_win () s2))))"
   using cpu_reg_val_low_equal by auto
   from a1 have "(fst (fst (get_curr_win () s1))) = (fst (fst (get_curr_win () s2)))"
   using get_curr_win_low_equal by auto
   then show ?thesis using f1 f2
   by auto 
 qed
 
 lemma save_restore_instr_low_equal:
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (save_restore_instr instr s1)) \<and> t2 = snd (fst (save_restore_instr instr s2))"
 shows "low_equal t1 t2"
 proof (cases "fst instr = ctrl_type SAVE")
   case True
   then have f1: "fst instr = ctrl_type SAVE" by auto
   then show ?thesis using a1
   apply (simp add: save_restore_instr_def)
   apply (simp add: Let_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   apply (simp add: case_prod_unfold)
   apply auto
      apply (simp add: raise_trap_def add_trap_set_def simpler_modify_def)
      apply (simp add: get_curr_win_traps_low_equal)
     apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
     apply (simp add: get_WIM_bit_low_equal)
    apply (simp add: get_WIM_bit_low_equal)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   apply (simp add: get_curr_win_low_equal)
   using get_curr_win2_low_equal save_restore_instr_sub1_low_equal get_addr2_low_equal
   by metis 
 next
   case False
   then show ?thesis using a1
   apply (simp add: save_restore_instr_def)
   apply (simp add: Let_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   apply (simp add: case_prod_unfold)
   apply auto
      apply (simp add: raise_trap_def add_trap_set_def simpler_modify_def)
      apply (simp add: get_curr_win_traps_low_equal)
     apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
     apply (simp add: get_WIM_bit_low_equal2)
    apply (simp add: get_WIM_bit_low_equal2)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   apply (simp add: get_curr_win_low_equal)
   using get_curr_win2_low_equal save_restore_instr_sub1_low_equal get_addr2_low_equal
   by metis 
 qed
 
 lemma call_instr_low_equal: 
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (call_instr instr s1)) \<and> t2 = snd (fst (call_instr instr s2))"
 shows "low_equal t1 t2"
 using a1
 apply (simp add: call_instr_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 apply (auto simp add: get_curr_win_low_equal)
 using cpu_reg_val_low_equal get_curr_win2_low_equal
 write_cpu_low_equal write_reg_low_equal
 proof -
   assume a1: "low_equal s1 s2"
   assume "t1 = snd (fst (write_cpu (cpu_reg_val PC (snd (fst (get_curr_win () s1))) + (ucast (get_operand_w30 (snd instr ! 0)) << 2)) nPC (snd (fst (write_cpu (cpu_reg_val nPC (snd (fst (get_curr_win () s1)))) PC (snd (fst (write_reg (cpu_reg_val PC (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s2))) 15 (snd (fst (get_curr_win () s1)))))))))))"
   assume "t2 = snd (fst (write_cpu (cpu_reg_val PC (snd (fst (get_curr_win () s2))) + (ucast (get_operand_w30 (snd instr ! 0)) << 2)) nPC (snd (fst (write_cpu (cpu_reg_val nPC (snd (fst (get_curr_win () s2)))) PC (snd (fst (write_reg (cpu_reg_val PC (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) 15 (snd (fst (get_curr_win () s2)))))))))))"
   have "\<forall>c. cpu_reg_val c (snd (fst (get_curr_win () s1))) = cpu_reg_val c (snd (fst (get_curr_win () s2)))"
     using a1 by (meson cpu_reg_val_low_equal get_curr_win2_low_equal)
   then show "low_equal (snd (fst (write_cpu (cpu_reg_val PC (snd (fst (get_curr_win () s1))) + (ucast (get_operand_w30 (snd instr ! 0)) << 2)) nPC (snd (fst (write_cpu (cpu_reg_val nPC (snd (fst (get_curr_win () s1)))) PC (snd (fst (write_reg (cpu_reg_val PC (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s2))) 15 (snd (fst (get_curr_win () s1)))))))))))) (snd (fst (write_cpu (cpu_reg_val PC (snd (fst (get_curr_win () s2))) + (ucast (get_operand_w30 (snd instr ! 0)) << 2)) nPC (snd (fst (write_cpu (cpu_reg_val nPC (snd (fst (get_curr_win () s2)))) PC (snd (fst (write_reg (cpu_reg_val PC (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) 15 (snd (fst (get_curr_win () s2))))))))))))"
     using a1 by (metis (no_types) get_curr_win2_low_equal write_cpu_low_equal write_reg_low_equal)
 qed
 
 lemma jmpl_instr_low_equal_sub1: 
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (write_cpu (get_addr (snd instr) (snd (fst (get_curr_win () s2)))) nPC
   (snd (fst (write_cpu (cpu_reg_val nPC 
   (snd (fst (write_reg (cpu_reg_val PC (snd (fst (get_curr_win () s1))))
   (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
   (snd (fst (get_curr_win () s1)))))))
   PC (snd (fst (write_reg (cpu_reg_val PC (snd (fst (get_curr_win () s1))))
   (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
   (snd (fst (get_curr_win () s1))))))))))) \<and>
 t2 = snd (fst (write_cpu (get_addr (snd instr) (snd (fst (get_curr_win () s2)))) nPC
   (snd (fst (write_cpu (cpu_reg_val nPC
   (snd (fst (write_reg (cpu_reg_val PC (snd (fst (get_curr_win () s2))))
   (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
   (snd (fst (get_curr_win () s2)))))))
   PC (snd (fst (write_reg (cpu_reg_val PC (snd (fst (get_curr_win () s2))))
   (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
   (snd (fst (get_curr_win () s2)))))))))))"
 shows "low_equal t1 t2"
 proof -
   from a1 have f1: "low_equal (snd (fst (get_curr_win () s1))) (snd (fst (get_curr_win () s2)))"
   using get_curr_win2_low_equal by blast
   then have f2: "(cpu_reg_val PC (snd (fst (get_curr_win () s1)))) =
     (cpu_reg_val PC (snd (fst (get_curr_win () s2))))"
   using cpu_reg_val_low_equal by blast
   then have f3: "low_equal 
     (snd (fst (write_reg (cpu_reg_val PC (snd (fst (get_curr_win () s1))))
     (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
     (snd (fst (get_curr_win () s1))))))
     (snd (fst (write_reg (cpu_reg_val PC (snd (fst (get_curr_win () s2))))
     (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
     (snd (fst (get_curr_win () s2))))))"
   using f1 write_reg_low_equal by fastforce
   then have "(cpu_reg_val nPC 
     (snd (fst (write_reg (cpu_reg_val PC (snd (fst (get_curr_win () s1))))
     (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
     (snd (fst (get_curr_win () s1))))))) =
     (cpu_reg_val nPC
     (snd (fst (write_reg (cpu_reg_val PC (snd (fst (get_curr_win () s2))))
     (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
     (snd (fst (get_curr_win () s2)))))))"
   using cpu_reg_val_low_equal by auto
   then have f4: "low_equal
     (snd (fst (write_cpu (cpu_reg_val nPC 
     (snd (fst (write_reg (cpu_reg_val PC (snd (fst (get_curr_win () s1))))
     (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
     (snd (fst (get_curr_win () s1)))))))
     PC (snd (fst (write_reg (cpu_reg_val PC (snd (fst (get_curr_win () s1))))
     (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
     (snd (fst (get_curr_win () s1)))))))))
     (snd (fst (write_cpu (cpu_reg_val nPC
     (snd (fst (write_reg (cpu_reg_val PC (snd (fst (get_curr_win () s2))))
     (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
     (snd (fst (get_curr_win () s2)))))))
     PC (snd (fst (write_reg (cpu_reg_val PC (snd (fst (get_curr_win () s2))))
     (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! 3))
     (snd (fst (get_curr_win () s2)))))))))"
   using f3 write_cpu_low_equal by fastforce
   then show ?thesis using write_cpu_low_equal
   using assms by blast  
 qed
 
 lemma jmpl_instr_low_equal_sub2:
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (write_cpu (get_addr (snd instr) (snd (fst (get_curr_win () s2)))) nPC
   (snd (fst (write_cpu (cpu_reg_val nPC
   (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0
   (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s2))) 0
   (snd (fst (get_curr_win () s1))))))) PC (snd (fst (write_reg
   (user_reg_val (fst (fst (get_curr_win () s2))) 0
   (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s2))) 0
   (snd (fst (get_curr_win () s1))))))))))) \<and>
 t2 = snd (fst (write_cpu (get_addr (snd instr) (snd (fst (get_curr_win () s2)))) nPC
   (snd (fst (write_cpu (cpu_reg_val nPC (snd (fst (write_reg
   (user_reg_val (fst (fst (get_curr_win () s2))) 0
   (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) 0
   (snd (fst (get_curr_win () s2))))))) PC (snd (fst (write_reg
   (user_reg_val (fst (fst (get_curr_win () s2))) 0
   (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) 0
   (snd (fst (get_curr_win () s2)))))))))))"
 shows "low_equal t1 t2"
 proof -
   from a1 have f1: "low_equal (snd (fst (get_curr_win () s1))) (snd (fst (get_curr_win () s2)))"
   using get_curr_win2_low_equal by blast
   then have f2: "(user_reg_val (fst (fst (get_curr_win () s2))) 0
     (snd (fst (get_curr_win () s1)))) = 
     (user_reg_val (fst (fst (get_curr_win () s2))) 0
     (snd (fst (get_curr_win () s2))))"
   using user_reg_val_low_equal by blast
   then have f3: "low_equal 
     (snd (fst (write_reg
     (user_reg_val (fst (fst (get_curr_win () s2))) 0
     (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s2))) 0
     (snd (fst (get_curr_win () s1))))))
     (snd (fst (write_reg
     (user_reg_val (fst (fst (get_curr_win () s2))) 0
     (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) 0
     (snd (fst (get_curr_win () s2))))))"
   using f1 write_reg_low_equal by fastforce
   then have "(cpu_reg_val nPC
     (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0
     (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s2))) 0
     (snd (fst (get_curr_win () s1))))))) = 
     (cpu_reg_val nPC (snd (fst (write_reg
     (user_reg_val (fst (fst (get_curr_win () s2))) 0
     (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) 0
     (snd (fst (get_curr_win () s2)))))))"
   using cpu_reg_val_low_equal by blast
   then have "low_equal 
     (snd (fst (write_cpu (cpu_reg_val nPC
     (snd (fst (write_reg (user_reg_val (fst (fst (get_curr_win () s2))) 0
     (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s2))) 0
     (snd (fst (get_curr_win () s1))))))) PC (snd (fst (write_reg
     (user_reg_val (fst (fst (get_curr_win () s2))) 0
     (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s2))) 0
     (snd (fst (get_curr_win () s1)))))))))
     (snd (fst (write_cpu (cpu_reg_val nPC (snd (fst (write_reg
     (user_reg_val (fst (fst (get_curr_win () s2))) 0
     (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) 0
     (snd (fst (get_curr_win () s2))))))) PC (snd (fst (write_reg
     (user_reg_val (fst (fst (get_curr_win () s2))) 0
     (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) 0
     (snd (fst (get_curr_win () s2)))))))))"
   using f1 f2 f3 write_cpu_low_equal by fastforce
   then show ?thesis 
   using write_cpu_low_equal
   using assms by blast 
 qed
 
 lemma jmpl_instr_low_equal:
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (jmpl_instr instr s1)) \<and> t2 = snd (fst (jmpl_instr instr s2))"
 shows "low_equal t1 t2"
 using a1
 apply (simp add: jmpl_instr_def)
 apply (simp add: Let_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 apply auto
    apply (simp add: raise_trap_def add_trap_set_def simpler_modify_def)
    apply (simp add: get_curr_win_traps_low_equal)
   apply (simp add: get_addr2_low_equal)
  apply (simp add: get_addr2_low_equal)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 apply (simp_all add: get_addr2_low_equal)
 apply (simp_all add: get_curr_win_low_equal)
 apply (case_tac "get_operand_w5 (snd instr ! 3) \<noteq> 0")
 apply auto
  using jmpl_instr_low_equal_sub1 apply blast
 apply (simp_all add: get_curr_win_low_equal)
 using jmpl_instr_low_equal_sub2 by blast
 
 lemma rett_instr_low_equal:
 assumes a1: "low_equal s1 s2 \<and>
 \<not> snd (rett_instr instr s1) \<and>
 \<not> snd (rett_instr instr s2) \<and>
 ((ucast (get_S (cpu_reg_val PSR s1)))::word1) = 0 \<and>
 ((ucast (get_S (cpu_reg_val PSR s2)))::word1) = 0 \<and>
 t1 = snd (fst (rett_instr instr s1)) \<and> t2 = snd (fst (rett_instr instr s2))"
 shows "low_equal t1 t2"
 using a1
 apply (simp add: rett_instr_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
 apply auto
    apply (simp add: raise_trap_def add_trap_set_def simpler_modify_def)
    apply (simp add: return_def)
    using mod_trap_low_equal traps_low_equal apply fastforce
   using cpu_reg_val_low_equal apply fastforce
  using cpu_reg_val_low_equal apply fastforce
 apply (simp add: bind_def h1_def h2_def Let_def)
 by (simp add: case_prod_unfold fail_def)
 
 lemma read_state_reg_low_equal:
 assumes a1: "low_equal s1 s2 \<and>
 ((ucast (get_S (cpu_reg_val PSR s1)))::word1) = 0 \<and>
 ((ucast (get_S (cpu_reg_val PSR s2)))::word1) = 0 \<and>
 t1 = snd (fst (read_state_reg_instr instr s1)) \<and> 
 t2 = snd (fst (read_state_reg_instr instr s2))"
 shows "low_equal t1 t2"
 proof (cases "(fst instr \<in> {sreg_type RDPSR,sreg_type RDWIM,sreg_type RDTBR} \<or> 
         (fst instr = sreg_type RDASR \<and> privileged_ASR (get_operand_w5 ((snd instr)!0))))")
   case True   
   then have "(fst instr \<in> {sreg_type RDPSR,sreg_type RDWIM,sreg_type RDTBR} \<or> 
         (fst instr = sreg_type RDASR \<and> privileged_ASR (get_operand_w5 ((snd instr)!0))))
         \<and> ((ucast (get_S (cpu_reg_val PSR (snd (fst (get_curr_win () s1))))))::word1) = 0
         \<and> ((ucast (get_S (cpu_reg_val PSR (snd (fst (get_curr_win () s2))))))::word1) = 0"
     by (metis assms get_curr_win_privilege)
   then show ?thesis using a1
   apply (simp add: read_state_reg_instr_def)
   apply (simp add: Let_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   apply (simp add: case_prod_unfold)
   apply (simp add: raise_trap_def add_trap_set_def simpler_modify_def)
   apply clarsimp
   using get_curr_win_traps_low_equal
   by auto  
 next
   case False
   then have f1: "\<not>((fst instr = sreg_type RDPSR \<or>
                     fst instr = sreg_type RDWIM \<or>
                     fst instr = sreg_type RDTBR \<or>
                     fst instr = sreg_type RDASR \<and> privileged_ASR (get_operand_w5 (snd instr ! 0))))"
     by blast 
   then show ?thesis 
   proof (cases "illegal_instruction_ASR (get_operand_w5 ((snd instr)!0))")
     case True
     then show ?thesis using a1 f1
     apply read_state_reg_instr_privilege_proof
     by (simp add: illegal_instruction_ASR_def)    
   next
     case False
     then have f2: "\<not>(illegal_instruction_ASR (get_operand_w5 ((snd instr)!0)))" 
       by auto
     then show ?thesis 
     proof (cases "(get_operand_w5 ((snd instr)!1)) \<noteq> 0")
       case True
       then have f3: "(get_operand_w5 ((snd instr)!1)) \<noteq> 0" 
         by auto
       then show ?thesis 
       proof (cases "fst instr = sreg_type RDY")
         case True
         then show ?thesis using a1 f1 f2 f3
         apply (simp add: read_state_reg_instr_def)
         apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
         apply (simp add: case_prod_unfold)
         apply (auto simp add: get_curr_win_low_equal)
         using cpu_reg_val_low_equal get_curr_win2_low_equal write_reg_low_equal
         proof -
           assume "low_equal s1 s2"
           then have "low_equal (snd (fst (get_curr_win () s1))) (snd (fst (get_curr_win () s2)))"
             by (meson get_curr_win2_low_equal)
           then show "low_equal (snd (fst (write_reg (cpu_reg_val Y (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))))) (snd (fst (write_reg (cpu_reg_val Y (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))))))"
             using cpu_reg_val_low_equal write_reg_low_equal by fastforce
         qed
       next
         case False
         then have f4: "\<not>(fst instr = sreg_type RDY)" by auto
         then show ?thesis 
         proof (cases "fst instr = sreg_type RDASR")
           case True
           then show ?thesis using a1 f1 f2 f3 f4
           apply read_state_reg_instr_privilege_proof
           apply (clarsimp simp add: get_curr_win_low_equal)
           using cpu_reg_val_low_equal get_curr_win2_low_equal write_reg_low_equal
           proof -
             assume a1: "low_equal s1 s2"
             then have "cpu_reg_val (ASR (get_operand_w5 (snd instr ! 0))) (snd (fst (get_curr_win () s1))) = cpu_reg_val (ASR (get_operand_w5 (snd instr ! 0))) (snd (fst (get_curr_win () s2)))"
               by (meson cpu_reg_val_low_equal get_curr_win2_low_equal)
             then show "low_equal (snd (fst (write_reg (cpu_reg_val (ASR (get_operand_w5 (snd instr ! 0))) (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))))) (snd (fst (write_reg (cpu_reg_val (ASR (get_operand_w5 (snd instr ! 0))) (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))))))"
               using a1 by (metis (no_types) get_curr_win2_low_equal write_reg_low_equal)
           qed
         next
           case False
           then have f5: "\<not>(fst instr = sreg_type RDASR)" by auto
           then show ?thesis using a1 f1 f2 f3 f4 f5
           apply read_state_reg_instr_privilege_proof
           apply (clarsimp simp add: get_curr_win_low_equal)
           using cpu_reg_val_low_equal get_curr_win2_low_equal write_reg_low_equal
           proof -
             assume a1: "low_equal s1 s2"
             assume a2: "t1 = snd (fst (write_reg (cpu_reg_val TBR (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))))"
             assume "t2 = snd (fst (write_reg (cpu_reg_val TBR (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2)))))"
             have "\<forall>s. \<not> low_equal (snd (fst (get_curr_win () s1))) s \<or> snd (fst (write_reg (cpu_reg_val TBR s) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))))) = t1"
               using a2 by (simp add: cpu_reg_val_low_equal)
             then show "low_equal (snd (fst (write_reg (cpu_reg_val TBR (snd (fst (get_curr_win () s1)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1)))))) (snd (fst (write_reg (cpu_reg_val TBR (snd (fst (get_curr_win () s2)))) (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))))))"
               using a2 a1 by (metis (no_types) get_curr_win2_low_equal write_reg_low_equal)
           qed
         qed
       qed
     next
       case False
       then show ?thesis using a1 f1 f2
       apply (simp add: read_state_reg_instr_def)
       apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
       apply (simp add: return_def) 
       apply clarsimp
       apply (simp add: case_prod_unfold)
       using get_curr_win2_low_equal by auto
     qed
   qed
 qed
 
 lemma get_s_get_curr_win:
 assumes a1: "low_equal s1 s2"
 shows "get_S (cpu_reg_val PSR (snd (fst (get_curr_win () s1)))) =
 get_S (cpu_reg_val PSR (snd (fst (get_curr_win () s2))))"
 proof - 
   from a1 have "low_equal (snd (fst (get_curr_win () s1))) 
     (snd (fst (get_curr_win () s2)))"
   using get_curr_win2_low_equal by blast
   then show ?thesis
   using cpu_reg_val_low_equal
   by fastforce  
 qed
 
 lemma write_state_reg_low_equal:
 assumes a1: "low_equal s1 s2 \<and>
 ((ucast (get_S (cpu_reg_val PSR s1)))::word1) = 0 \<and>
 ((ucast (get_S (cpu_reg_val PSR s2)))::word1) = 0 \<and>
 t1 = snd (fst (write_state_reg_instr instr s1)) \<and>
 t2 = snd (fst (write_state_reg_instr instr s2))"
 shows "low_equal t1 t2"
 proof (cases "fst instr = sreg_type WRY")
   case True
   then show ?thesis using a1
   apply write_state_reg_instr_privilege_proof
   apply (simp add: simpler_modify_def)
   apply (simp add: delayed_pool_add_def DELAYNUM_def)
   apply (auto simp add: get_curr_win_low_equal)
   using get_curr_win2_low_equal cpu_reg_mod_low_equal
   user_reg_val_low_equal get_operand2_low_equal
   proof -
     assume a1: "low_equal s1 s2"
     assume "t2 = cpu_reg_mod (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) XOR get_operand2 (snd instr) (snd (fst (get_curr_win () s2)))) Y (snd (fst (get_curr_win () s2)))"
     assume "t1 = cpu_reg_mod (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) XOR get_operand2 (snd instr) (snd (fst (get_curr_win () s1)))) Y (snd (fst (get_curr_win () s1)))"
     have f2: "low_equal (snd (fst (get_curr_win () s1))) (snd (fst (get_curr_win () s2)))"
       using a1 by (meson get_curr_win2_low_equal)
     then have f3: "\<And>w wa. user_reg_val w wa (snd (fst (get_curr_win () s2))) = user_reg_val w wa (snd (fst (get_curr_win () s1)))"
       by (simp add: user_reg_val_low_equal)
     have "\<And>is. get_operand2 is (snd (fst (get_curr_win () s2))) = get_operand2 is (snd (fst (get_curr_win () s1)))"
       using f2 by (simp add: get_operand2_low_equal)
     then show "low_equal (cpu_reg_mod (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) XOR get_operand2 (snd instr) (snd (fst (get_curr_win () s1)))) Y (snd (fst (get_curr_win () s1)))) (cpu_reg_mod (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) XOR get_operand2 (snd instr) (snd (fst (get_curr_win () s2)))) Y (snd (fst (get_curr_win () s2))))"
       using f3 f2 by (metis cpu_reg_mod_low_equal)
   qed
 next
   case False
   then have f1: "\<not>(fst instr = sreg_type WRY)" by auto
   then show ?thesis
   proof (cases "fst instr = sreg_type WRASR")
     case True
     then have f1_1: "fst instr = sreg_type WRASR" by auto
     then show ?thesis
     proof (cases "privileged_ASR (get_operand_w5 (snd instr ! 3)) \<and>
                   get_S (cpu_reg_val PSR (snd (fst (get_curr_win () s2)))) = 0")
       case True
       then show ?thesis using a1 f1 f1_1
       apply write_state_reg_instr_privilege_proof
       apply (clarsimp simp add: get_s_get_curr_win)
       apply (simp add: raise_trap_def add_trap_set_def simpler_modify_def)
       apply (clarsimp simp add: get_curr_win3_low_equal)
       using traps_low_equal mod_trap_low_equal get_curr_win2_low_equal
       by fastforce
     next
       case False
       then have f1_2: "\<not> (privileged_ASR (get_operand_w5 (snd instr ! 3)) \<and>
       get_S (cpu_reg_val PSR (snd (fst (get_curr_win () s2)))) = 0)"
       by auto
       then show ?thesis
       proof (cases "illegal_instruction_ASR (get_operand_w5 (snd instr ! 3))")
         case True
         then show ?thesis using a1 f1 f1_1 f1_2
         apply write_state_reg_instr_privilege_proof
         apply (clarsimp simp add: get_s_get_curr_win)
         apply auto
          apply (simp add: raise_trap_def add_trap_set_def simpler_modify_def)
          apply (clarsimp simp add: get_curr_win3_low_equal)
          using traps_low_equal mod_trap_low_equal get_curr_win2_low_equal
          apply fastforce
         apply (simp add: raise_trap_def add_trap_set_def simpler_modify_def)
         apply (clarsimp simp add: get_curr_win3_low_equal)
         using traps_low_equal mod_trap_low_equal get_curr_win2_low_equal
         by fastforce
       next
         case False
         then show ?thesis using a1 f1 f1_1 f1_2
         apply write_state_reg_instr_privilege_proof
         apply (clarsimp simp add: get_s_get_curr_win)
         apply auto
          apply (simp add: simpler_modify_def)
          apply (simp add: delayed_pool_add_def DELAYNUM_def)
          apply (auto simp add: get_curr_win_low_equal)      
          using get_curr_win2_low_equal cpu_reg_mod_low_equal
          user_reg_val_low_equal get_operand2_low_equal
          proof -
            assume a1: "low_equal s1 s2"
            assume "t2 = cpu_reg_mod (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) XOR get_operand2 (snd instr) (snd (fst (get_curr_win () s2)))) (ASR (get_operand_w5 (snd instr ! 3))) (snd (fst (get_curr_win () s2)))"
            assume "t1 = cpu_reg_mod (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) XOR get_operand2 (snd instr) (snd (fst (get_curr_win () s1)))) (ASR (get_operand_w5 (snd instr ! 3))) (snd (fst (get_curr_win () s1)))"
            have "low_equal (snd (fst (get_curr_win () s1))) (snd (fst (get_curr_win () s2)))"
             using a1 by (meson get_curr_win2_low_equal)
            then show "low_equal (cpu_reg_mod (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s1))) XOR get_operand2 (snd instr) (snd (fst (get_curr_win () s1)))) (ASR (get_operand_w5 (snd instr ! 3))) (snd (fst (get_curr_win () s1)))) (cpu_reg_mod (user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0)) (snd (fst (get_curr_win () s2))) XOR get_operand2 (snd instr) (snd (fst (get_curr_win () s2)))) (ASR (get_operand_w5 (snd instr ! 3))) (snd (fst (get_curr_win () s2))))"
             using cpu_reg_mod_low_equal get_operand2_low_equal user_reg_val_low_equal by fastforce
          next
            assume f1: "\<not> illegal_instruction_ASR (get_operand_w5 (snd instr ! 3))"
            assume f2: "fst instr = sreg_type WRASR"
            assume f3: "snd (fst (write_state_reg_instr instr s1)) =
     snd (fst (modify
                (delayed_pool_add
                  (DELAYNUM,
                   user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                    (snd (fst (get_curr_win () s1))) XOR
                   get_operand2 (snd instr) (snd (fst (get_curr_win () s1))),
                   ASR (get_operand_w5 (snd instr ! 3))))
                (snd (fst (get_curr_win () s1))))) "
            assume f4: "snd (fst (write_state_reg_instr instr s2)) =
     snd (fst (modify
                (delayed_pool_add
                  (DELAYNUM,
                   user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                    (snd (fst (get_curr_win () s2))) XOR
                   get_operand2 (snd instr) (snd (fst (get_curr_win () s2))),
                   ASR (get_operand_w5 (snd instr ! 3))))
                (snd (fst (get_curr_win () s2)))))"
            assume f5: "low_equal s1 s2"
            assume f6: "ucast (get_S (cpu_reg_val PSR s1)) = 0"
            assume f7: "ucast (get_S (cpu_reg_val PSR s2)) = 0"
            assume f8: "t1 = snd (fst (modify
                     (delayed_pool_add
                       (DELAYNUM,
                        user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                         (snd (fst (get_curr_win () s1))) XOR
                        get_operand2 (snd instr) (snd (fst (get_curr_win () s1))),
                        ASR (get_operand_w5 (snd instr ! 3))))
                     (snd (fst (get_curr_win () s1)))))"
            assume f9: "t2 = snd (fst (modify
                     (delayed_pool_add
                       (DELAYNUM,
                        user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                         (snd (fst (get_curr_win () s2))) XOR
                        get_operand2 (snd instr) (snd (fst (get_curr_win () s2))),
                        ASR (get_operand_w5 (snd instr ! 3))))
                     (snd (fst (get_curr_win () s2)))))"
            assume f10: "get_S (cpu_reg_val PSR (snd (fst (get_curr_win () s2)))) \<noteq> 0"
            assume f11: "(\<And>s1 s2 t1 t2.
             low_equal s1 s2 \<Longrightarrow>
             t1 = snd (fst (get_curr_win () s1)) \<Longrightarrow> t2 = snd (fst (get_curr_win () s2)) \<Longrightarrow> low_equal t1 t2)"
            assume f12: "(\<And>s1 s2 t1 w cr t2.
             low_equal s1 s2 \<and> t1 = cpu_reg_mod w cr s1 \<and> t2 = cpu_reg_mod w cr s2 \<Longrightarrow> low_equal t1 t2)"
            assume f13: "(\<And>s1 s2 win ur. low_equal s1 s2 \<Longrightarrow> user_reg_val win ur s1 = user_reg_val win ur s2)"
            assume f14: "(\<And>s1 s2 op_list. low_equal s1 s2 \<Longrightarrow> get_operand2 op_list s1 = get_operand2 op_list s2)"
            show "low_equal
      (snd (fst (modify
                  (delayed_pool_add
                    (DELAYNUM,
                     user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                      (snd (fst (get_curr_win () s1))) XOR
                     get_operand2 (snd instr) (snd (fst (get_curr_win () s1))),
                     ASR (get_operand_w5 (snd instr ! 3))))
                  (snd (fst (get_curr_win () s1))))))
      (snd (fst (modify
                  (delayed_pool_add
                    (DELAYNUM,
                     user_reg_val (fst (fst (get_curr_win () s2))) (get_operand_w5 (snd instr ! Suc 0))
                      (snd (fst (get_curr_win () s2))) XOR
                     get_operand2 (snd instr) (snd (fst (get_curr_win () s2))),
                     ASR (get_operand_w5 (snd instr ! 3))))
                  (snd (fst (get_curr_win () s2))))))"
            using f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14
            using Sparc_Properties.ucast_0 assms get_curr_win_privilege by blast            
          qed
       qed
     qed
   next
     case False
     then have f2: "\<not>(fst instr = sreg_type WRASR)" by auto
     have f3: "get_S (cpu_reg_val PSR (snd (fst (get_curr_win () s1)))) = 0 \<and>
       get_S (cpu_reg_val PSR (snd (fst (get_curr_win () s2)))) = 0"
       using get_curr_win_privilege a1 by (metis ucast_id)
     then show ?thesis 
     proof (cases "fst instr = sreg_type WRPSR")
       case True
       then show ?thesis using a1 f1 f2 f3
       apply write_state_reg_instr_privilege_proof
       apply (simp add: raise_trap_def add_trap_set_def simpler_modify_def)
       apply (clarsimp simp add: get_curr_win3_low_equal)
       using traps_low_equal mod_trap_low_equal get_curr_win2_low_equal
       by fastforce      
     next
       case False
       then have f4: "\<not>(fst instr = sreg_type WRPSR)" by auto
       then show ?thesis 
       proof (cases "fst instr = sreg_type WRWIM")  
         case True
         then show ?thesis using a1 f1 f2 f3 f4
         apply write_state_reg_instr_privilege_proof
         apply (simp add: raise_trap_def add_trap_set_def simpler_modify_def)
         apply (clarsimp simp add: get_curr_win3_low_equal)
         using traps_low_equal mod_trap_low_equal get_curr_win2_low_equal
         by fastforce 
       next
         case False
         then have f5: "\<not>(fst instr = sreg_type WRWIM)" by auto
         then show ?thesis using a1 f1 f2 f3 f4 f5
         apply write_state_reg_instr_privilege_proof
         apply (simp add: raise_trap_def add_trap_set_def simpler_modify_def)
         apply (clarsimp simp add: get_curr_win3_low_equal)
         using traps_low_equal mod_trap_low_equal get_curr_win2_low_equal
         by fastforce        
       qed
     qed
   qed
 qed
 
 lemma flush_instr_low_equal:
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (flush_instr instr s1)) \<and>
 t2 = snd (fst (flush_instr instr s2))"
 shows "low_equal t1 t2"
 using a1
 apply (simp add: flush_instr_def)
 apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def simpler_modify_def)
 apply (simp add: flush_cache_all_def)
 apply (simp add: low_equal_def)
 apply (simp add: user_accessible_def)
 apply (simp add: mem_equal_def)
 by auto
 
 lemma branch_instr_sub1_low_equal:
 assumes a1: "low_equal s1 s2"
 shows "branch_instr_sub1 instr_name s1 = branch_instr_sub1 instr_name s2"
 using a1 apply (simp add: branch_instr_sub1_def)
 by (simp add: low_equal_def)
 
 lemma set_annul_low_equal:
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (set_annul True s1)) \<and>
 t2 = snd (fst (set_annul True s2))"
 shows "low_equal t1 t2"
 using a1 apply (simp add: set_annul_def)
 apply (simp add: simpler_modify_def annul_mod_def)
 using state_var2_low_equal state_var_low_equal 
 by fastforce
 
 lemma branch_instr_low_equal_sub0:
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (write_cpu (cpu_reg_val PC s2 +
   sign_ext24 (ucast (get_operand_w22 (snd instr ! Suc 0)) << 2))
   nPC (snd (fst (write_cpu (cpu_reg_val nPC s2) PC s1))))) \<and>
 t2 = snd (fst (write_cpu (cpu_reg_val PC s2 +
   sign_ext24 (ucast (get_operand_w22 (snd instr ! Suc 0)) << 2))
   nPC (snd (fst (write_cpu (cpu_reg_val nPC s2) PC s2)))))"
 shows "low_equal t1 t2"
 proof -
   from a1 have "low_equal
     (snd (fst (write_cpu (cpu_reg_val nPC s2) PC s1)))
     (snd (fst (write_cpu (cpu_reg_val nPC s2) PC s2)))"
   using write_cpu_low_equal by blast
   then show ?thesis
   using a1 write_cpu_low_equal by blast
 qed
 
 lemma branch_instr_low_equal_sub1:
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (set_annul True (snd (fst (write_cpu
   (cpu_reg_val PC s2 + sign_ext24
   (ucast (get_operand_w22 (snd instr ! Suc 0)) << 2))
   nPC (snd (fst (write_cpu (cpu_reg_val nPC s2) PC s1)))))))) \<and>
 t2 = snd (fst (set_annul True (snd (fst (write_cpu
   (cpu_reg_val PC s2 + sign_ext24
   (ucast (get_operand_w22 (snd instr ! Suc 0)) << 2))
   nPC (snd (fst (write_cpu (cpu_reg_val nPC s2) PC s2))))))))"
 shows "low_equal t1 t2"
 proof -
   from a1 have "low_equal 
     (snd (fst (write_cpu
     (cpu_reg_val PC s2 + sign_ext24
     (ucast (get_operand_w22 (snd instr ! Suc 0)) << 2))
     nPC (snd (fst (write_cpu (cpu_reg_val nPC s2) PC s1))))))
     (snd (fst (write_cpu
     (cpu_reg_val PC s2 + sign_ext24
     (ucast (get_operand_w22 (snd instr ! Suc 0)) << 2))
     nPC (snd (fst (write_cpu (cpu_reg_val nPC s2) PC s2))))))"
   using branch_instr_low_equal_sub0 by blast  
   then show ?thesis using a1
   using set_annul_low_equal by blast  
 qed
 
 lemma branch_instr_low_equal_sub2:
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (set_annul True
   (snd (fst (write_cpu (cpu_reg_val nPC s2 + 4) nPC
   (snd (fst (write_cpu (cpu_reg_val nPC s2) PC s1)))))))) \<and>
 t2 = snd (fst (set_annul True
   (snd (fst (write_cpu (cpu_reg_val nPC s2 + 4) nPC
    (snd (fst (write_cpu (cpu_reg_val nPC s2) PC s2))))))))"
 shows "low_equal t1 t2"
 proof -
   from a1 have "low_equal
     (snd (fst (write_cpu (cpu_reg_val nPC s2) PC s1)))
     (snd (fst (write_cpu (cpu_reg_val nPC s2) PC s2)))"
   using write_cpu_low_equal by blast
   then have "low_equal 
     (snd (fst (write_cpu (cpu_reg_val nPC s2 + 4) nPC
     (snd (fst (write_cpu (cpu_reg_val nPC s2) PC s1))))))
     (snd (fst (write_cpu (cpu_reg_val nPC s2 + 4) nPC
     (snd (fst (write_cpu (cpu_reg_val nPC s2) PC s2))))))"
   using write_cpu_low_equal by blast
   then show ?thesis using a1
   using set_annul_low_equal by blast
 qed
 
 lemma branch_instr_low_equal:
 assumes a1: "low_equal s1 s2 \<and>
 t1 = snd (fst (branch_instr instr s1)) \<and>
 t2 = snd (fst (branch_instr instr s2))"
 shows "low_equal t1 t2"
 using a1 
 apply (simp add: branch_instr_def)
 apply (simp add: Let_def simpler_gets_def bind_def h1_def h2_def)
 apply (simp add: case_prod_unfold return_def)
 apply clarsimp
 apply (simp add: branch_instr_sub1_low_equal)
 apply (simp_all add: cpu_reg_val_low_equal)
 apply (cases "branch_instr_sub1 (fst instr) s2 = 1")
  apply clarsimp
  apply (simp add: bind_def h1_def h2_def Let_def)
  apply (simp_all add: cpu_reg_val_low_equal)
  apply (simp add: case_prod_unfold)
  apply (cases "fst instr = bicc_type BA \<and> get_operand_flag (snd instr ! 0) = 1")
   apply clarsimp
   using branch_instr_low_equal_sub1 apply blast
  apply clarsimp
  apply (simp add: return_def)
  using branch_instr_low_equal_sub0 apply fastforce
 apply (simp add: bind_def h1_def h2_def Let_def)
 apply (simp add: case_prod_unfold)
 apply (cases "get_operand_flag (snd instr ! 0) = 1")
  apply clarsimp
  apply (simp_all add: cpu_reg_val_low_equal)
  using branch_instr_low_equal_sub2 apply metis
 apply (simp add: return_def)
 using write_cpu_low_equal by metis
 
 lemma dispath_instr_low_equal:
 assumes a1: "low_equal s1 s2 \<and>
 ((ucast (get_S (cpu_reg_val PSR s1)))::word1) = 0 \<and>
 ((ucast (get_S (cpu_reg_val PSR s2)))::word1) = 0 \<and>
 \<not> snd (dispatch_instruction instr s1) \<and>
 \<not> snd (dispatch_instruction instr s2) \<and>
 t1 = (snd (fst (dispatch_instruction instr s1))) \<and>
 t2 = (snd (fst (dispatch_instruction instr s2)))"
 shows "low_equal t1 t2"
 proof (cases "get_trap_set s1 = {}")
   case True
   then have f_no_traps: "get_trap_set s1 = {} \<and> get_trap_set s2 = {}"
     using a1 by (simp add: low_equal_def get_trap_set_def)
   then show ?thesis
   proof (cases "fst instr \<in> {load_store_type LDSB,load_store_type LDUB,
         load_store_type LDUBA,load_store_type LDUH,load_store_type LD,
         load_store_type LDA,load_store_type LDD}")
     case True
     then show ?thesis using a1 f_no_traps
     apply dispath_instr_privilege_proof
     by (blast intro: load_instr_low_equal)
   next
     case False
     then have f1: "fst instr \<notin> {load_store_type LDSB, load_store_type LDUB, 
       load_store_type LDUBA, load_store_type LDUH,
       load_store_type LD, load_store_type LDA, load_store_type LDD}" 
       by auto
     then show ?thesis 
     proof (cases "fst instr \<in> {load_store_type STB,load_store_type STH,
         load_store_type ST,load_store_type STA,load_store_type STD}")
       case True
       then show ?thesis using a1 f_no_traps f1
       apply dispath_instr_privilege_proof
       using store_instr_low_equal by blast      
     next
       case False
       then have f2: "\<not>(fst instr \<in> {load_store_type STB,load_store_type STH,
         load_store_type ST,load_store_type STA,load_store_type STD})"
         by auto
       then show ?thesis 
       proof (cases "fst instr \<in> {sethi_type SETHI}")
         case True
         then show ?thesis using a1 f_no_traps f1 f2
         apply dispath_instr_privilege_proof
         by (auto intro: sethi_low_equal)        
       next
         case False
         then have f3: "\<not>(fst instr \<in> {sethi_type SETHI})"
           by auto
         then show ?thesis 
         proof (cases "fst instr \<in> {nop_type NOP}")
           case True
           then show ?thesis using a1 f_no_traps f1 f2 f3
           apply dispath_instr_privilege_proof
           by (auto intro: nop_low_equal)
         next
           case False
           then have f4: "\<not>(fst instr \<in> {nop_type NOP})" 
             by auto
           then show ?thesis 
           proof (cases "fst instr \<in> {logic_type ANDs,logic_type ANDcc,logic_type ANDN,
             logic_type ANDNcc,logic_type ORs,logic_type ORcc,logic_type ORN,
             logic_type XORs,logic_type XNOR}")
             case True
             then show ?thesis using a1 f_no_traps f1 f2 f3 f4
             apply dispath_instr_privilege_proof
             using logical_instr_low_equal by blast
           next
             case False
             then have f5: "\<not>(fst instr \<in> {logic_type ANDs,logic_type ANDcc,logic_type ANDN,
             logic_type ANDNcc,logic_type ORs,logic_type ORcc,logic_type ORN,
             logic_type XORs,logic_type XNOR})"
               by auto
             then show ?thesis 
             proof (cases "fst instr \<in> {shift_type SLL,shift_type SRL,shift_type SRA}")
               case True
               then show ?thesis using a1 f_no_traps f1 f2 f3 f4 f5 
               apply dispath_instr_privilege_proof
               using shift_instr_low_equal by blast
             next
               case False
               then have f6: "\<not>(fst instr \<in> {shift_type SLL,shift_type SRL,shift_type SRA})"
                 by auto
               then show ?thesis 
               proof (cases "fst instr \<in> {arith_type ADD,arith_type ADDcc,arith_type ADDX}")
                 case True
                 then show ?thesis using a1 f_no_traps f1 f2 f3 f4 f5 f6
                 apply dispath_instr_privilege_proof
                 using add_instr_low_equal by blast
               next
                 case False
                 then have f7: "\<not>(fst instr \<in> {arith_type ADD,arith_type ADDcc,arith_type ADDX})"
                   by auto
                 then show ?thesis
                 proof (cases "fst instr \<in> {arith_type SUB,arith_type SUBcc,arith_type SUBX}")
                   case True
                   then show ?thesis using a1 f_no_traps f1 f2 f3 f4 f5 f6 f7 
                   apply dispath_instr_privilege_proof
                   using sub_instr_low_equal by blast
                 next
                   case False
                   then have f8: "\<not>(fst instr \<in> {arith_type SUB,arith_type SUBcc,arith_type SUBX})"
                     by auto
                   then show ?thesis
                   proof (cases "fst instr \<in> {arith_type UMUL,arith_type SMUL,arith_type SMULcc}")
                     case True
                     then show ?thesis using a1 f_no_traps f1 f2 f3 f4 f5 f6 f7 f8
                     apply dispath_instr_privilege_proof
                     using mul_instr_low_equal by blast
                   next
                     case False
                     then have f9: "\<not>(fst instr \<in> {arith_type UMUL,arith_type SMUL,
                       arith_type SMULcc})"
                       by auto
                     then show ?thesis 
                     proof (cases "fst instr \<in> {arith_type UDIV,arith_type UDIVcc,arith_type SDIV}")
                       case True
                       then show ?thesis using a1 f_no_traps f1 f2 f3 f4 f5 f6 f7 f8 f9
                       apply dispath_instr_privilege_proof
                       using div_instr_low_equal by blast
                     next
                       case False
                       then have f10: "\<not>(fst instr \<in> {arith_type UDIV,
                         arith_type UDIVcc,arith_type SDIV})"
                         by auto
                       then show ?thesis 
                       proof (cases "fst instr \<in> {ctrl_type SAVE,ctrl_type RESTORE}")
                         case True
                         then show ?thesis using a1 f_no_traps f1 f2 f3 f4 f5 f6 f7 f8 f9 f10
                         apply dispath_instr_privilege_proof
                         using save_restore_instr_low_equal by blast
                       next
                         case False
                         then have f11: "\<not>(fst instr \<in> {ctrl_type SAVE,ctrl_type RESTORE})"
                           by auto
                         then show ?thesis 
                         proof (cases "fst instr \<in> {call_type CALL}")
                           case True
                           then show ?thesis using a1 f_no_traps f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11
                           apply dispath_instr_privilege_proof
                           using call_instr_low_equal by blast                          
                         next
                           case False
                           then have f12: "\<not>(fst instr \<in> {call_type CALL})" by auto
                           then show ?thesis
                           proof (cases "fst instr \<in> {ctrl_type JMPL}")
                             case True
                             then show ?thesis using a1 f_no_traps f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12
                             apply dispath_instr_privilege_proof
                             using jmpl_instr_low_equal by blast
                           next
                             case False
                             then have f13: "\<not>(fst instr \<in> {ctrl_type JMPL})" by auto
                             then show ?thesis 
                             proof (cases "fst instr \<in> {ctrl_type RETT}")
                               case True
                               then show ?thesis using a1 f_no_traps f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 
                                 f11 f12 f13
                               apply dispath_instr_privilege_proof
                               using rett_instr_low_equal by blast
                             next
                               case False
                               then have f14: "\<not>(fst instr \<in> {ctrl_type RETT})" by auto
                               then show ?thesis 
                               proof (cases "fst instr \<in> {sreg_type RDY,sreg_type RDPSR,
                                 sreg_type RDWIM, sreg_type RDTBR}")
                                 case True
                                 then show ?thesis using a1 f_no_traps f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 
                                   f11 f12 f13 f14
                                 apply dispath_instr_privilege_proof
                                 using read_state_reg_low_equal by blast
                               next
                                 case False
                                 then have f15: "\<not>(fst instr \<in> {sreg_type RDY,sreg_type RDPSR,
                                 sreg_type RDWIM, sreg_type RDTBR})" by auto
                                 then show ?thesis
                                 proof (cases "fst instr \<in> {sreg_type WRY,sreg_type WRPSR,
                                   sreg_type WRWIM, sreg_type WRTBR}")
                                   case True
                                   then show ?thesis using a1 f_no_traps f1 f2 f3 f4 f5 f6 f7 f8 f9 
                                     f10 f11 f12 f13 f14 f15 
                                   apply dispath_instr_privilege_proof
                                   using write_state_reg_low_equal by blast
                                 next
                                   case False
                                   then have f16: "\<not>(fst instr \<in> {sreg_type WRY,sreg_type WRPSR,
                                   sreg_type WRWIM, sreg_type WRTBR})" by auto
                                   then show ?thesis
                                   proof (cases "fst instr \<in> {load_store_type FLUSH}")
                                     case True
                                     then show ?thesis using a1 f_no_traps f1 f2 f3 f4 f5 f6 f7 f8 f9 
                                       f10 f11 f12 f13 f14 f15 f16 
                                     apply dispath_instr_privilege_proof
                                     using flush_instr_low_equal by blast
                                   next
                                     case False
                                     then have f17: "\<not>(fst instr \<in> {load_store_type FLUSH})" by auto
                                     then show ?thesis 
                                     proof (cases "fst instr \<in> {bicc_type BE,bicc_type BNE,
                                       bicc_type BGU,bicc_type BLE,bicc_type BL,bicc_type BGE,
                                       bicc_type BNEG,bicc_type BG,bicc_type BCS,bicc_type BLEU,
                                       bicc_type BCC,bicc_type BA,bicc_type BN}")
                                       case True
                                       then show ?thesis using a1 f_no_traps f1 f2 f3 f4 f5 f6 f7 f8 
                                         f9 f10 f11 f12 f13 f14 f15 f16 f17
                                       apply dispath_instr_privilege_proof
                                       using branch_instr_low_equal by blast
                                     next
                                       case False
                                       then show ?thesis using a1 f_no_traps f1 f2 f3 f4 f5 f6 f7 f8 
                                         f9 f10 f11 f12 f13 f14 f15 f16 f17
                                       apply dispath_instr_privilege_proof
                                       by (simp add: fail_def)
                                     qed
                                   qed
                                 qed
                               qed
                             qed
                           qed
                         qed
                       qed
                     qed
                   qed
                 qed
               qed
             qed
           qed
         qed
       qed
     qed
   qed
 next
   case False
   then have "get_trap_set s1 \<noteq> {} \<and> get_trap_set s2 \<noteq> {}" 
     using a1 by (simp add: low_equal_def get_trap_set_def)
   then show ?thesis using a1
   apply (simp add: dispatch_instruction_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def)
   apply (simp add: Let_def)
   by (simp add: return_def)
 qed
 
 lemma execute_instr_sub1_low_equal:
 assumes a1: "low_equal s1 s2 \<and>
 \<not> snd (execute_instr_sub1 instr s1) \<and>
 \<not> snd (execute_instr_sub1 instr s2) \<and>
 t1 = (snd (fst (execute_instr_sub1 instr s1))) \<and>
 t2 = (snd (fst (execute_instr_sub1 instr s2)))"
 shows "low_equal t1 t2"
 proof (cases "get_trap_set s1 = {}")
   case True
   then have "get_trap_set s1 = {} \<and> get_trap_set s2 = {}"
     using a1 by (simp add: low_equal_def get_trap_set_def)
   then show ?thesis using a1
   apply (simp add: execute_instr_sub1_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   apply (case_tac "fst instr \<noteq> call_type CALL \<and>
                 fst instr \<noteq> ctrl_type RETT \<and>
                 fst instr \<noteq> ctrl_type JMPL \<and>
                 fst instr \<noteq> bicc_type BE \<and>
                 fst instr \<noteq> bicc_type BNE \<and>
                 fst instr \<noteq> bicc_type BGU \<and>
                 fst instr \<noteq> bicc_type BLE \<and>
                 fst instr \<noteq> bicc_type BL \<and>
                 fst instr \<noteq> bicc_type BGE \<and>
                 fst instr \<noteq> bicc_type BNEG \<and>
                 fst instr \<noteq> bicc_type BG \<and>
                 fst instr \<noteq> bicc_type BCS \<and>
                 fst instr \<noteq> bicc_type BLEU \<and>
                 fst instr \<noteq> bicc_type BCC \<and>
                 fst instr \<noteq> bicc_type BA \<and> fst instr \<noteq> bicc_type BN")
    apply clarsimp
    apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
    apply (simp add: case_prod_unfold)
    apply (simp add: low_equal_def)
    apply (simp add: cpu_reg_val_def write_cpu_def cpu_reg_mod_def)
    apply (simp add: simpler_modify_def return_def)
    apply (simp add: user_accessible_mod_cpu_reg mem_equal_mod_cpu_reg)
    apply clarsimp
   by (auto simp add: return_def)
 next
   case False
   then have "get_trap_set s1 \<noteq> {} \<and> get_trap_set s2 \<noteq> {}" 
     using a1 by (simp add: low_equal_def get_trap_set_def)
   then show ?thesis using a1
   apply (simp add: execute_instr_sub1_def)
   apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
   by (simp add: return_def)
 qed
 
 theorem non_interference_step: 
 assumes a1: "((ucast (get_S (cpu_reg_val PSR s1)))::word1) = 0 \<and>
 good_context s1 \<and>
 get_delayed_pool s1 = [] \<and> get_trap_set s1 = {} \<and>
 ((ucast (get_S (cpu_reg_val PSR s2)))::word1) = 0 \<and>
 get_delayed_pool s2 = [] \<and> get_trap_set s2 = {} \<and>
 good_context s2 \<and>
 low_equal s1 s2"
 shows "\<exists>t1 t2. Some t1 = NEXT s1 \<and> Some t2 = NEXT s2 \<and> 
 ((ucast (get_S (cpu_reg_val PSR t1)))::word1) = 0 \<and>
 ((ucast (get_S (cpu_reg_val PSR t2)))::word1) = 0 \<and>
 low_equal t1 t2"
 proof -
   from a1 have "good_context s1 \<and> good_context s2" by auto
   then have "NEXT s1 = Some (snd (fst (execute_instruction () s1))) \<and>
              NEXT s2 = Some (snd (fst (execute_instruction () s2)))"
        by (simp add: single_step)
   then have "\<exists>t1 t2. Some t1 = NEXT s1 \<and> Some t2 = NEXT s2" 
        by auto
   then have f0: "snd (execute_instruction() s1) = False \<and>
              snd (execute_instruction() s2) = False"
        by (auto simp add: NEXT_def case_prod_unfold)
   then have f1: "\<exists>t1 t2. Some t1 = NEXT s1 \<and>
       Some t2 = NEXT s2 \<and>
       ((ucast (get_S (cpu_reg_val PSR t1)))::word1) = 0 \<and>
       ((ucast (get_S (cpu_reg_val PSR t2)))::word1) = 0"
       using a1
       apply (auto simp add: NEXT_def case_prod_unfold)
        by (auto simp add: safe_privilege)
   then show ?thesis 
   proof (cases "exe_mode_val s1")
     case True
     then have f_exe0: "exe_mode_val s1" by auto
     then have f_exe: "exe_mode_val s1 \<and> exe_mode_val s2"
       proof -
         have "low_equal s1 s2" using a1 by auto
         then have "state_var s1 = state_var s2" by (simp add: low_equal_def)
         then have "exe_mode_val s1 = exe_mode_val s2" by (simp add: exe_mode_val_def)
         then show ?thesis using f_exe0 by auto
       qed
     then show ?thesis
     proof (cases "\<exists>e. fetch_instruction (delayed_pool_write s1) = Inl e")
       case True
       then have f_fetch_error: "\<exists>e. fetch_instruction (delayed_pool_write s1) = Inl e" by auto
       then have f_fetch_error2: "(\<exists>e. fetch_instruction (delayed_pool_write s1) = Inl e) \<and> 
                  (\<exists>e. fetch_instruction (delayed_pool_write s2) = Inl e)"
         proof -
           have "cpu_reg s1 = cpu_reg s2" 
             using a1 by (simp add: low_equal_def)
           then have "cpu_reg_val PC s1 = cpu_reg_val PC s2" 
             by (simp add: cpu_reg_val_def)
           then have "cpu_reg_val PC s1 = cpu_reg_val PC s2 \<and>
                      ((ucast (get_S (cpu_reg_val PSR (delayed_pool_write s1))))::word1) = 0 \<and>
                      ((ucast (get_S (cpu_reg_val PSR (delayed_pool_write s2))))::word1) = 0"
             using a1 
             by (auto simp add: empty_delayed_pool_write_privilege)  
           then show ?thesis using a1 f_fetch_error
           apply (simp add: fetch_instruction_def)
           apply (simp add: Let_def ucast_def)         
           apply clarsimp
           apply (case_tac "uint (3 AND cpu_reg_val PC (delayed_pool_write s1)) = 0")
            apply auto
            apply (case_tac "fst (memory_read 8 (cpu_reg_val PC (delayed_pool_write s1)) 
            (delayed_pool_write s1)) = None")
             apply auto
             apply (simp add: case_prod_unfold)
             using a1 apply (auto simp add: mem_read_delayed_write_low_equal)
            apply (simp add: case_prod_unfold)
            using a1 apply (auto simp add: mem_read_delayed_write_low_equal)
           apply (simp add: delayed_pool_write_def)
           by (simp add: Let_def get_delayed_write_def)
         qed
       then show ?thesis 
       proof (cases "exe_mode_val s1")
         case True
         then have "exe_mode_val s1 \<and> exe_mode_val s2" using exe_mode_low_equal a1 by auto
         then show ?thesis using f1
         apply (simp add: NEXT_def execute_instruction_def)
         apply (simp add: bind_def h1_def h2_def Let_def simpler_gets_def)
         using a1 apply clarsimp
         apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
         apply (simp add: simpler_modify_def)
         using f_fetch_error2 apply clarsimp
         apply (simp add: raise_trap_def simpler_modify_def return_def)
         apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
         apply (simp add: return_def simpler_modify_def)
         apply (simp add: raise_trap_def simpler_modify_def return_def)
         apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
         apply (simp add: return_def)
         apply (simp add: delayed_pool_write_def get_delayed_write_def Let_def)
         apply (simp add: low_equal_def)
         apply (simp add: add_trap_set_def)
         apply (simp add: cpu_reg_val_def)
         apply clarsimp
         by (simp add: mem_equal_mod_trap user_accessible_mod_trap)       
       next
         case False
         then have "\<not> (exe_mode_val s1) \<and> \<not> (exe_mode_val s2)" 
           using exe_mode_low_equal a1 by auto
         then show ?thesis using f1
         apply (simp add: NEXT_def execute_instruction_def)
         apply (simp add: bind_def h1_def h2_def Let_def simpler_gets_def)
         using a1 apply clarsimp
         apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
         by (simp add: return_def)
       qed
     next
       case False
       then have f_fetch_suc: "(\<exists>v. fetch_instruction (delayed_pool_write s1) = Inr v)" 
         using fetch_instr_result_1 by auto
       then have "(\<exists>v. fetch_instruction (delayed_pool_write s1) = Inr v \<and>
                       fetch_instruction (delayed_pool_write s2) = Inr v)"
         proof -
           have "cpu_reg s1 = cpu_reg s2" 
             using a1 by (simp add: low_equal_def)
           then have "cpu_reg_val PC s1 = cpu_reg_val PC s2" 
             by (simp add: cpu_reg_val_def)
           then have "cpu_reg_val PC s1 = cpu_reg_val PC s2 \<and>
                      ((ucast (get_S (cpu_reg_val PSR (delayed_pool_write s1))))::word1) = 0 \<and>
                      ((ucast (get_S (cpu_reg_val PSR (delayed_pool_write s2))))::word1) = 0"
             using a1 
             by (auto simp add: empty_delayed_pool_write_privilege)  
           then show ?thesis using a1 f_fetch_suc
           apply (simp add: fetch_instruction_def)
           apply (simp add: Let_def ucast_def) 
           apply clarsimp
           apply (case_tac "uint (3 AND cpu_reg_val PC (delayed_pool_write s1)) = 0")
            apply auto
            apply (case_tac "fst (memory_read 8 (cpu_reg_val PC (delayed_pool_write s1)) 
            (delayed_pool_write s1)) = None")
             apply auto
             apply (simp add: case_prod_unfold)
            using a1 apply (auto simp add: mem_read_delayed_write_low_equal)
            apply (simp add: case_prod_unfold)
            using a1 apply (auto simp add: mem_read_delayed_write_low_equal)
           apply (simp add: delayed_pool_write_def)
           by (simp add: Let_def get_delayed_write_def)
         qed
       then have "(\<exists>v. fetch_instruction (delayed_pool_write s1) = Inr v \<and>
                       fetch_instruction (delayed_pool_write s2) = Inr v \<and>
                       \<not> (\<exists>e. (decode_instruction v) = Inl e))"
         using dispatch_fail f0 a1 f_exe by auto
       then have f_fetch_dec: "(\<exists>v. fetch_instruction (delayed_pool_write s1) = Inr v \<and>
                       fetch_instruction (delayed_pool_write s2) = Inr v \<and>
                       (\<exists>v1. (decode_instruction v) = Inr v1))"
         using decode_instr_result_4 by auto      
       then show ?thesis 
       proof (cases "annul_val (delayed_pool_write s1)")
         case True
         then have "annul_val (delayed_pool_write s1) \<and> annul_val (delayed_pool_write s2)"
           using a1 
           apply (simp add: low_equal_def)
           by (simp add: delayed_pool_write_def get_delayed_write_def annul_val_def)
         then show ?thesis using a1 f1 f_exe f_fetch_dec
         apply (simp add: NEXT_def execute_instruction_def)
         apply (simp add: exec_gets return_def)
         apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
         apply (simp add: simpler_modify_def)
         apply clarsimp
         apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
         apply (simp add: case_prod_unfold)
         apply (simp add: write_cpu_def cpu_reg_val_def set_annul_def)
         apply (simp add: simpler_modify_def)
         apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
         apply (simp add: write_cpu_def cpu_reg_val_def set_annul_def)
         apply (simp add: simpler_modify_def)
         apply (simp add: cpu_reg_mod_def annul_mod_def)
         apply (simp add: delayed_pool_write_def get_delayed_write_def)
         apply (simp add: write_annul_def)
         apply clarsimp
         apply (simp add: low_equal_def)
         apply (simp add: user_accessible_annul mem_equal_annul)
         by (metis)        
       next
         case False
         then have "\<not> annul_val (delayed_pool_write s1) \<and>
           \<not> annul_val (delayed_pool_write s2)"
           using a1 apply (simp add: low_equal_def)
           apply (simp add: delayed_pool_write_def get_delayed_write_def)
           by (simp add: annul_val_def)
         then show ?thesis using a1 f1 f_exe f_fetch_dec
         apply (simp add: NEXT_def execute_instruction_def)
         apply (simp add: exec_gets return_def)
         apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
         apply (simp add: simpler_modify_def)
         apply clarsimp
         apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
         apply (simp add: case_prod_unfold)
         apply (case_tac "snd (execute_instr_sub1 (a, b)
                    (snd (fst (dispatch_instruction (a, b)
                                (delayed_pool_write s1))))) \<or>
              snd (dispatch_instruction (a, b) (delayed_pool_write s1))")
          apply auto
         apply (case_tac "snd (execute_instr_sub1 (a, b)
                    (snd (fst (dispatch_instruction (a, b)
                                (delayed_pool_write s2))))) \<or>
              snd (dispatch_instruction (a, b) (delayed_pool_write s2))")
          apply auto
         apply (simp add: simpler_modify_def)
         apply (simp add: simpler_gets_def bind_def h1_def h2_def Let_def)
         apply (simp add: case_prod_unfold)
         apply (simp add: delayed_pool_write_def get_delayed_write_def)
         by (meson dispath_instr_low_equal dispath_instr_privilege execute_instr_sub1_low_equal)        
       qed
     qed
   next
     case False
     then have f_non_exe: "exe_mode_val s1 = False" by auto
     then have "exe_mode_val s1 = False \<and> exe_mode_val s2 = False"        
       proof -
         have "low_equal s1 s2" using a1 by auto
         then have "state_var s1 = state_var s2" by (simp add: low_equal_def)
         then have "exe_mode_val s1 = exe_mode_val s2" by (simp add: exe_mode_val_def)
         then show ?thesis using f_non_exe by auto
       qed
     then show ?thesis using f1 a1    
     apply (simp add: NEXT_def execute_instruction_def)
     by (simp add: simpler_gets_def bind_def h1_def h2_def Let_def return_def)
   qed
 qed
 
 function (sequential) SEQ:: "nat \<Rightarrow> ('a::len0) sparc_state \<Rightarrow> ('a) sparc_state option"
 where "SEQ 0 s = Some s"
 |"SEQ n s = (
   case SEQ (n-1) s of None \<Rightarrow> None
   | Some t \<Rightarrow> NEXT t
 )"
 by pat_completeness auto
 termination by lexicographic_order
 
 lemma SEQ_suc: "SEQ n s = Some t \<Longrightarrow> SEQ (Suc n) s = NEXT t"
 apply (induction n)
  apply clarsimp
 by (simp add: option.case_eq_if)
 
 definition user_seq_exe:: "nat \<Rightarrow> ('a::len0) sparc_state \<Rightarrow> bool" where
 "user_seq_exe n s \<equiv> \<forall>i t. (i \<le> n \<and> SEQ i s = Some t) \<longrightarrow>
   (good_context t \<and> get_delayed_pool t = [] \<and> get_trap_set t = {})"
 
 text \<open>NIA is short for non-interference assumption.\<close>
 definition "NIA t1 t2 \<equiv> 
     ((ucast (get_S (cpu_reg_val PSR t1)))::word1) = 0 \<and>
     ((ucast (get_S (cpu_reg_val PSR t2)))::word1) = 0 \<and>
     good_context t1 \<and> get_delayed_pool t1 = [] \<and> get_trap_set t1 = {} \<and>
     good_context t2 \<and> get_delayed_pool t2 = [] \<and> get_trap_set t2 = {} \<and>
     low_equal t1 t2"
 
 text \<open>NIC is short for non-interference conclusion.\<close>
 definition "NIC t1 t2 \<equiv> (\<exists>u1 u2. Some u1 = NEXT t1 \<and> Some u2 = NEXT t2 \<and> 
     ((ucast (get_S (cpu_reg_val PSR u1)))::word1) = 0 \<and>
     ((ucast (get_S (cpu_reg_val PSR u2)))::word1) = 0 \<and>
     low_equal u1 u2)"
 
 lemma NIS_short: "\<forall>t1 t2. NIA t1 t2 \<longrightarrow> NIC t1 t2"
 apply (simp add: NIA_def NIC_def)
 using non_interference_step by auto
 
 lemma non_interference_induct_case_sub1:
 assumes a1: "(\<exists>t1. Some t1 = SEQ n s1 \<and>
     (\<exists>t2. Some t2 = SEQ n s2 \<and>
     NIA t1 t2))"
 shows "(\<exists>t1. Some t1 = SEQ n s1 \<and>
     (\<exists>t2. Some t2 = SEQ n s2 \<and>
     NIA t1 t2 \<and>
     NIC t1 t2))"
 using NIS_short
 using assms by auto 
 
 lemma non_interference_induct_case: 
 assumes a1: 
 "((\<forall>i t. i \<le> n \<and> SEQ i s1 = Some t \<longrightarrow>
                  good_context t \<and> get_delayed_pool t = [] \<and> get_trap_set t = {}) \<and>
           (\<forall>i t. i \<le> n \<and> SEQ i s2 = Some t \<longrightarrow>
                  good_context t \<and> get_delayed_pool t = [] \<and> get_trap_set t = {}) \<longrightarrow>
           (\<exists>t1. Some t1 = SEQ n s1 \<and>
                (\<exists>t2. Some t2 = SEQ n s2 \<and>
                      ((ucast (get_S (cpu_reg_val PSR t1)))::word1) = 0 \<and>
     ((ucast (get_S (cpu_reg_val PSR t2)))::word1) = 0 \<and> low_equal t1 t2))) \<and>
 (\<forall>i t. i \<le> Suc n \<and> SEQ i s1 = Some t \<longrightarrow>
                good_context t \<and> get_delayed_pool t = [] \<and> get_trap_set t = {}) \<and>
          (\<forall>i t. i \<le> Suc n \<and> SEQ i s2 = Some t \<longrightarrow>
                good_context t \<and> get_delayed_pool t = [] \<and> get_trap_set t = {})"
 shows "\<exists>t1. Some t1 = (case SEQ n s1 of None \<Rightarrow> None | Some x \<Rightarrow> NEXT x) \<and>
               (\<exists>t2. Some t2 = (case SEQ n s2 of None \<Rightarrow> None | Some x \<Rightarrow> NEXT x) \<and>
                     ((ucast (get_S (cpu_reg_val PSR t1)))::word1) = 0 \<and>
     ((ucast (get_S (cpu_reg_val PSR t2)))::word1) = 0 \<and> low_equal t1 t2)"
 proof -
   from a1 have f1: "((\<forall>i t. i \<le> n \<and> SEQ i s1 = Some t \<longrightarrow>
   good_context t \<and> get_delayed_pool t = [] \<and> get_trap_set t = {}) \<and>
   (\<forall>i t. i \<le> n \<and> SEQ i s2 = Some t \<longrightarrow>
   good_context t \<and> get_delayed_pool t = [] \<and> get_trap_set t = {}))"
   by (metis le_SucI)
   then have f2: "(\<exists>t1. Some t1 = SEQ n s1 \<and>
     (\<exists>t2. Some t2 = SEQ n s2 \<and>
     ((ucast (get_S (cpu_reg_val PSR t1)))::word1) = 0 \<and>
     ((ucast (get_S (cpu_reg_val PSR t2)))::word1) = 0 \<and>
     low_equal t1 t2))"
   using a1 by auto
   then have f3: "(\<exists>t1. Some t1 = SEQ n s1 \<and>
     (\<exists>t2. Some t2 = SEQ n s2 \<and>
     NIA t1 t2))"
   using f1 NIA_def by (metis (full_types) dual_order.refl)  
   then have "(\<exists>t1. Some t1 = SEQ n s1 \<and>
     (\<exists>t2. Some t2 = SEQ n s2 \<and>
     NIA t1 t2 \<and>
     NIC t1 t2))"
   using non_interference_induct_case_sub1 by blast
   then have "(\<exists>t1. Some t1 = SEQ n s1 \<and>
     (\<exists>t2. Some t2 = SEQ n s2 \<and>
     (((ucast (get_S (cpu_reg_val PSR t1)))::word1) = 0 \<and>
     ((ucast (get_S (cpu_reg_val PSR t2)))::word1) = 0 \<and>
     good_context t1 \<and> get_delayed_pool t1 = [] \<and> get_trap_set t1 = {} \<and>
     good_context t2 \<and> get_delayed_pool t2 = [] \<and> get_trap_set t2 = {} \<and>
     low_equal t1 t2) \<and>
     (\<exists>u1 u2. Some u1 = NEXT t1 \<and> Some u2 = NEXT t2 \<and> 
     ((ucast (get_S (cpu_reg_val PSR u1)))::word1) = 0 \<and>
     ((ucast (get_S (cpu_reg_val PSR u2)))::word1) = 0 \<and>
     low_equal u1 u2)))"
   using NIA_def NIC_def by fastforce
   then show ?thesis
   by (metis option.simps(5))
 qed
 
 lemma non_interference_induct_case_sub2: 
 assumes a1: 
 "(user_seq_exe n s1 \<and>
           user_seq_exe n s2 \<longrightarrow>
           (\<exists>t1. Some t1 = SEQ n s1 \<and>
                (\<exists>t2. Some t2 = SEQ n s2 \<and>
                      ((ucast (get_S (cpu_reg_val PSR t1)))::word1) = 0 \<and>
     ((ucast (get_S (cpu_reg_val PSR t2)))::word1) = 0 \<and> low_equal t1 t2))) \<and>
 user_seq_exe (Suc n) s1 \<and>
          user_seq_exe (Suc n) s2"
 shows "\<exists>t1. Some t1 = (case SEQ n s1 of None \<Rightarrow> None | Some x \<Rightarrow> NEXT x) \<and>
               (\<exists>t2. Some t2 = (case SEQ n s2 of None \<Rightarrow> None | Some x \<Rightarrow> NEXT x) \<and>
                     ((ucast (get_S (cpu_reg_val PSR t1)))::word1) = 0 \<and>
     ((ucast (get_S (cpu_reg_val PSR t2)))::word1) = 0 \<and> low_equal t1 t2)"
 using a1
 by (simp add: non_interference_induct_case user_seq_exe_def)
 
 theorem non_interference:
 assumes a1: 
 "((ucast (get_S (cpu_reg_val PSR s1)))::word1) = 0 \<and>
 good_context s1 \<and>
 get_delayed_pool s1 = [] \<and> get_trap_set s1 = {} \<and>
 ((ucast (get_S (cpu_reg_val PSR s2)))::word1) = 0 \<and>
 get_delayed_pool s2 = [] \<and> get_trap_set s2 = {} \<and>
 good_context s2 \<and>
 user_seq_exe n s1 \<and> user_seq_exe n s2 \<and>
 low_equal s1 s2"
 shows "(\<exists>t1 t2. Some t1 = SEQ n s1 \<and> Some t2 = SEQ n s2 \<and>
   ((ucast (get_S (cpu_reg_val PSR t1)))::word1) = 0 \<and>
   ((ucast (get_S (cpu_reg_val PSR t2)))::word1) = 0 \<and>
   low_equal t1 t2)"
 using a1
 apply (induction n)
  apply (simp add: user_seq_exe_def)
 apply clarsimp
 by (simp add: non_interference_induct_case_sub2)
 
 end
diff --git a/thys/SPARCv8/SparcModel_MMU/Sparc_State.thy b/thys/SPARCv8/SparcModel_MMU/Sparc_State.thy
--- a/thys/SPARCv8/SparcModel_MMU/Sparc_State.thy
+++ b/thys/SPARCv8/SparcModel_MMU/Sparc_State.thy
@@ -1,1007 +1,1007 @@
 (*
  * Copyright 2016, NTU
  *
  * This software may be distributed and modified according to the terms of
  * the BSD 2-Clause license. Note that NO WARRANTY is provided.
  * See "LICENSE_BSD2.txt" for details.
  *
  * Author: Zhe Hou, David Sanan.
  *)
 
 section \<open>SPARC V8 state model\<close>
 theory Sparc_State
 imports Main Sparc_Types  "../lib/wp/DetMonadLemmas" MMU
 begin                                                                    
 section \<open>state as a function\<close>
 
 record cpu_cache = 
 dcache:: cache_context
 icache:: cache_context
 
 text\<open>
 The state @{term sparc_state} is defined as a tuple @{term cpu_context}, 
 @{term user_context}, @{term mem_context}, defining the state of the CPU registers, 
 user registers, memory, cache, and delayed write pool respectively. 
 Additionally, a boolean indicates whether the state is 
 undefined or not.
 \<close>
 
 record (overloaded) ('a) sparc_state =
 cpu_reg:: cpu_context
 user_reg:: "('a) user_context"
 sys_reg:: sys_context
 mem:: mem_context
 mmu:: MMU_state
 cache:: cpu_cache
 dwrite:: delayed_write_pool
 state_var:: sparc_state_var
 traps:: "Trap set"
 undef:: bool
 
 section\<open>functions for state member access\<close>
 
 definition cpu_reg_val:: "CPU_register \<Rightarrow> ('a) sparc_state \<Rightarrow> reg_type"
 where
 "cpu_reg_val reg state \<equiv> (cpu_reg state) reg"
 
 definition cpu_reg_mod :: "word32 \<Rightarrow> CPU_register \<Rightarrow> ('a) sparc_state \<Rightarrow> 
                            ('a) sparc_state"
 where "cpu_reg_mod data_w32 cpu state \<equiv> 
   state\<lparr>cpu_reg := ((cpu_reg state)(cpu := data_w32))\<rparr>"
 
 text \<open>r[0] = 0. Otherwise read the actual value.\<close>
 definition user_reg_val:: "('a) window_size \<Rightarrow> user_reg_type \<Rightarrow> ('a) sparc_state \<Rightarrow> reg_type"
 where
 "user_reg_val window ur state \<equiv> 
   if ur = 0 then 0
   else (user_reg state) window ur"
 
 text \<open>Write a global register. win should be initialised as NWINDOWS.\<close>
 fun (sequential) global_reg_mod :: "word32 \<Rightarrow> nat \<Rightarrow> user_reg_type \<Rightarrow> 
   ('a::len0) sparc_state \<Rightarrow> ('a) sparc_state"
 where
 "global_reg_mod data_w32 0 ur state = state"
 |
 "global_reg_mod data_w32 win ur state = (
     let win_word = word_of_int (int (win-1));
         ns = state\<lparr>user_reg := 
           (user_reg state)(win_word := ((user_reg state) win_word)(ur := data_w32))\<rparr> 
     in
     global_reg_mod data_w32 (win-1) ur ns
 )"
 
 text \<open>Compute the next window.\<close>
 definition next_window :: "('a::len0) window_size \<Rightarrow> ('a) window_size"
 where
 "next_window win \<equiv>
   if (uint win) < (NWINDOWS - 1) then (win + 1)
   else 0
 "
 
 text \<open>Compute the previous window.\<close>
 definition pre_window :: "('a::len0) window_size \<Rightarrow> ('a::len0) window_size"
 where
 "pre_window win \<equiv>
   if (uint win) > 0 then (win - 1)
   else (word_of_int (NWINDOWS - 1))
 "
 
 text \<open>write an output register. 
   Also write ur+16 of the previous window.\<close>
 definition out_reg_mod :: "word32 \<Rightarrow> ('a::len0) window_size \<Rightarrow> user_reg_type \<Rightarrow> 
   ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where
 "out_reg_mod data_w32 win ur state \<equiv>
   let state' = state\<lparr>user_reg :=
         (user_reg state)(win := ((user_reg state) win)(ur := data_w32))\<rparr>;
       win' = pre_window win;
       ur' = ur + 16
   in
   state'\<lparr>user_reg := 
     (user_reg state')(win' := ((user_reg state') win')(ur' := data_w32))\<rparr>
 "
 
 text \<open>Write a input register.
   Also write ur-16 of the next window.\<close>
 definition in_reg_mod :: "word32 \<Rightarrow> ('a::len0) window_size \<Rightarrow> user_reg_type \<Rightarrow>
   ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where
 "in_reg_mod data_w32 win ur state \<equiv>
   let state' = state\<lparr>user_reg :=
     (user_reg state)(win := ((user_reg state) win)(ur := data_w32))\<rparr>;
       win' = next_window win;
       ur' = ur - 16
   in
   state'\<lparr>user_reg :=
     (user_reg state')(win' := ((user_reg state') win')(ur' := data_w32))\<rparr>
 "
 
 text \<open>Do not modify r[0].\<close>
 definition user_reg_mod :: "word32 \<Rightarrow> ('a::len0) window_size \<Rightarrow> user_reg_type \<Rightarrow> 
  ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where
 "user_reg_mod data_w32 win ur state \<equiv>
   if ur = 0 then state
   else if 0 < ur \<and> ur < 8 then
     global_reg_mod data_w32 (nat NWINDOWS) ur state
   else if 7 < ur \<and> ur < 16 then 
     out_reg_mod data_w32 win ur state
   else if 15 < ur \<and> ur < 24 then
     state\<lparr>user_reg := 
       (user_reg state)(win := ((user_reg state) win)(ur := data_w32))\<rparr>
   else \<^cancel>\<open>if 23 < ur \<and> ur < 32 then\<close>
     in_reg_mod data_w32 win ur state
   \<^cancel>\<open>else state\<close>
 "
 
 definition sys_reg_val :: "sys_reg \<Rightarrow> ('a) sparc_state \<Rightarrow> reg_type"
 where
 "sys_reg_val reg state \<equiv> (sys_reg state) reg"
 
 definition sys_reg_mod :: "word32 \<Rightarrow> sys_reg \<Rightarrow> 
                           ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where
 "sys_reg_mod data_w32 sys state \<equiv> state\<lparr>sys_reg := (sys_reg state)(sys := data_w32)\<rparr>"
 
 text \<open>The following fucntions deal with physical memory. 
 N.B. Physical memory address in SPARCv8 is 36-bit.\<close>
 
 text \<open>LEON3 doesn't distinguish ASI 8 and 9; 10 and 11 for read access
   for both user and supervisor. 
 We recently discovered that the compiled machine code by
 the sparc-elf compiler often reads asi = 10 (user data) 
 when the actual content is store in asi = 8 (user instruction).
 For testing purposes, we don't distinguish asi = 8,9,10,11
 for reading access.\<close>
 
 definition mem_val:: "asi_type \<Rightarrow> phys_address \<Rightarrow> 
                       ('a) sparc_state \<Rightarrow> mem_val_type option"
 where
 "mem_val asi add state \<equiv> 
   let asi8 = word_of_int 8;
       asi9 = word_of_int 9;
       asi10 = word_of_int 10;
       asi11 = word_of_int 11;
       r1 = (mem state) asi8 add
   in
   if r1 = None then
     let r2 = (mem state) asi9 add in
     if r2 = None then
       let r3 = (mem state) asi10 add in
       if r3 = None then 
         (mem state) asi11 add
       else r3
     else r2
   else r1
 "
 
 text \<open>An alternative way to read values from memory. 
 Some implementations may use this definition.\<close>
 
 definition mem_val_alt:: "asi_type \<Rightarrow> phys_address \<Rightarrow> 
                       ('a) sparc_state \<Rightarrow> mem_val_type option"
 where
 "mem_val_alt asi add state \<equiv> 
   let r1 = (mem state) asi add; 
       asi8 = word_of_int 8;
       asi9 = word_of_int 9;
       asi10 = word_of_int 10;
       asi11 = word_of_int 11
   in
   if r1 = None \<and> (uint asi) = 8 then
     let r2 = (mem state) asi9 add in
     r2
   else if r1 = None \<and> (uint asi) = 9 then
     let r2 = (mem state) asi8 add in
     r2
   else if r1 = None \<and> (uint asi) = 10 then
     let r2 = (mem state) asi11 add in
     if r2 = None then
       let r3 = (mem state) asi8 add in
       if r3 = None then
         (mem state) asi9 add        
       else r3
     else r2
   else if r1 = None \<and> (uint asi) = 11 then
     let r2 = (mem state) asi10 add in
     if r2 = None then
       let r3 = (mem state) asi8 add in
       if r3 = None then
         (mem state) asi9 add        
       else r3
     else r2
   else r1"
 
 definition mem_mod :: "asi_type \<Rightarrow> phys_address \<Rightarrow> mem_val_type \<Rightarrow> 
                          ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where
 "mem_mod asi addr val state \<equiv>
   let state1 = state\<lparr>mem := (mem state)
     (asi := ((mem state) asi)(addr := Some val))\<rparr>
   in \<comment> \<open>Only allow one of \<open>asi\<close> 8 and 9 (10 and 11) to have value.\<close>
   if (uint asi) = 8 \<or> (uint asi) = 10 then
     let asi2 = word_of_int ((uint asi) + 1) in
     state1\<lparr>mem := (mem state1)
       (asi2 := ((mem state1) asi2)(addr := None))\<rparr>
   else if (uint asi) = 9 \<or> (uint asi) = 11 then
     let asi2 = word_of_int ((uint asi) - 1) in
     state1\<lparr>mem := (mem state1)(asi2 := ((mem state1) asi2)(addr := None))\<rparr>
   else state1
 "
 
 text \<open>An alternative way to write memory. This method insists that 
 for each address, it can only hold a value in one of ASI = 8,9,10,11.\<close>
 
 definition mem_mod_alt :: "asi_type \<Rightarrow> phys_address \<Rightarrow> mem_val_type \<Rightarrow> 
                          ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where
 "mem_mod_alt asi addr val state \<equiv>
   let state1 = state\<lparr>mem := (mem state)
     (asi := ((mem state) asi)(addr := Some val))\<rparr>;
     asi8 = word_of_int 8;
     asi9 = word_of_int 9;
     asi10 = word_of_int 10;
     asi11 = word_of_int 11
   in 
   \<comment> \<open>Only allow one of \<open>asi\<close> 8, 9, 10, 11 to have value.\<close>
   if (uint asi) = 8 then 
     let state2 = state1\<lparr>mem := (mem state1)
       (asi9 := ((mem state1) asi9)(addr := None))\<rparr>;
      state3 = state2\<lparr>mem := (mem state2)
       (asi10 := ((mem state2) asi10)(addr := None))\<rparr>;
      state4 = state3\<lparr>mem := (mem state3)
       (asi11 := ((mem state3) asi11)(addr := None))\<rparr>
     in
     state4
   else if (uint asi) = 9 then 
     let state2 = state1\<lparr>mem := (mem state1)
       (asi8 := ((mem state1) asi8)(addr := None))\<rparr>;  
      state3 = state2\<lparr>mem := (mem state2)
       (asi10 := ((mem state2) asi10)(addr := None))\<rparr>;
      state4 = state3\<lparr>mem := (mem state3)
       (asi11 := ((mem state3) asi11)(addr := None))\<rparr>
     in
     state4  
   else if (uint asi) = 10 then 
     let state2 = state1\<lparr>mem := (mem state1)
       (asi9 := ((mem state1) asi9)(addr := None))\<rparr>;
      state3 = state2\<lparr>mem := (mem state2)
       (asi8 := ((mem state2) asi8)(addr := None))\<rparr>;
      state4 = state3\<lparr>mem := (mem state3)
       (asi11 := ((mem state3) asi11)(addr := None))\<rparr>
     in
     state4
   else if (uint asi) = 11 then 
     let state2 = state1\<lparr>mem := (mem state1)
       (asi9 := ((mem state1) asi9)(addr := None))\<rparr>;
      state3 = state2\<lparr>mem := (mem state2)
       (asi10 := ((mem state2) asi10)(addr := None))\<rparr>;
      state4 = state3\<lparr>mem := (mem state3)
       (asi8 := ((mem state3) asi8)(addr := None))\<rparr>
     in
     state4
   else state1
 "
 
 text \<open>Given an ASI (word8), an address (word32) addr, 
         read the 32bit value from the memory addresses 
         starting from address addr' where addr' = addr 
         exception that the last two bits are 0's. 
         That is, read the data from 
         addr', addr'+1, addr'+2, addr'+3.\<close>
 definition mem_val_w32 :: "asi_type \<Rightarrow> phys_address \<Rightarrow> 
                            ('a) sparc_state \<Rightarrow> word32 option"
 where
 "mem_val_w32 asi addr state \<equiv>
-  let addr' = bitAND addr 0b111111111111111111111111111111111100;
+  let addr' = (AND) addr 0b111111111111111111111111111111111100;
       addr0 = addr';
       addr1 = addr' + 1;
       addr2 = addr' + 2;
       addr3 = addr' + 3;
       r0 = mem_val_alt asi addr0 state;
       r1 = mem_val_alt asi addr1 state;
       r2 = mem_val_alt asi addr2 state;
       r3 = mem_val_alt asi addr3 state
   in
   if r0 = None \<or> r1 = None \<or> r2 = None \<or> r3 = None then
     None
   else
     let byte0 = case r0 of Some v \<Rightarrow> v;
         byte1 = case r1 of Some v \<Rightarrow> v;
         byte2 = case r2 of Some v \<Rightarrow> v;
         byte3 = case r3 of Some v \<Rightarrow> v 
     in
-    Some (bitOR (bitOR (bitOR ((ucast(byte0)) << 24) 
+    Some ((OR) ((OR) ((OR) ((ucast(byte0)) << 24) 
                               ((ucast(byte1)) << 16)) 
                        ((ucast(byte2)) << 8)) 
                 (ucast(byte3)))
 "
 
 text \<open>
   Let \<open>addr'\<close> be \<open>addr\<close> with last two bits set to 0's.
   Write the 32bit data in the memory address \<open>addr'\<close>
   (and the following 3 addresses). 
   \<open>byte_mask\<close> decides which byte of the 32bits are written.
 \<close>
 definition mem_mod_w32 :: "asi_type \<Rightarrow> phys_address \<Rightarrow> word4 \<Rightarrow> word32 \<Rightarrow> 
                            ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where
 "mem_mod_w32 asi addr byte_mask data_w32 state \<equiv>
-  let addr' = bitAND addr 0b111111111111111111111111111111111100;
-      addr0 = bitOR addr' 0b000000000000000000000000000000000000;
-      addr1 = bitOR addr' 0b000000000000000000000000000000000001;
-      addr2 = bitOR addr' 0b000000000000000000000000000000000010;
-      addr3 = bitOR addr' 0b000000000000000000000000000000000011;
+  let addr' = (AND) addr 0b111111111111111111111111111111111100;
+      addr0 = (OR) addr' 0b000000000000000000000000000000000000;
+      addr1 = (OR) addr' 0b000000000000000000000000000000000001;
+      addr2 = (OR) addr' 0b000000000000000000000000000000000010;
+      addr3 = (OR) addr' 0b000000000000000000000000000000000011;
       byte0 = (ucast (data_w32 >> 24))::mem_val_type;
       byte1 = (ucast (data_w32 >> 16))::mem_val_type;
       byte2 = (ucast (data_w32 >> 8))::mem_val_type;
       byte3 = (ucast data_w32)::mem_val_type;
-      s0 = if ((bitAND byte_mask (0b1000::word4)) >> 3) = 1 then
+      s0 = if (((AND) byte_mask (0b1000::word4)) >> 3) = 1 then
               mem_mod asi addr0 byte0 state 
            else state;
-      s1 = if ((bitAND byte_mask (0b0100::word4)) >> 2) = 1 then
+      s1 = if (((AND) byte_mask (0b0100::word4)) >> 2) = 1 then
               mem_mod asi addr1 byte1 s0 
            else s0;
-      s2 = if ((bitAND byte_mask (0b0010::word4)) >> 1) = 1 then
+      s2 = if (((AND) byte_mask (0b0010::word4)) >> 1) = 1 then
               mem_mod asi addr2 byte2 s1 
            else s1;
-      s3 = if (bitAND byte_mask (0b0001::word4)) = 1 then
+      s3 = if ((AND) byte_mask (0b0001::word4)) = 1 then
               mem_mod asi addr3 byte3 s2 
            else s2
   in
   s3
 "
 
 text \<open>The following functions deal with virtual addresses. 
 These are based on functions written by David Sanan.\<close>
 
 definition load_word_mem :: "('a) sparc_state \<Rightarrow> virtua_address \<Rightarrow> asi_type \<Rightarrow> 
                              machine_word option"
 where "load_word_mem state va asi \<equiv> 
 let pair = (virt_to_phys va (mmu state) (mem state)) in 
 case pair of
   Some pair \<Rightarrow> ( 
     if mmu_readable (get_acc_flag (snd pair)) asi then 
       (mem_val_w32 asi (fst pair) state)
     else None)
   | None \<Rightarrow> None"
 
 definition store_word_mem ::"('a) sparc_state \<Rightarrow> virtua_address \<Rightarrow> machine_word \<Rightarrow> 
                              word4 \<Rightarrow> asi_type \<Rightarrow> ('a) sparc_state option"
 where "store_word_mem state va wd byte_mask asi \<equiv> 
 let pair = (virt_to_phys va (mmu state) (mem state)) in 
 case pair of
   Some pair \<Rightarrow> ( 
     if mmu_writable (get_acc_flag (snd pair)) asi then 
       Some (mem_mod_w32 asi (fst pair) byte_mask wd state)
     else None)
   | None \<Rightarrow> None"
 
 definition icache_val:: "cache_type \<Rightarrow> ('a) sparc_state \<Rightarrow> mem_val_type option"
 where "icache_val c state \<equiv> icache (cache state) c"
 
 definition dcache_val:: "cache_type \<Rightarrow> ('a) sparc_state \<Rightarrow> mem_val_type option"
 where "dcache_val c state \<equiv> dcache (cache state) c"
 
 definition icache_mod :: "cache_type \<Rightarrow> mem_val_type \<Rightarrow> 
                            ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where "icache_mod c val state \<equiv> 
   state\<lparr>cache := ((cache state)
     \<lparr>icache := (icache (cache state))(c := Some val)\<rparr>)\<rparr>
 "
 
 definition dcache_mod :: "cache_type \<Rightarrow> mem_val_type \<Rightarrow> 
                            ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where "dcache_mod c val state \<equiv> 
   state\<lparr>cache := ((cache state)
     \<lparr>dcache := (dcache (cache state))(c := Some val)\<rparr>)\<rparr>
 "
 
 text \<open>Check if the memory address is in the cache or not.\<close>
 definition icache_miss :: "virtua_address \<Rightarrow> ('a) sparc_state \<Rightarrow> bool"
 where
 "icache_miss addr state \<equiv>
   let line_len = 12;
       tag = (ucast (addr >> line_len))::cache_tag;
       line = (ucast (0b0::word1))::cache_line_size 
   in
   if (icache_val (tag,line) state) = None then True 
   else False    
 "
 
 text \<open>Check if the memory address is in the cache or not.\<close>
 definition dcache_miss :: "virtua_address \<Rightarrow> ('a) sparc_state \<Rightarrow> bool"
 where
 "dcache_miss addr state \<equiv>
   let line_len = 12;
       tag = (ucast (addr >> line_len))::cache_tag;
       line = (ucast (0b0::word1))::cache_line_size 
   in
   if (dcache_val (tag,line) state) = None then True 
   else False    
 "
 
 definition read_data_cache:: "('a) sparc_state \<Rightarrow> virtua_address \<Rightarrow> machine_word option"
 where "read_data_cache state va \<equiv>
   let tag = (ucast (va >> 12))::word20;
-       offset0 = bitAND ((ucast va)::word12) 0b111111111100;
-       offset1 = bitOR offset0 0b000000000001;
-       offset2 = bitOR offset0 0b000000000010;
-       offset3 = bitOR offset0 0b000000000011;
+       offset0 = (AND) ((ucast va)::word12) 0b111111111100;
+       offset1 = (OR) offset0 0b000000000001;
+       offset2 = (OR) offset0 0b000000000010;
+       offset3 = (OR) offset0 0b000000000011;
        r0 = dcache_val (tag,offset0) state;
        r1 = dcache_val (tag,offset1) state;
        r2 = dcache_val (tag,offset2) state;
        r3 = dcache_val (tag,offset3) state
   in
   if r0 = None \<or> r1 = None \<or> r2 = None \<or> r3 = None then
     None
   else
     let byte0 = case r0 of Some v \<Rightarrow> v;
         byte1 = case r1 of Some v \<Rightarrow> v;
         byte2 = case r2 of Some v \<Rightarrow> v;
         byte3 = case r3 of Some v \<Rightarrow> v 
     in
-    Some (bitOR (bitOR (bitOR ((ucast(byte0)) << 24) 
+    Some ((OR) ((OR) ((OR) ((ucast(byte0)) << 24) 
                               ((ucast(byte1)) << 16)) 
                        ((ucast(byte2)) << 8)) 
                 (ucast(byte3)))
 "
 
 definition read_instr_cache:: "('a) sparc_state \<Rightarrow> virtua_address \<Rightarrow> machine_word option"
 where "read_instr_cache state va \<equiv>
   let tag = (ucast (va >> 12))::word20;
-       offset0 = bitAND ((ucast va)::word12) 0b111111111100;
-       offset1 = bitOR offset0 0b000000000001;
-       offset2 = bitOR offset0 0b000000000010;
-       offset3 = bitOR offset0 0b000000000011;
+       offset0 = (AND) ((ucast va)::word12) 0b111111111100;
+       offset1 = (OR) offset0 0b000000000001;
+       offset2 = (OR) offset0 0b000000000010;
+       offset3 = (OR) offset0 0b000000000011;
        r0 = icache_val (tag,offset0) state;
        r1 = icache_val (tag,offset1) state;
        r2 = icache_val (tag,offset2) state;
        r3 = icache_val (tag,offset3) state
   in
   if r0 = None \<or> r1 = None \<or> r2 = None \<or> r3 = None then
     None
   else
     let byte0 = case r0 of Some v \<Rightarrow> v;
         byte1 = case r1 of Some v \<Rightarrow> v;
         byte2 = case r2 of Some v \<Rightarrow> v;
         byte3 = case r3 of Some v \<Rightarrow> v 
     in
-    Some (bitOR (bitOR (bitOR ((ucast(byte0)) << 24) 
+    Some ((OR) ((OR) ((OR) ((ucast(byte0)) << 24) 
                               ((ucast(byte1)) << 16)) 
                        ((ucast(byte2)) << 8)) 
                 (ucast(byte3)))
 "
 
 definition add_data_cache :: "('a) sparc_state \<Rightarrow> virtua_address \<Rightarrow> machine_word \<Rightarrow> 
   word4 \<Rightarrow> ('a) sparc_state"
 where 
  "add_data_cache state va word byte_mask \<equiv> 
    let tag = (ucast (va >> 12))::word20;
-       offset0 = bitAND ((ucast va)::word12) 0b111111111100;
-       offset1 = bitOR offset0 0b000000000001;
-       offset2 = bitOR offset0 0b000000000010;
-       offset3 = bitOR offset0 0b000000000011;
+       offset0 = (AND) ((ucast va)::word12) 0b111111111100;
+       offset1 = (OR) offset0 0b000000000001;
+       offset2 = (OR) offset0 0b000000000010;
+       offset3 = (OR) offset0 0b000000000011;
        byte0 = (ucast (word >> 24))::mem_val_type;
        byte1 = (ucast (word >> 16))::mem_val_type;
        byte2 = (ucast (word >> 8))::mem_val_type;
        byte3 = (ucast word)::mem_val_type;
-       s0 = if ((bitAND byte_mask (0b1000::word4)) >> 3) = 1 then
+       s0 = if (((AND) byte_mask (0b1000::word4)) >> 3) = 1 then
               dcache_mod (tag,offset0) byte0 state
             else state;
-       s1 = if ((bitAND byte_mask (0b0100::word4)) >> 2) = 1 then
+       s1 = if (((AND) byte_mask (0b0100::word4)) >> 2) = 1 then
               dcache_mod (tag,offset1) byte1 s0
             else s0;
-       s2 = if ((bitAND byte_mask (0b0010::word4)) >> 1) = 1 then
+       s2 = if (((AND) byte_mask (0b0010::word4)) >> 1) = 1 then
               dcache_mod (tag,offset2) byte2 s1
             else s1;
-       s3 = if (bitAND byte_mask (0b0001::word4)) = 1 then
+       s3 = if ((AND) byte_mask (0b0001::word4)) = 1 then
               dcache_mod (tag,offset3) byte3 s2
             else s2
    in s3
 "
 
 definition add_instr_cache :: "('a) sparc_state \<Rightarrow> virtua_address \<Rightarrow> machine_word \<Rightarrow> 
   word4 \<Rightarrow> ('a) sparc_state"
 where 
  "add_instr_cache state va word byte_mask \<equiv> 
    let tag = (ucast (va >> 12))::word20;
-       offset0 = bitAND ((ucast va)::word12) 0b111111111100;
-       offset1 = bitOR offset0 0b000000000001;
-       offset2 = bitOR offset0 0b000000000010;
-       offset3 = bitOR offset0 0b000000000011;
+       offset0 = (AND) ((ucast va)::word12) 0b111111111100;
+       offset1 = (OR) offset0 0b000000000001;
+       offset2 = (OR) offset0 0b000000000010;
+       offset3 = (OR) offset0 0b000000000011;
        byte0 = (ucast (word >> 24))::mem_val_type;
        byte1 = (ucast (word >> 16))::mem_val_type;
        byte2 = (ucast (word >> 8))::mem_val_type;
        byte3 = (ucast word)::mem_val_type;
-       s0 = if ((bitAND byte_mask (0b1000::word4)) >> 3) = 1 then
+       s0 = if (((AND) byte_mask (0b1000::word4)) >> 3) = 1 then
               icache_mod (tag,offset0) byte0 state
             else state;
-       s1 = if ((bitAND byte_mask (0b0100::word4)) >> 2) = 1 then
+       s1 = if (((AND) byte_mask (0b0100::word4)) >> 2) = 1 then
               icache_mod (tag,offset1) byte1 s0
             else s0;
-       s2 = if ((bitAND byte_mask (0b0010::word4)) >> 1) = 1 then
+       s2 = if (((AND) byte_mask (0b0010::word4)) >> 1) = 1 then
               icache_mod (tag,offset2) byte2 s1
             else s1;
-       s3 = if (bitAND byte_mask (0b0001::word4)) = 1 then
+       s3 = if ((AND) byte_mask (0b0001::word4)) = 1 then
               icache_mod (tag,offset3) byte3 s2
             else s2
    in s3
 "
 
 definition empty_cache ::"cache_context" where "empty_cache c \<equiv> None"
 
 definition flush_data_cache:: "('a) sparc_state \<Rightarrow> ('a) sparc_state" where
 "flush_data_cache state \<equiv> state\<lparr>cache := ((cache state)\<lparr>dcache := empty_cache\<rparr>)\<rparr>"
 
 definition flush_instr_cache:: "('a) sparc_state \<Rightarrow> ('a) sparc_state" where
 "flush_instr_cache state \<equiv> state\<lparr>cache := ((cache state)\<lparr>icache := empty_cache\<rparr>)\<rparr>"
 
 definition flush_cache_all:: "('a) sparc_state \<Rightarrow> ('a) sparc_state" where
 "flush_cache_all state \<equiv> state\<lparr>cache := ((cache state)\<lparr>
   icache := empty_cache, dcache := empty_cache\<rparr>)\<rparr>"
 
 text \<open>Check if the FI or FD bit of CCR is 1. 
 If FI is 1 then flush instruction cache. 
 If FD is 1 then flush data cache.\<close>
 definition ccr_flush :: "('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where
 "ccr_flush state \<equiv>
   let ccr_val = sys_reg_val CCR state;
       \<comment> \<open>\<open>FI\<close> is bit 21 of \<open>CCR\<close>\<close>
-      fi_val = (bitAND ccr_val (0b00000000001000000000000000000000)) >> 21;
-      fd_val = (bitAND ccr_val (0b00000000010000000000000000000000)) >> 22;
+      fi_val = ((AND) ccr_val (0b00000000001000000000000000000000)) >> 21;
+      fd_val = ((AND) ccr_val (0b00000000010000000000000000000000)) >> 22;
       state1 = (if fi_val = 1 then flush_instr_cache state else state)
   in
   if fd_val = 1 then flush_data_cache state1 else state1"
 
 definition get_delayed_pool :: "('a) sparc_state \<Rightarrow> delayed_write_pool"
 where "get_delayed_pool state \<equiv> dwrite state"
 
 definition exe_pool :: "(int \<times> reg_type \<times> CPU_register) \<Rightarrow> (int \<times> reg_type \<times> CPU_register)"
 where "exe_pool w \<equiv> case w of (n,v,c) \<Rightarrow> ((n-1),v,c)"
 
 text \<open>Minus 1 to the delayed count for all the members in the set. 
         Assuming all members have delay > 0.\<close>
 primrec delayed_pool_minus :: "delayed_write_pool \<Rightarrow> delayed_write_pool"
 where
 "delayed_pool_minus [] = []"
 |
 "delayed_pool_minus (x#xs) = (exe_pool x)#(delayed_pool_minus xs)"
 
 text \<open>Add a delayed-write to the pool.\<close>
 definition delayed_pool_add :: "(int \<times> reg_type \<times> CPU_register) \<Rightarrow> 
                                 ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where 
 "delayed_pool_add dw s \<equiv>
   let (i,v,cr) = dw in
   if i = 0 then \<comment> \<open>Write the value to the register immediately.\<close>
     cpu_reg_mod v cr s
   else \<comment> \<open>Add to delayed write pool.\<close>
     let curr_pool = get_delayed_pool s in
     s\<lparr>dwrite := curr_pool@[dw]\<rparr>"
 
 text \<open>Remove a delayed-write from the pool. 
         Assume that the delayed-write to be removed has delay 0.
         i.e., it has been executed.\<close>
 definition delayed_pool_rm :: "(int \<times> reg_type \<times> CPU_register) \<Rightarrow> 
                                ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where
 "delayed_pool_rm dw s \<equiv>
   let curr_pool = get_delayed_pool s in
   case dw of (n,v,cr) \<Rightarrow> 
     (if n = 0 then
       s\<lparr>dwrite := List.remove1 dw curr_pool\<rparr>
      else s)
 "
 
 text \<open>Remove all the entries with delay = 0, i.e., those that are written.\<close>
 primrec delayed_pool_rm_written :: "delayed_write_pool \<Rightarrow> delayed_write_pool"
 where
 "delayed_pool_rm_written [] = []"
 |
 "delayed_pool_rm_written (x#xs) = 
   (if fst x = 0 then delayed_pool_rm_written xs else x#(delayed_pool_rm_written xs))    
 "
 
 definition annul_val :: "('a) sparc_state \<Rightarrow> bool"
 where "annul_val state \<equiv> get_annul (state_var state)"
 
 definition annul_mod :: "bool \<Rightarrow> ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where "annul_mod b s \<equiv> s\<lparr>state_var := write_annul b (state_var s)\<rparr>"
 
 definition reset_trap_val :: "('a) sparc_state \<Rightarrow> bool"
 where "reset_trap_val state \<equiv> get_reset_trap (state_var state)"
 
 definition reset_trap_mod :: "bool \<Rightarrow> ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where "reset_trap_mod b s \<equiv> s\<lparr>state_var := write_reset_trap b (state_var s)\<rparr>"
 
 definition exe_mode_val :: "('a) sparc_state \<Rightarrow> bool"
 where "exe_mode_val state \<equiv> get_exe_mode (state_var state)"
 
 definition exe_mode_mod :: "bool \<Rightarrow> ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where "exe_mode_mod b s \<equiv> s\<lparr>state_var := write_exe_mode b (state_var s)\<rparr>"
 
 definition reset_mode_val :: "('a) sparc_state \<Rightarrow> bool"
 where "reset_mode_val state \<equiv> get_reset_mode (state_var state)"
 
 definition reset_mode_mod :: "bool \<Rightarrow> ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where "reset_mode_mod b s \<equiv> s\<lparr>state_var := write_reset_mode b (state_var s)\<rparr>"
 
 definition err_mode_val :: "('a) sparc_state \<Rightarrow> bool"
 where "err_mode_val state \<equiv> get_err_mode (state_var state)"
 
 definition err_mode_mod :: "bool \<Rightarrow> ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where "err_mode_mod b s \<equiv> s\<lparr>state_var := write_err_mode b (state_var s)\<rparr>"
 
 definition ticc_trap_type_val :: "('a) sparc_state \<Rightarrow> word7"
 where "ticc_trap_type_val state \<equiv> get_ticc_trap_type (state_var state)"
 
 definition ticc_trap_type_mod :: "word7 \<Rightarrow> ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where "ticc_trap_type_mod w s \<equiv> s\<lparr>state_var := write_ticc_trap_type w (state_var s)\<rparr>"
 
 definition interrupt_level_val :: "('a) sparc_state \<Rightarrow> word3"
 where "interrupt_level_val state \<equiv> get_interrupt_level (state_var state)"
 
 definition interrupt_level_mod :: "word3 \<Rightarrow> ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where "interrupt_level_mod w s \<equiv> s\<lparr>state_var := write_interrupt_level w (state_var s)\<rparr>"
 
 definition store_barrier_pending_val :: "('a) sparc_state \<Rightarrow> bool"
 where "store_barrier_pending_val state \<equiv> 
   get_store_barrier_pending (state_var state)"
 
 definition store_barrier_pending_mod :: "bool \<Rightarrow> 
   ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where "store_barrier_pending_mod w s \<equiv>
   s\<lparr>state_var := write_store_barrier_pending w (state_var s)\<rparr>"
 
 definition pb_block_ldst_byte_val :: "virtua_address \<Rightarrow> ('a) sparc_state
   \<Rightarrow> bool"
 where "pb_block_ldst_byte_val add state \<equiv>
   (atm_ldst_byte (state_var state)) add"
 
 definition pb_block_ldst_byte_mod :: "virtua_address \<Rightarrow> bool \<Rightarrow> 
   ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where "pb_block_ldst_byte_mod add b s \<equiv>
   s\<lparr>state_var := ((state_var s)
     \<lparr>atm_ldst_byte := (atm_ldst_byte (state_var s))(add := b)\<rparr>)\<rparr>"
 
 text \<open>We only read the address such that add mod 4 = 0. 
   add mod 4 represents the current word.\<close>
 definition pb_block_ldst_word_val :: "virtua_address \<Rightarrow> ('a) sparc_state
   \<Rightarrow> bool"
 where "pb_block_ldst_word_val add state \<equiv>
-  let add0 = (bitAND add (0b11111111111111111111111111111100::word32)) in
+  let add0 = ((AND) add (0b11111111111111111111111111111100::word32)) in
   (atm_ldst_word (state_var state)) add0"
 
 text \<open>We only write the address such that add mod 4 = 0.
   add mod 4 represents the current word.\<close>
 definition pb_block_ldst_word_mod :: "virtua_address \<Rightarrow> bool \<Rightarrow> 
   ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where "pb_block_ldst_word_mod add b s \<equiv>
-  let add0 = (bitAND add (0b11111111111111111111111111111100::word32)) in
+  let add0 = ((AND) add (0b11111111111111111111111111111100::word32)) in
   s\<lparr>state_var := ((state_var s)
     \<lparr>atm_ldst_word := (atm_ldst_word (state_var s))(add0 := b)\<rparr>)\<rparr>"
 
 definition get_trap_set :: "('a) sparc_state \<Rightarrow> Trap set"
 where "get_trap_set state \<equiv> (traps state)"
 
 definition add_trap_set :: "Trap \<Rightarrow> ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where "add_trap_set t s \<equiv> s\<lparr>traps := (traps s) \<union> {t}\<rparr>"
 
 definition emp_trap_set :: "('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where "emp_trap_set s \<equiv> s\<lparr>traps := {}\<rparr>"
 
 definition state_undef:: "('a) sparc_state \<Rightarrow> bool"
 where "state_undef state \<equiv> (undef state)"
 
 text \<open>The \<open>memory_read\<close> interface that conforms with the SPARCv8 manual.\<close>
 definition memory_read :: "asi_type \<Rightarrow> virtua_address \<Rightarrow> 
                            ('a) sparc_state \<Rightarrow> 
                            ((word32 option) \<times> ('a) sparc_state)"
 where "memory_read asi addr state \<equiv>
   let asi_int = uint asi in \<comment> \<open>See Page 25 and 35 for ASI usage in LEON 3FT.\<close>
   if asi_int = 1 then \<comment> \<open>Forced cache miss.\<close>
     \<comment> \<open>Directly read from memory.\<close>
     let r1 = load_word_mem state addr (word_of_int 8) in
     if r1 = None then
       let r2 = load_word_mem state addr (word_of_int 10) in
       if r2 = None then
         (None,state)
       else (r2,state)
     else (r1,state)
   else if asi_int = 2 then \<comment> \<open>System registers.\<close>
     \<comment> \<open>See Table 19, Page 34 for System Register address map in LEON 3FT.\<close>
     if uint addr = 0 then \<comment> \<open>Cache control register.\<close>
       ((Some (sys_reg_val CCR state)), state)
     else if uint addr = 8 then \<comment> \<open>Instruction cache configuration register.\<close>
       ((Some (sys_reg_val ICCR state)), state)
     else if uint addr = 12 then \<comment> \<open>Data cache configuration register.\<close>
       ((Some (sys_reg_val DCCR state)), state)
     else \<comment> \<open>Invalid address.\<close>
       (None, state)
   else if asi_int \<in> {8,9} then \<comment> \<open>Access instruction memory.\<close>
     let ccr_val = (sys_reg state) CCR in
     if ccr_val AND 1 \<noteq> 0 then \<comment> \<open>Cache is enabled. Update cache.\<close>
     \<comment> \<open>We don't go through the tradition, i.e., read from cache first,\<close>
     \<comment> \<open>if the address is not cached, then read from memory,\<close>
     \<comment> \<open>because performance is not an issue here.\<close>
     \<comment> \<open>Thus we directly read from memory and update the cache.\<close>
       let data = load_word_mem state addr asi in
       case data of
       Some w \<Rightarrow> (Some w,(add_instr_cache state addr w (0b1111::word4)))
       |None \<Rightarrow> (None, state)
     else \<comment> \<open>Cache is disabled. Just read from memory.\<close>
       ((load_word_mem state addr asi),state)
   else if asi_int \<in> {10,11} then \<comment> \<open>Access data memory.\<close>
     let ccr_val = (sys_reg state) CCR in
     if ccr_val AND 1 \<noteq> 0 then \<comment> \<open>Cache is enabled. Update cache.\<close>
     \<comment> \<open>We don't go through the tradition, i.e., read from cache first,\<close>
     \<comment> \<open>if the address is not cached, then read from memory,\<close>
     \<comment> \<open>because performance is not an issue here.\<close>
     \<comment> \<open>Thus we directly read from memory and update the cache.\<close>
       let data = load_word_mem state addr asi in
       case data of
       Some w \<Rightarrow> (Some w,(add_data_cache state addr w (0b1111::word4)))
       |None \<Rightarrow> (None, state)
     else \<comment> \<open>Cache is disabled. Just read from memory.\<close>
       ((load_word_mem state addr asi),state)
   \<comment> \<open>We don't access instruction cache tag. i.e., \<open>asi = 12\<close>.\<close>
   else if asi_int = 13 then \<comment> \<open>Read instruction cache data.\<close>
     let cache_result = read_instr_cache state addr in
     case cache_result of
     Some w \<Rightarrow> (Some w, state)
     |None \<Rightarrow> (None, state)
   \<comment> \<open>We don't access data cache tag. i.e., \<open>asi = 14\<close>.\<close>
   else if asi_int = 15 then \<comment> \<open>Read data cache data.\<close>
     let cache_result = read_data_cache state addr in
     case cache_result of
     Some w \<Rightarrow> (Some w, state)
     |None \<Rightarrow> (None, state)
   else if asi_int \<in> {16,17} then \<comment> \<open>Flush entire instruction/data cache.\<close>
     (None, state) \<comment> \<open>Has no effect for memory read.\<close>
   else if asi_int \<in> {20,21} then \<comment> \<open>MMU diagnostic cache access.\<close>
     (None, state) \<comment> \<open>Not considered in this model.\<close>
   else if asi_int = 24 then \<comment> \<open>Flush cache and TLB in LEON3.\<close>
     \<comment> \<open>But is not used for memory read.\<close>
     (None, state)
   else if asi_int = 25 then \<comment> \<open>MMU registers.\<close>
     \<comment> \<open>Treat MMU registers as memory addresses that are not in the main memory.\<close>
     ((mmu_reg_val (mmu state) addr), state) 
   else if asi_int = 28 then \<comment> \<open>MMU bypass.\<close>
     \<comment> \<open>Directly use addr as a physical address.\<close>
     \<comment> \<open>Append 0000 in the front of addr.\<close>
     \<comment> \<open>In this case, (ucast addr) suffices.\<close>
     ((mem_val_w32 asi (ucast addr) state), state)
   else if asi_int = 29 then \<comment> \<open>MMU diagnostic access.\<close>
     (None, state) \<comment> \<open>Not considered in this model.\<close>
   else \<comment> \<open>Not considered in this model.\<close>
     (None, state)
 "
 
 text \<open>Get the value of a memory address and an ASI.\<close>
 definition mem_val_asi:: "asi_type \<Rightarrow> phys_address \<Rightarrow> 
                       ('a) sparc_state \<Rightarrow> mem_val_type option"
 where "mem_val_asi asi add state \<equiv> (mem state) asi add"
 
 text \<open>Check if an address is used in ASI 9 or 11.\<close>
 definition sup_addr :: "phys_address \<Rightarrow> ('a) sparc_state \<Rightarrow> bool"
 where
 "sup_addr addr state \<equiv>
-  let addr' = bitAND addr 0b111111111111111111111111111111111100;
-      addr0 = bitOR addr' 0b000000000000000000000000000000000000;
-      addr1 = bitOR addr' 0b000000000000000000000000000000000001;
-      addr2 = bitOR addr' 0b000000000000000000000000000000000010;
-      addr3 = bitOR addr' 0b000000000000000000000000000000000011;
+  let addr' = (AND) addr 0b111111111111111111111111111111111100;
+      addr0 = (OR) addr' 0b000000000000000000000000000000000000;
+      addr1 = (OR) addr' 0b000000000000000000000000000000000001;
+      addr2 = (OR) addr' 0b000000000000000000000000000000000010;
+      addr3 = (OR) addr' 0b000000000000000000000000000000000011;
       r0 = mem_val_asi 9 addr0 state;
       r1 = mem_val_asi 9 addr1 state;
       r2 = mem_val_asi 9 addr2 state;
       r3 = mem_val_asi 9 addr3 state;
       r4 = mem_val_asi 11 addr0 state;
       r5 = mem_val_asi 11 addr1 state;
       r6 = mem_val_asi 11 addr2 state;
       r7 = mem_val_asi 11 addr3 state
   in
   if r0 = None \<and> r1 = None \<and> r2 = None \<and> r3 = None \<and>
      r4 = None \<and> r5 = None \<and> r6 = None \<and> r7 = None
   then False
   else True
 "
 
 text \<open>The \<open>memory_write\<close> interface that conforms with SPARCv8 manual.\<close>
 text \<open>LEON3 forbids user to write an address in ASI 9 and 11.\<close>
 definition memory_write_asi :: "asi_type \<Rightarrow> virtua_address \<Rightarrow> word4 \<Rightarrow> word32 \<Rightarrow> 
                             ('a) sparc_state \<Rightarrow> 
                             ('a) sparc_state option"
 where
 "memory_write_asi asi addr byte_mask data_w32 state \<equiv> 
   let asi_int = uint asi; \<comment> \<open>See Page 25 and 35 for ASI usage in LEON 3FT.\<close>
       psr_val = cpu_reg_val PSR state;
       s_val = get_S psr_val
   in 
   if asi_int = 1 then \<comment> \<open>Forced cache miss.\<close>
     \<comment> \<open>Directly write to memory.\<close>
     \<comment> \<open>Assuming writing into \<open>asi = 10\<close>.\<close>
     store_word_mem state addr data_w32 byte_mask (word_of_int 10) 
   else if asi_int = 2 then \<comment> \<open>System registers.\<close>
     \<comment> \<open>See Table 19, Page 34 for System Register address map in LEON 3FT.\<close>
     if uint addr = 0 then \<comment> \<open>Cache control register.\<close>
       let s1 = (sys_reg_mod data_w32 CCR state) in
       \<comment> \<open>Flush the instruction cache if FI of CCR is 1;\<close>
       \<comment> \<open>flush the data cache if FD of CCR is 1.\<close>
       Some (ccr_flush s1)
     else if uint addr = 8 then \<comment> \<open>Instruction cache configuration register.\<close>
       Some (sys_reg_mod data_w32 ICCR state)
     else if uint addr = 12 then \<comment> \<open>Data cache configuration register.\<close>
       Some (sys_reg_mod data_w32 DCCR state)
     else \<comment> \<open>Invalid address.\<close>
       None
   else if asi_int \<in> {8,9} then \<comment> \<open>Access instruction memory.\<close>
     \<comment> \<open>Write to memory. LEON3 does write-through. Both cache and the memory are updated.\<close>
     let ns = add_instr_cache state addr data_w32 byte_mask in
     store_word_mem ns addr data_w32 byte_mask asi
   else if asi_int \<in> {10,11} then \<comment> \<open>Access data memory.\<close>
     \<comment> \<open>Write to memory. LEON3 does write-through. Both cache and the memory are updated.\<close>
     let ns = add_data_cache state addr data_w32 byte_mask in
     store_word_mem ns addr data_w32 byte_mask asi
   \<comment> \<open>We don't access instruction cache tag. i.e., \<open>asi = 12\<close>.\<close>
   else if asi_int = 13 then \<comment> \<open>Write instruction cache data.\<close>
     Some (add_instr_cache state addr data_w32 (0b1111::word4))
   \<comment> \<open>We don't access data cache tag. i.e., asi = 14.\<close>
   else if asi_int = 15 then \<comment> \<open>Write data cache data.\<close>
     Some (add_data_cache state addr data_w32 (0b1111::word4))
   else if asi_int = 16 then \<comment> \<open>Flush instruction cache.\<close>
     Some (flush_instr_cache state)
   else if asi_int = 17 then \<comment> \<open>Flush data cache.\<close>
     Some (flush_data_cache state)
   else if asi_int \<in> {20,21} then \<comment> \<open>MMU diagnostic cache access.\<close>
     None \<comment> \<open>Not considered in this model.\<close>
   else if asi_int = 24 then \<comment> \<open>Flush TLB and cache in LEON3.\<close>
     \<comment> \<open>We don't consider TLB here.\<close>
     Some (flush_cache_all state)
   else if asi_int = 25 then \<comment> \<open>MMU registers.\<close>
     \<comment> \<open>Treat MMU registers as memory addresses that are not in the main memory.\<close>
     let mmu_state' = mmu_reg_mod (mmu state) addr data_w32 in
     case mmu_state' of
     Some mmus \<Rightarrow> Some (state\<lparr>mmu := mmus\<rparr>)
     |None \<Rightarrow> None 
   else if asi_int = 28 then \<comment> \<open>MMU bypass.\<close>
     \<comment> \<open>Write to virtual address as physical address.\<close>
     \<comment> \<open>Append 0000 in front of addr.\<close>
     Some (mem_mod_w32 asi (ucast addr) byte_mask data_w32 state)
   else if asi_int = 29 then \<comment> \<open>MMU diagnostic access.\<close>
     None \<comment> \<open>Not considered in this model.\<close>
   else \<comment> \<open>Not considered in this model.\<close>
     None
 "
 
 definition memory_write :: "asi_type \<Rightarrow> virtua_address \<Rightarrow> word4 \<Rightarrow> word32 \<Rightarrow> 
                             ('a) sparc_state \<Rightarrow> 
                             ('a) sparc_state option"
 where
 "memory_write asi addr byte_mask data_w32 state \<equiv> 
   let result = memory_write_asi asi addr byte_mask data_w32 state in
   case result of 
   None \<Rightarrow> None
   | Some s1 \<Rightarrow> Some (store_barrier_pending_mod False s1)"
 
 text \<open>monad for sequential operations over the register representation\<close>
 type_synonym ('a,'e) sparc_state_monad = "(('a) sparc_state,'e) det_monad" 
 
 text \<open>Given a word32 value, a cpu register, 
         write the value in the cpu register.\<close>
 definition write_cpu :: "word32 \<Rightarrow> CPU_register \<Rightarrow> ('a,unit) sparc_state_monad"
 where "write_cpu w cr \<equiv>
   do
     modify (\<lambda>s. (cpu_reg_mod w cr s));
     return ()
   od"
 
 definition write_cpu_tt :: "word8 \<Rightarrow> ('a,unit) sparc_state_monad"
 where "write_cpu_tt w \<equiv>
   do
     tbr_val \<leftarrow> gets (\<lambda>s. (cpu_reg_val TBR s));
     new_tbr_val \<leftarrow> gets (\<lambda>s. (write_tt w tbr_val));
     write_cpu new_tbr_val TBR;
     return ()
   od"
 
 text \<open>Given a word32 value, a word4 window, a user register, 
         write the value in the user register. 
         N.B. CWP is a 5 bit value, but we only use the last 4 bits,
         since there are only 16 windows.\<close>
 definition write_reg :: "word32 \<Rightarrow> ('a::len0) word \<Rightarrow> user_reg_type \<Rightarrow> 
   ('a,unit) sparc_state_monad"
 where "write_reg w win ur \<equiv>
   do
     modify (\<lambda>s.(user_reg_mod w win ur s));
     return ()
   od"
 
 definition set_annul :: "bool \<Rightarrow> ('a,unit) sparc_state_monad"
 where "set_annul b \<equiv>
   do
     modify (\<lambda>s. (annul_mod b s));
     return ()
   od"
 
 definition set_reset_trap :: "bool \<Rightarrow> ('a,unit) sparc_state_monad"
 where "set_reset_trap b \<equiv>
   do
     modify (\<lambda>s. (reset_trap_mod b s));
     return ()
   od"
 
 definition set_exe_mode :: "bool \<Rightarrow> ('a,unit) sparc_state_monad"
 where "set_exe_mode b \<equiv>
   do
     modify (\<lambda>s. (exe_mode_mod b s));
     return ()
   od"
 
 definition set_reset_mode :: "bool \<Rightarrow> ('a,unit) sparc_state_monad"
 where "set_reset_mode b \<equiv>
   do
     modify (\<lambda>s. (reset_mode_mod b s));
     return ()
   od" 
 
 definition set_err_mode :: "bool \<Rightarrow> ('a,unit) sparc_state_monad"
 where "set_err_mode b \<equiv>
   do
     modify (\<lambda>s. (err_mode_mod b s));
     return ()
   od"
 
 fun get_delayed_0 :: "(int \<times> reg_type \<times> CPU_register) list \<Rightarrow> 
   (int \<times> reg_type \<times> CPU_register) list"
 where
 "get_delayed_0 [] = []"
 |
 "get_delayed_0 (x # xs) = 
   (if fst x = 0 then x # (get_delayed_0 xs)
   else get_delayed_0 xs)"
 
 text \<open>Get a list of delayed-writes with delay 0.\<close>
 definition get_delayed_write :: "delayed_write_pool \<Rightarrow> (int \<times> reg_type \<times> CPU_register) list"
 where
 "get_delayed_write dwp \<equiv> get_delayed_0 dwp"
 
 definition delayed_write :: "(int \<times> reg_type \<times> CPU_register) \<Rightarrow> ('a) sparc_state \<Rightarrow>
   ('a) sparc_state"
 where "delayed_write dw s \<equiv>
   let (n,v,r) = dw in
   if n = 0 then
     cpu_reg_mod v r s
   else s"
 
 primrec delayed_write_all :: "(int \<times> reg_type \<times> CPU_register) list \<Rightarrow>
   ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where "delayed_write_all [] s = s"
 |"delayed_write_all (x # xs) s =
   delayed_write_all xs (delayed_write x s)"
 
 primrec delayed_pool_rm_list :: "(int \<times> reg_type \<times> CPU_register) list\<Rightarrow> 
   ('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where "delayed_pool_rm_list [] s = s"
 |"delayed_pool_rm_list (x # xs) s =
   delayed_pool_rm_list xs (delayed_pool_rm x s)"
 
 definition delayed_pool_write :: "('a) sparc_state \<Rightarrow> ('a) sparc_state"
 where "delayed_pool_write s \<equiv>
   let dwp0 = get_delayed_pool s;
       dwp1 = delayed_pool_minus dwp0;
       wl = get_delayed_write dwp1;
       s1 = delayed_write_all wl s;
       s2 = delayed_pool_rm_list wl s1 
   in s2"
 
 definition raise_trap :: "Trap \<Rightarrow> ('a,unit) sparc_state_monad"
 where "raise_trap t \<equiv>
   do
     modify (\<lambda>s. (add_trap_set t s));
     return ()
   od"
 
 end
 
diff --git a/thys/SPARCv8/SparcModel_MMU/Sparc_Types.thy b/thys/SPARCv8/SparcModel_MMU/Sparc_Types.thy
--- a/thys/SPARCv8/SparcModel_MMU/Sparc_Types.thy
+++ b/thys/SPARCv8/SparcModel_MMU/Sparc_Types.thy
@@ -1,791 +1,791 @@
 (*
  * Copyright 2016, NTU
  *
  * This software may be distributed and modified according to the terms of
  * the BSD 2-Clause license. Note that NO WARRANTY is provided.
  * See "LICENSE_BSD2.txt" for details.
  *
  * Author: Zhe Hou, David Sanan. 
  *)
 
 section \<open>SPARC V8 architecture CPU model\<close>
 theory Sparc_Types    
 imports Main "../lib/WordDecl" 
 begin
 
 text \<open>The following type definitions are taken from David Sanan's 
 definitions for SPARC machines.\<close>
 
 type_synonym machine_word = word32
 type_synonym byte = word8
 type_synonym phys_address = word36
 
 type_synonym virtua_address = word32
 type_synonym page_address = word24
 type_synonym offset = word12
 
 type_synonym table_entry = word8
 
 definition page_size :: "word32" where "page_size \<equiv> 4096"
 
 type_synonym virtua_page_address = word20
 type_synonym context_type = word8
 
 type_synonym word_length_t1 = word_length8
 type_synonym word_length_t2 = word_length6
 type_synonym word_length_t3 = word_length6
 type_synonym word_length_offset = word_length12
 type_synonym word_length_page = word_length24
 type_synonym word_length_phys_address = word_length36
 type_synonym word_length_virtua_address = word_length32
 type_synonym word_length_entry_type = word_length2
 type_synonym word_length_machine_word = word_length32
 
 definition length_machine_word :: "nat" 
  where "length_machine_word \<equiv> LENGTH(word_length_machine_word)"
 
 text_raw \<open>\newpage\<close>
 
 section \<open>CPU Register Definitions\<close>
 
 text\<open>
  The definitions below come from the SPARC Architecture Manual, Version 8.
  The LEON3 processor has been certified SPARC V8 conformant (2005).
 \<close>
 
 definition leon3khz ::"word32"
 where
 "leon3khz \<equiv> 33000"
 
 text \<open>The following type definitions for MMU is taken from 
 David Sanan's definitions for MMU.\<close>
 
 text\<open>
   The definitions below come from the UT699 LEON 3FT/SPARC V8 Microprocessor Functional Manual, 
    Aeroflex, June 20, 2012, p35.
 \<close>
 datatype MMU_register
  = CR    \<comment> \<open>Control Register\<close>
  | CTP   \<comment> \<open>ConText Pointer register\<close>
  | CNR   \<comment> \<open>Context Register\<close>
  | FTSR   \<comment> \<open>Fault Status Register\<close>
  | FAR   \<comment> \<open>Fault Address Register\<close>
 
 lemma MMU_register_induct: 
   "P CR \<Longrightarrow> P CTP \<Longrightarrow> P CNR \<Longrightarrow> P FTSR \<Longrightarrow> P FAR 
    \<Longrightarrow> P x"
   by (cases x) auto
 
 lemma UNIV_MMU_register [no_atp]: "UNIV = {CR, CTP, CNR, FTSR, FAR}"
    apply (safe)
    apply (case_tac x)
    apply (auto intro:MMU_register_induct)
   done
 
 
 instantiation MMU_register :: enum begin
 
 definition "enum_MMU_register = [ CR, CTP, CNR, FTSR, FAR ]"
 
 definition
   "enum_all_MMU_register P \<longleftrightarrow> P CR \<and> P CTP \<and> P CNR \<and> P FTSR \<and> P FAR "
 definition
   "enum_ex_MMU_register P \<longleftrightarrow> P CR \<or> P CTP \<or> P CNR \<or> P FTSR \<or> P FAR"
 
  instance proof
   qed (simp_all only: enum_MMU_register_def enum_all_MMU_register_def 
                       enum_ex_MMU_register_def UNIV_MMU_register, simp_all)
 end
 type_synonym MMU_context = "MMU_register \<Rightarrow> machine_word"
 
 text \<open>\<open>PTE_flags\<close> is the last 8 bits of a PTE. See page 242 of SPARCv8 manual.
 \<^item> C - bit 7
 \<^item> M - bit 6,
 \<^item> R - bit 5
 \<^item> ACC - bit 4~2
 \<^item> ET - bit 1~0.\<close>
 
 type_synonym PTE_flags = word8
 
 text \<open>
   @{term CPU_register} datatype is an enumeration with the CPU registers defined in the SPARC V8 
   architecture.
 \<close>
 datatype CPU_register = 
    PSR   \<comment> \<open>Processor State Register\<close>
  | WIM   \<comment> \<open>Window Invalid Mask\<close>
  | TBR   \<comment> \<open>Trap Base Register\<close>
  | Y     \<comment> \<open>Multiply/Divide Register\<close>
  | PC    \<comment> \<open>Program Counter\<close>
  | nPC   \<comment> \<open>next Program Counter\<close>
  | DTQ   \<comment> \<open>Deferred-Trap Queue\<close>
  | FSR   \<comment> \<open>Floating-Point State Register\<close>
  | FQ    \<comment> \<open>Floating-Point Deferred-Trap Queue\<close>
  | CSR   \<comment> \<open>Coprocessor State Register\<close>
  | CQ    \<comment> \<open>Coprocessor Deferred-Trap Queue\<close>
  (*| CCR   --   "Cache Control Register"*)
  | ASR "word5"  \<comment> \<open>Ancillary State Register\<close>
 
 text \<open>The following two functions are dummies since we will not use 
         ASRs. Future formalisation may add more details to this.\<close>
 
 definition privileged_ASR :: "word5 \<Rightarrow> bool"
 where
 "privileged_ASR r \<equiv> False
 "
 
 definition illegal_instruction_ASR :: "word5 \<Rightarrow> bool"
 where
 "illegal_instruction_ASR r \<equiv> False
 "
 
 definition get_tt :: "word32 \<Rightarrow> word8"
 where
 "get_tt tbr \<equiv>
-  ucast ((bitAND tbr 0b00000000000000000000111111110000) >> 4)
+  ucast (((AND) tbr 0b00000000000000000000111111110000) >> 4)
 "
 
 text \<open>Write the tt field of the TBR register. 
         Return the new value of TBR.\<close>
 definition write_tt :: "word8 \<Rightarrow> word32 \<Rightarrow> word32"
 where
 "write_tt new_tt_val tbr_val \<equiv>
-  let tmp = bitAND tbr_val 0b111111111111111111111000000001111 in
-      bitOR tmp (((ucast new_tt_val)::word32) << 4)
+  let tmp = (AND) tbr_val 0b111111111111111111111000000001111 in
+      (OR) tmp (((ucast new_tt_val)::word32) << 4)
 "
 
-text \<open>Get the nth bit of WIM. This equals (bitAND WIM $2^n$). 
+text \<open>Get the nth bit of WIM. This equals ((AND) WIM $2^n$). 
         N.B. the first bit of WIM is the 0th bit.\<close>
 definition get_WIM_bit :: "nat \<Rightarrow> word32 \<Rightarrow> word1"
 where
 "get_WIM_bit n wim \<equiv>
   let mask = ((ucast (0b1::word1))::word32) << n in
-  ucast ((bitAND mask wim) >> n)
+  ucast (((AND) mask wim) >> n)
 "
 
 definition get_CWP :: "word32 \<Rightarrow> word5"
 where
 "get_CWP psr \<equiv> 
-  ucast (bitAND psr 0b00000000000000000000000000011111) 
+  ucast ((AND) psr 0b00000000000000000000000000011111) 
 "
 
 definition get_ET :: "word32 \<Rightarrow> word1"
 where
 "get_ET psr \<equiv> 
-  ucast ((bitAND psr 0b00000000000000000000000000100000) >> 5) 
+  ucast (((AND) psr 0b00000000000000000000000000100000) >> 5) 
 "
 
 definition get_PIL :: "word32 \<Rightarrow> word4"
 where
 "get_PIL psr \<equiv> 
-  ucast ((bitAND psr 0b00000000000000000000111100000000) >> 8) 
+  ucast (((AND) psr 0b00000000000000000000111100000000) >> 8) 
 "
 
 definition get_PS :: "word32 \<Rightarrow> word1"
 where
 "get_PS psr \<equiv> 
-  ucast ((bitAND psr 0b00000000000000000000000001000000) >> 6) 
+  ucast (((AND) psr 0b00000000000000000000000001000000) >> 6) 
 "
 
 definition get_S :: "word32 \<Rightarrow> word1"
 where
 "get_S psr \<equiv> 
-  \<^cancel>\<open>ucast ((bitAND psr 0b00000000000000000000000010000000) >> 7)\<close>
-  if (bitAND psr (0b00000000000000000000000010000000::word32)) = 0 then 0
+  \<^cancel>\<open>ucast (((AND) psr 0b00000000000000000000000010000000) >> 7)\<close>
+  if ((AND) psr (0b00000000000000000000000010000000::word32)) = 0 then 0
   else 1
 "
 
 definition get_icc_N :: "word32 \<Rightarrow> word1"
 where
 "get_icc_N psr \<equiv>
-  ucast ((bitAND psr 0b00000000100000000000000000000000) >> 23)
+  ucast (((AND) psr 0b00000000100000000000000000000000) >> 23)
 "
 
 definition get_icc_Z :: "word32 \<Rightarrow> word1"
 where
 "get_icc_Z psr \<equiv>
-  ucast ((bitAND psr 0b00000000010000000000000000000000) >> 22)
+  ucast (((AND) psr 0b00000000010000000000000000000000) >> 22)
 "
 
 definition get_icc_V :: "word32 \<Rightarrow> word1"
 where
 "get_icc_V psr \<equiv>
-  ucast ((bitAND psr 0b00000000001000000000000000000000) >> 21)
+  ucast (((AND) psr 0b00000000001000000000000000000000) >> 21)
 "
 
 definition get_icc_C :: "word32 \<Rightarrow> word1"
 where
 "get_icc_C psr \<equiv>
-  ucast ((bitAND psr 0b00000000000100000000000000000000) >> 20)
+  ucast (((AND) psr 0b00000000000100000000000000000000) >> 20)
 "
 
 definition update_S :: "word1 \<Rightarrow> word32 \<Rightarrow> word32"
 where
 "update_S s_val psr_val \<equiv>
-  let tmp0 = bitAND psr_val 0b11111111111111111111111101111111 in
-  bitOR tmp0 (((ucast s_val)::word32) << 7)
+  let tmp0 = (AND) psr_val 0b11111111111111111111111101111111 in
+  (OR) tmp0 (((ucast s_val)::word32) << 7)
 "
 
 text \<open>Update the CWP field of PSR. 
         Return the new value of PSR.\<close>
 definition update_CWP :: "word5 \<Rightarrow> word32 \<Rightarrow> word32"
 where
 "update_CWP cwp_val psr_val \<equiv>
-  let tmp0 = bitAND psr_val (0b11111111111111111111111111100000::word32);
+  let tmp0 = (AND) psr_val (0b11111111111111111111111111100000::word32);
       s_val = ((ucast (get_S psr_val))::word1)
   in
   if s_val = 0 then  
-    bitAND (bitOR tmp0 ((ucast cwp_val)::word32)) (0b11111111111111111111111101111111::word32)
+    (AND) ((OR) tmp0 ((ucast cwp_val)::word32)) (0b11111111111111111111111101111111::word32)
   else
-    bitOR (bitOR tmp0 ((ucast cwp_val)::word32)) (0b00000000000000000000000010000000::word32)
+    (OR) ((OR) tmp0 ((ucast cwp_val)::word32)) (0b00000000000000000000000010000000::word32)
 "
 
 text \<open>Update the the ET, CWP, and S fields of PSR. 
         Return the new value of PSR.\<close>
 definition update_PSR_rett :: "word5 \<Rightarrow> word1 \<Rightarrow> word1 \<Rightarrow> word32 \<Rightarrow> word32"
 where
 "update_PSR_rett cwp_val et_val s_val psr_val \<equiv>
-  let tmp0 = bitAND psr_val 0b11111111111111111111111101000000;
-      tmp1 = bitOR tmp0 ((ucast cwp_val)::word32);
-      tmp2 = bitOR tmp1 (((ucast et_val)::word32) << 5); 
-      tmp3 = bitOR tmp2 (((ucast s_val)::word32) << 7)
+  let tmp0 = (AND) psr_val 0b11111111111111111111111101000000;
+      tmp1 = (OR) tmp0 ((ucast cwp_val)::word32);
+      tmp2 = (OR) tmp1 (((ucast et_val)::word32) << 5); 
+      tmp3 = (OR) tmp2 (((ucast s_val)::word32) << 7)
   in  
   tmp3
 "
 
 definition update_PSR_exe_trap :: "word5 \<Rightarrow> word1 \<Rightarrow> word1 \<Rightarrow> word32 \<Rightarrow> word32"
 where
 "update_PSR_exe_trap cwp_val et_val ps_val psr_val \<equiv>
-  let tmp0 = bitAND psr_val 0b11111111111111111111111110000000;
-      tmp1 = bitOR tmp0 ((ucast cwp_val)::word32);
-      tmp2 = bitOR tmp1 (((ucast et_val)::word32) << 5); 
-      tmp3 = bitOR tmp2 (((ucast ps_val)::word32) << 6)
+  let tmp0 = (AND) psr_val 0b11111111111111111111111110000000;
+      tmp1 = (OR) tmp0 ((ucast cwp_val)::word32);
+      tmp2 = (OR) tmp1 (((ucast et_val)::word32) << 5); 
+      tmp3 = (OR) tmp2 (((ucast ps_val)::word32) << 6)
   in  
   tmp3
 "
 
 text \<open>Update the N, Z, V, C fields of PSR. 
         Return the new value of PSR.\<close>
 definition update_PSR_icc :: "word1 \<Rightarrow> word1 \<Rightarrow> word1 \<Rightarrow> word1 \<Rightarrow> word32 \<Rightarrow> word32"
 where
 "update_PSR_icc n_val z_val v_val c_val psr_val \<equiv>
   let
       n_val_32 = if n_val = 0 then 0 
                  else       (0b00000000100000000000000000000000::word32); 
       z_val_32 = if z_val = 0 then 0 
                  else       (0b00000000010000000000000000000000::word32); 
       v_val_32 = if v_val = 0 then 0 
                  else       (0b00000000001000000000000000000000::word32);
       c_val_32 = if c_val = 0 then 0 
                  else       (0b00000000000100000000000000000000::word32);
-      tmp0 = bitAND psr_val (0b11111111000011111111111111111111::word32);
-      tmp1 = bitOR tmp0 n_val_32;
-      tmp2 = bitOR tmp1 z_val_32;
-      tmp3 = bitOR tmp2 v_val_32;
-      tmp4 = bitOR tmp3 c_val_32
+      tmp0 = (AND) psr_val (0b11111111000011111111111111111111::word32);
+      tmp1 = (OR) tmp0 n_val_32;
+      tmp2 = (OR) tmp1 z_val_32;
+      tmp3 = (OR) tmp2 v_val_32;
+      tmp4 = (OR) tmp3 c_val_32
   in
   tmp4
 "
 
 text \<open>Update the ET, PIL fields of PSR. 
         Return the new value of PSR.\<close>
 definition update_PSR_et_pil :: "word1 \<Rightarrow> word4 \<Rightarrow> word32 \<Rightarrow> word32"
 where
 "update_PSR_et_pil et pil psr_val \<equiv>
-  let tmp0 = bitAND psr_val 0b111111111111111111111000011011111;
-      tmp1 = bitOR tmp0 (((ucast et)::word32) << 5);
-      tmp2 = bitOR tmp1 (((ucast pil)::word32) << 8)
+  let tmp0 = (AND) psr_val 0b111111111111111111111000011011111;
+      tmp1 = (OR) tmp0 (((ucast et)::word32) << 5);
+      tmp2 = (OR) tmp1 (((ucast pil)::word32) << 8)
   in
   tmp2
 "
 
 text \<open>
    SPARC V8 architecture is organized in windows of 32 user registers.
    The data stored in a register is defined as a 32 bits word @{term reg_type}:
 \<close>
 type_synonym reg_type = "word32"
 
 text \<open>
   The access to the value of a CPU register of type @{term CPU_register} is
   defined by a total function @{term cpu_context}
 \<close>
 
 type_synonym cpu_context = "CPU_register \<Rightarrow> reg_type"
 
 text \<open>
   User registers are defined with the type @{term user_reg} represented by a 5 bits word.
 \<close>
 
 type_synonym user_reg_type = "word5"
 
 definition PSR_S ::"reg_type"
 where "PSR_S \<equiv> 6"
 text \<open>
   Each window context is defined by a total function @{term window_context} from @{term user_register} 
   to @{term reg_type} (32 bits word storing the actual value of the register).
 \<close>
 
 type_synonym window_context = "user_reg_type \<Rightarrow> reg_type"
 text \<open>
   The number of windows is implementation dependent. 
   The LEON architecture is composed of 16 different windows (a 4 bits word).
 \<close>
 
 definition NWINDOWS :: "int"
 where "NWINDOWS \<equiv> 8"
 
 text \<open>Maximum number of windows is 32 in SPARCv8.\<close>
 type_synonym ('a) window_size = "'a word"
 
 text \<open>
 Finally the user context is defined by another total function @{term user_context} from 
 @{term window_size} to @{term window_context}. That is, the user context is a function taking as
 argument a register set window and a register within that window, and it returns the value stored
 in that user register.
 \<close>
 type_synonym ('a) user_context = "('a) window_size \<Rightarrow> window_context"
 
 datatype sys_reg = 
          CCR    \<comment> \<open>Cache control register\<close>
         |ICCR   \<comment> \<open>Instruction cache configuration register\<close>
         |DCCR   \<comment> \<open>Data cache configuration register\<close>
 
 type_synonym sys_context = "sys_reg \<Rightarrow> reg_type"
 
 text\<open>
 The memory model is defined by a total function from 32 bits words to 8 bits words
 \<close>
 type_synonym asi_type = "word8"
 
 text \<open>
  The memory is defined as a function from page address to page, which is also defined
   as a function from physical address to @{term "machine_word"}
 \<close>
 
 type_synonym mem_val_type = "word8"
 type_synonym mem_context = "asi_type \<Rightarrow> phys_address \<Rightarrow> mem_val_type option"
 
 type_synonym cache_tag = "word20"
 type_synonym cache_line_size = "word12"
 type_synonym cache_type = "(cache_tag \<times> cache_line_size)"
 type_synonym cache_context = "cache_type \<Rightarrow> mem_val_type option"
 
 text \<open>The delayed-write pool generated from write state register instructions.\<close>
 type_synonym delayed_write_pool = "(int \<times> reg_type \<times> CPU_register) list"
 
 definition DELAYNUM :: "int"
 where "DELAYNUM \<equiv> 0"
 
 text \<open>Convert a set to a list.\<close>
 definition list_of_set :: "'a set \<Rightarrow> 'a list"
   where "list_of_set s = (SOME l. set l = s)"
 
 lemma set_list_of_set: "finite s \<Longrightarrow> set (list_of_set s) = s"
 unfolding list_of_set_def 
 by (metis (mono_tags) finite_list some_eq_ex)
 
 type_synonym ANNUL = "bool"
 type_synonym RESET_TRAP = "bool"
 type_synonym EXECUTE_MODE = "bool"
 type_synonym RESET_MODE = "bool"
 type_synonym ERROR_MODE = "bool"
 type_synonym TICC_TRAP_TYPE = "word7"
 type_synonym INTERRUPT_LEVEL = "word3"
 type_synonym STORE_BARRIER_PENDING = "bool"
 
 text \<open>The processor asserts this signal to ensure that the
 memory system will not process another SWAP or
 LDSTUB operation to the same memory byte.\<close>
 type_synonym pb_block_ldst_byte = "virtua_address \<Rightarrow> bool"
 
 text\<open>The processor asserts this signal to ensure that the
 memory system will not process another SWAP or
 LDSTUB operation to the same memory word.\<close>
 type_synonym pb_block_ldst_word = "virtua_address \<Rightarrow> bool"
 
 record sparc_state_var =
 annul:: ANNUL
 resett:: RESET_TRAP
 exe:: EXECUTE_MODE
 reset:: RESET_MODE
 err:: ERROR_MODE
 ticc:: TICC_TRAP_TYPE
 itrpt_lvl:: INTERRUPT_LEVEL
 st_bar:: STORE_BARRIER_PENDING
 atm_ldst_byte:: pb_block_ldst_byte
 atm_ldst_word:: pb_block_ldst_word
 
 definition get_annul :: "sparc_state_var \<Rightarrow> bool"
 where "get_annul v \<equiv> annul v"
 
 definition get_reset_trap :: "sparc_state_var \<Rightarrow> bool"
 where "get_reset_trap v \<equiv> resett v"
 
 definition get_exe_mode :: "sparc_state_var \<Rightarrow> bool"
 where "get_exe_mode v \<equiv> exe v"
 
 definition get_reset_mode :: "sparc_state_var \<Rightarrow> bool"
 where "get_reset_mode v \<equiv> reset v"
 
 definition get_err_mode :: "sparc_state_var \<Rightarrow> bool"
 where "get_err_mode v \<equiv> err v"
 
 definition get_ticc_trap_type :: "sparc_state_var \<Rightarrow> word7"
 where "get_ticc_trap_type v \<equiv> ticc v"
 
 definition get_interrupt_level :: "sparc_state_var \<Rightarrow> word3"
 where "get_interrupt_level v \<equiv> itrpt_lvl v"
 
 definition get_store_barrier_pending :: "sparc_state_var \<Rightarrow> bool"
 where "get_store_barrier_pending v \<equiv> st_bar v"
 
 definition write_annul :: "bool \<Rightarrow> sparc_state_var \<Rightarrow> sparc_state_var"
 where "write_annul b v \<equiv> v\<lparr>annul := b\<rparr>"
 
 definition write_reset_trap :: "bool \<Rightarrow> sparc_state_var \<Rightarrow> sparc_state_var"
 where "write_reset_trap b v \<equiv> v\<lparr>resett := b\<rparr>"
 
 definition write_exe_mode :: "bool \<Rightarrow> sparc_state_var \<Rightarrow> sparc_state_var"
 where "write_exe_mode b v \<equiv> v\<lparr>exe := b\<rparr>"
 
 definition write_reset_mode :: "bool \<Rightarrow> sparc_state_var \<Rightarrow> sparc_state_var"
 where "write_reset_mode b v \<equiv> v\<lparr>reset := b\<rparr>"
 
 definition write_err_mode :: "bool \<Rightarrow> sparc_state_var \<Rightarrow> sparc_state_var"
 where "write_err_mode b v \<equiv> v\<lparr>err := b\<rparr>"
 
 definition write_ticc_trap_type :: "word7 \<Rightarrow> sparc_state_var \<Rightarrow> sparc_state_var"
 where "write_ticc_trap_type w v \<equiv> v\<lparr>ticc := w\<rparr>"
 
 definition write_interrupt_level :: "word3 \<Rightarrow> sparc_state_var \<Rightarrow> sparc_state_var"
 where "write_interrupt_level w v \<equiv> v\<lparr>itrpt_lvl := w\<rparr>"
 
 definition write_store_barrier_pending :: "bool \<Rightarrow> sparc_state_var \<Rightarrow> sparc_state_var"
 where "write_store_barrier_pending b v \<equiv> v\<lparr>st_bar := b\<rparr>"
 
 text \<open>Given a word7 value, find the highest bit,
         and fill the left bits to be the highest bit.\<close>
 definition sign_ext7::"word7 \<Rightarrow> word32"
 where
 "sign_ext7 w \<equiv> 
-  let highest_bit = (bitAND w 0b1000000) >> 6 in
+  let highest_bit = ((AND) w 0b1000000) >> 6 in
   if highest_bit = 0 then
     (ucast w)::word32
-  else bitOR ((ucast w)::word32) 0b11111111111111111111111110000000
+  else (OR) ((ucast w)::word32) 0b11111111111111111111111110000000
 "
 
 definition zero_ext8 :: "word8 \<Rightarrow> word32"
 where
 "zero_ext8 w \<equiv> (ucast w)::word32
 "
 
 text \<open>Given a word8 value, find the highest bit,
         and fill the left bits to be the highest bit.\<close>
 definition sign_ext8::"word8 \<Rightarrow> word32"
 where
 "sign_ext8 w \<equiv> 
-  let highest_bit = (bitAND w 0b10000000) >> 7 in
+  let highest_bit = ((AND) w 0b10000000) >> 7 in
   if highest_bit = 0 then
     (ucast w)::word32
-  else bitOR ((ucast w)::word32) 0b11111111111111111111111100000000
+  else (OR) ((ucast w)::word32) 0b11111111111111111111111100000000
 "
 
 text \<open>Given a word13 value, find the highest bit,
         and fill the left bits to be the highest bit.\<close>
 definition sign_ext13::"word13 \<Rightarrow> word32"
 where
 "sign_ext13 w \<equiv> 
-  let highest_bit = (bitAND w 0b1000000000000) >> 12 in
+  let highest_bit = ((AND) w 0b1000000000000) >> 12 in
   if highest_bit = 0 then
     (ucast w)::word32
-  else bitOR ((ucast w)::word32) 0b11111111111111111110000000000000
+  else (OR) ((ucast w)::word32) 0b11111111111111111110000000000000
 "
 
 definition zero_ext16 :: "word16 \<Rightarrow> word32"
 where
 "zero_ext16 w \<equiv> (ucast w)::word32
 "
 
 text \<open>Given a word16 value, find the highest bit,
         and fill the left bits to be the highest bit.\<close>
 definition sign_ext16::"word16 \<Rightarrow> word32"
 where
 "sign_ext16 w \<equiv> 
-  let highest_bit = (bitAND w 0b1000000000000000) >> 15 in
+  let highest_bit = ((AND) w 0b1000000000000000) >> 15 in
   if highest_bit = 0 then
     (ucast w)::word32
-  else bitOR ((ucast w)::word32) 0b11111111111111110000000000000000
+  else (OR) ((ucast w)::word32) 0b11111111111111110000000000000000
 "
 
 text \<open>Given a word22 value, find the highest bit,
         and fill the left bits to tbe the highest bit.\<close>
 definition sign_ext22::"word22 \<Rightarrow> word32"
 where
 "sign_ext22 w \<equiv>
-  let highest_bit = (bitAND w 0b1000000000000000000000) >> 21 in
+  let highest_bit = ((AND) w 0b1000000000000000000000) >> 21 in
   if highest_bit = 0 then
     (ucast w)::word32
-  else bitOR ((ucast w)::word32) 0b11111111110000000000000000000000
+  else (OR) ((ucast w)::word32) 0b11111111110000000000000000000000
 "
 
 text \<open>Given a word24 value, find the highest bit,
         and fill the left bits to tbe the highest bit.\<close>
 definition sign_ext24::"word24 \<Rightarrow> word32"
 where
 "sign_ext24 w \<equiv>
-  let highest_bit = (bitAND w 0b100000000000000000000000) >> 23 in
+  let highest_bit = ((AND) w 0b100000000000000000000000) >> 23 in
   if highest_bit = 0 then
     (ucast w)::word32
-  else bitOR ((ucast w)::word32) 0b11111111000000000000000000000000
+  else (OR) ((ucast w)::word32) 0b11111111000000000000000000000000
 "
 
 text\<open>
 Operations to be defined.
 The SPARC V8 architecture is composed of the following set of instructions:
   \<^item> Load Integer Instructions
   \<^item> Load Floating-point Instructions
   \<^item> Load Coprocessor Instructions
   \<^item> Store Integer Instructions
   \<^item> Store Floating-point Instructions
   \<^item> Store Coprocessor Instructions
   \<^item> Atomic Load-Store Unsigned Byte Instructions
   \<^item> SWAP Register With Memory Instruction
   \<^item> SETHI Instructions
   \<^item> NOP Instruction
   \<^item> Logical Instructions
   \<^item> Shift Instructions
   \<^item> Add Instructions
   \<^item> Tagged Add Instructions
   \<^item> Subtract Instructions
   \<^item> Tagged Subtract Instructions
   \<^item> Multiply Step Instruction
   \<^item> Multiply Instructions
   \<^item> Divide Instructions
   \<^item> SAVE and RESTORE Instructions
   \<^item> Branch on Integer Condition Codes Instructions
   \<^item> Branch on Floating-point Condition Codes Instructions
   \<^item> Branch on Coprocessor Condition Codes Instructions
   \<^item> Call and Link Instruction
   \<^item> Jump and Link Instruction
   \<^item> Return from Trap Instruction
   \<^item> Trap on Integer Condition Codes Instructions
   \<^item> Read State Register Instructions
   \<^item> Write State Register Instructions
   \<^item> STBAR Instruction
   \<^item> Unimplemented Instruction
   \<^item> Flush Instruction Memory
   \<^item> Floating-point Operate (FPop) Instructions
   \<^item> Convert Integer to Floating point Instructions
   \<^item> Convert Floating point to Integer Instructions
   \<^item> Convert Between Floating-point Formats Instructions
   \<^item> Floating-point Move Instructions
   \<^item> Floating-point Square Root Instructions
   \<^item> Floating-point Add and Subtract Instructions
   \<^item> Floating-point Multiply and Divide Instructions
   \<^item> Floating-point Compare Instructions
   \<^item> Coprocessor Operate Instructions
 \<close>
 
 text \<open>The CALL instruction.\<close>
 datatype call_type = CALL \<comment> \<open>Call and Link\<close>
 
 text \<open>The SETHI instruction.\<close>
 datatype sethi_type = SETHI    \<comment> \<open>Set High 22 bits of r Register\<close>
 
 text \<open>The NOP instruction.\<close>
 datatype nop_type = NOP      \<comment> \<open>No Operation\<close>
 
 text \<open>The Branch on integer condition codes instructions.\<close> 
 datatype bicc_type = 
   BE       \<comment> \<open>Branch on Equal\<close>
  | BNE      \<comment> \<open>Branch on Not Equal\<close>
  | BGU      \<comment> \<open>Branch on Greater Unsigned\<close>
  | BLE      \<comment> \<open>Branch on Less or Equal\<close>
  | BL       \<comment> \<open>Branch on Less\<close>
  | BGE      \<comment> \<open>Branch on Greater or Equal\<close>
  | BNEG     \<comment> \<open>Branch on Negative\<close>
  | BG       \<comment> \<open>Branch on Greater\<close>
  | BCS      \<comment> \<open>Branch on Carry Set (Less than, Unsigned)\<close>
  | BLEU     \<comment> \<open>Branch on Less or Equal Unsigned\<close>
  | BCC      \<comment> \<open>Branch on Carry Clear (Greater than or Equal, Unsigned)\<close>
  | BA       \<comment> \<open>Branch Always\<close>
  | BN       \<comment> \<open>Branch Never\<close> \<comment> \<open>Added for unconditional branches\<close>
  | BPOS     \<comment> \<open>Branch on Positive\<close>
  | BVC      \<comment> \<open>Branch on Overflow Clear\<close>
  | BVS      \<comment> \<open>Branch on Overflow Set\<close>
 
 text \<open>Memory instructions. That is, load and store.\<close>
 datatype load_store_type =
   LDSB     \<comment> \<open>Load Signed Byte\<close>
  | LDUB     \<comment> \<open>Load Unsigned Byte\<close>
  | LDUBA    \<comment> \<open>Load Unsigned Byte from Alternate space\<close>
  | LDUH     \<comment> \<open>Load Unsigned Halfword\<close>
  | LD       \<comment> \<open>Load Word\<close>
  | LDA      \<comment> \<open>Load Word from Alternate space\<close>
  | LDD      \<comment> \<open>Load Doubleword\<close>
  | STB      \<comment> \<open>Store Byte\<close>
  | STH      \<comment> \<open>Store Halfword\<close>
  | ST       \<comment> \<open>Store Word\<close>
  | STA      \<comment> \<open>Store Word into Alternate space\<close>
  | STD      \<comment> \<open>Store Doubleword\<close>
  | LDSBA    \<comment> \<open>Load Signed Byte from Alternate space\<close>
  | LDSH     \<comment> \<open>Load Signed Halfword\<close>
  | LDSHA    \<comment> \<open>Load Signed Halfword from Alternate space\<close>
  | LDUHA    \<comment> \<open>Load Unsigned Halfword from Alternate space\<close>
  | LDDA     \<comment> \<open>Load Doubleword from Alternate space\<close>
  | STBA     \<comment> \<open>Store Byte into Alternate space\<close>
  | STHA     \<comment> \<open>Store Halfword into Alternate space\<close>
  | STDA     \<comment> \<open>Store Doubleword into Alternate space\<close>
  | LDSTUB   \<comment> \<open>Atomic Load Store Unsigned Byte\<close>
  | LDSTUBA  \<comment> \<open>Atomic Load Store Unsinged Byte in Alternate space\<close>
  | SWAP     \<comment> \<open>Swap r Register with Mmemory\<close>
  | SWAPA    \<comment> \<open>Swap r Register with Mmemory in Alternate space\<close>
  | FLUSH    \<comment> \<open>Flush Instruction Memory\<close>
  | STBAR    \<comment> \<open>Store Barrier\<close>
 
 text \<open>Arithmetic instructions.\<close>
 datatype arith_type =
   ADD      \<comment> \<open>Add\<close>
  | ADDcc    \<comment> \<open>Add and modify icc\<close>
  | ADDX     \<comment> \<open>Add with Carry\<close>
  | SUB      \<comment> \<open>Subtract\<close>
  | SUBcc    \<comment> \<open>Subtract and modify icc\<close>
  | SUBX     \<comment> \<open>Subtract with Carry\<close>
  | UMUL     \<comment> \<open>Unsigned Integer Multiply\<close>
  | SMUL     \<comment> \<open>Signed Integer Multiply\<close>
  | SMULcc   \<comment> \<open>Signed Integer Multiply and modify icc\<close>
  | UDIV     \<comment> \<open>Unsigned Integer Divide\<close>
  | UDIVcc   \<comment> \<open>Unsigned Integer Divide and modify icc\<close>
  | SDIV     \<comment> \<open>Signed Integer Divide\<close> 
  | ADDXcc   \<comment> \<open>Add with Carry and modify icc\<close>
  | TADDcc   \<comment> \<open>Tagged Add and modify icc\<close>
  | TADDccTV \<comment> \<open>Tagged Add and modify icc and Trap on overflow\<close>
  | SUBXcc   \<comment> \<open>Subtract with Carry and modify icc\<close>
  | TSUBcc   \<comment> \<open>Tagged Subtract and modify icc\<close>
  | TSUBccTV \<comment> \<open>Tagged Subtract and modify icc and Trap on overflow\<close>
  | MULScc   \<comment> \<open>Multiply Step and modify icc\<close>
  | UMULcc   \<comment> \<open>Unsigned Integer Multiply and modify icc\<close>
  | SDIVcc   \<comment> \<open>Signed Integer Divide and modify icc\<close>
 
 text \<open>Logical instructions.\<close>
 datatype logic_type =
   ANDs      \<comment> \<open>And\<close>
  | ANDcc    \<comment> \<open>And and modify icc\<close>
  | ANDN     \<comment> \<open>And Not\<close>
  | ANDNcc   \<comment> \<open>And Not and modify icc\<close>
  | ORs       \<comment> \<open>Inclusive-Or\<close>
  | ORcc     \<comment> \<open>Inclusive-Or and modify icc\<close>
  | ORN      \<comment> \<open>Inclusive Or Not\<close>
  | XORs      \<comment> \<open>Exclusive-Or\<close>
  | XNOR     \<comment> \<open>Exclusive-Nor\<close>
  | ORNcc    \<comment> \<open>Inclusive-Or Not and modify icc\<close>
  | XORcc    \<comment> \<open>Exclusive-Or and modify icc\<close>
  | XNORcc   \<comment> \<open>Exclusive-Nor and modify icc\<close>
  
 text \<open>Shift instructions.\<close>
 datatype shift_type =
   SLL      \<comment> \<open>Shift Left Logical\<close>
  | SRL      \<comment> \<open>Shift Right Logical\<close>
  | SRA      \<comment> \<open>Shift Right Arithmetic\<close> 
 
 text \<open>Other Control-transfer instructions.\<close>
 datatype ctrl_type = 
   JMPL     \<comment> \<open>Jump and Link\<close>
  | RETT     \<comment> \<open>Return from Trap\<close>
  | SAVE     \<comment> \<open>Save caller's window\<close>
  | RESTORE  \<comment> \<open>Restore caller's window\<close> 
 
 text \<open>Access state registers instructions.\<close>
 datatype sreg_type =
   RDASR    \<comment> \<open>Read Ancillary State Register\<close>
  | RDY      \<comment> \<open>Read Y Register\<close>
  | RDPSR    \<comment> \<open>Read Processor State Register\<close>
  | RDWIM    \<comment> \<open>Read Window Invalid Mask Register\<close>
  | RDTBR    \<comment> \<open>Read Trap Base Regiser\<close>
  | WRASR    \<comment> \<open>Write Ancillary State Register\<close>
  | WRY      \<comment> \<open>Write Y Register\<close>
  | WRPSR    \<comment> \<open>Write Processor State Register\<close>
  | WRWIM    \<comment> \<open>Write Window Invalid Mask Register\<close>
  | WRTBR    \<comment> \<open>Write Trap Base Register\<close> 
 
 text \<open>Unimplemented instruction.\<close>
 datatype uimp_type = UNIMP    \<comment> \<open>Unimplemented\<close> 
 
 text \<open>Trap on integer condition code instructions.\<close>
 datatype ticc_type =
  TA       \<comment> \<open>Trap Always\<close>
  | TN       \<comment> \<open>Trap Never\<close>
  | TNE      \<comment> \<open>Trap on Not Equal\<close>
  | TE       \<comment> \<open>Trap on Equal\<close>
  | TG       \<comment> \<open>Trap on Greater\<close>
  | TLE      \<comment> \<open>Trap on Less or Equal\<close>
  | TGE      \<comment> \<open>Trap on Greater or Equal\<close>
  | TL       \<comment> \<open>Trap on Less\<close>
  | TGU      \<comment> \<open>Trap on Greater Unsigned\<close>
  | TLEU     \<comment> \<open>Trap on Less or Equal Unsigned\<close>
  | TCC      \<comment> \<open>Trap on Carry Clear (Greater than or Equal, Unsigned)\<close>
  | TCS      \<comment> \<open>Trap on Carry Set (Less Than, Unsigned)\<close>
  | TPOS     \<comment> \<open>Trap on Postive\<close>
  | TNEG     \<comment> \<open>Trap on Negative\<close>
  | TVC      \<comment> \<open>Trap on Overflow Clear\<close>
  | TVS      \<comment> \<open>Trap on Overflow Set\<close>
 
 datatype sparc_operation =
   call_type call_type
  | sethi_type sethi_type
  | nop_type nop_type
  | bicc_type bicc_type
  | load_store_type load_store_type
  | arith_type arith_type
  | logic_type logic_type
  | shift_type shift_type
  | ctrl_type ctrl_type
  | sreg_type sreg_type
  | uimp_type uimp_type
  | ticc_type ticc_type
 
 datatype Trap = 
 reset 
 |data_store_error
 |instruction_access_MMU_miss
 |instruction_access_error
 |r_register_access_error
 |instruction_access_exception
 |privileged_instruction
 |illegal_instruction
 |unimplemented_FLUSH
 |watchpoint_detected
 |fp_disabled
 |cp_disabled
 |window_overflow
 |window_underflow
 |mem_address_not_aligned
 |fp_exception
 |cp_exception
 |data_access_error
 |data_access_MMU_miss
 |data_access_exception
 |tag_overflow
 |division_by_zero
 |trap_instruction
 |interrupt_level_n
 
 datatype Exception =
 \<comment> \<open>The following are processor states that are not in the instruction model,\<close>
 \<comment> \<open>but we MAY want to deal with these from hardware perspective.\<close>
 \<^cancel>\<open>|execute_mode\<close>
 \<^cancel>\<open>|reset_mode\<close>
 \<^cancel>\<open>|error_mode\<close>
 \<comment> \<open>The following are self-defined exceptions.\<close>
 invalid_cond_f2
 |invalid_op2_f2
 |illegal_instruction2 \<comment> \<open>when \<open>i = 0\<close> for load/store not from alternate space\<close>
 |invalid_op3_f3_op11
 |case_impossible
 |invalid_op3_f3_op10
 |invalid_op_f3
 |unsupported_instruction
 |fetch_instruction_error
 |invalid_trap_cond
 
 end